arch/arm/boot/dts/exynos5250.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5250 SoC device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
   8  * EXYNOS5250 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
  13  * additional nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include <dt-bindings/clock/exynos5250.h>
  21 #include "exynos5.dtsi"
  22 #include "exynos4-cpu-thermal.dtsi"
  23 #include <dt-bindings/clock/exynos-audss-clk.h>
  24
  25 / {
  26         compatible = "samsung,exynos5250", "samsung,exynos5";
  27
  28         aliases {
  29                 spi0 = &spi_0;
  30                 spi1 = &spi_1;
  31                 spi2 = &spi_2;
  32                 gsc0 = &gsc_0;
  33                 gsc1 = &gsc_1;
  34                 gsc2 = &gsc_2;
  35                 gsc3 = &gsc_3;
  36                 mshc0 = &mmc_0;
  37                 mshc1 = &mmc_1;
  38                 mshc2 = &mmc_2;
  39                 mshc3 = &mmc_3;
  40                 i2c4 = &i2c_4;
  41                 i2c5 = &i2c_5;
  42                 i2c6 = &i2c_6;
  43                 i2c7 = &i2c_7;
  44                 i2c8 = &i2c_8;
  45                 i2c9 = &i2c_9;
  46                 pinctrl0 = &pinctrl_0;
  47                 pinctrl1 = &pinctrl_1;
  48                 pinctrl2 = &pinctrl_2;
  49                 pinctrl3 = &pinctrl_3;
  50         };
  51
  52         cpus {
  53                 #address-cells = <1>;
  54                 #size-cells = <0>;
  55
  56                 cpu0: cpu@0 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <0>;
  60                         clock-frequency = <1700000000>;
  61                         clocks = <&clock CLK_ARM_CLK>;
  62                         clock-names = "cpu";
  63                         clock-latency = <140000>;
  64
  65                         operating-points = <
  66                                 1700000 1300000
  67                                 1600000 1250000
  68                                 1500000 1225000
  69                                 1400000 1200000
  70                                 1300000 1150000
  71                                 1200000 1125000
  72                                 1100000 1100000
  73                                 1000000 1075000
  74                                  900000 1050000
  75                                  800000 1025000
  76                                  700000 1012500
  77                                  600000 1000000
  78                                  500000  975000
  79                                  400000  950000
  80                                  300000  937500
  81                                  200000  925000
  82                         >;
  83                         cooling-min-level = <15>;
  84                         cooling-max-level = <9>;
  85                         #cooling-cells = <2>; /* min followed by max */
  86                 };
  87                 cpu@1 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a15";
  90                         reg = <1>;
  91                         clock-frequency = <1700000000>;
  92                 };
  93         };
  94
  95         soc: soc {
  96                 sysram@2020000 {
  97                         compatible = "mmio-sram";
  98                         reg = <0x02020000 0x30000>;
  99                         #address-cells = <1>;
 100                         #size-cells = <1>;
 101                         ranges = <0 0x02020000 0x30000>;
 102
 103                         smp-sysram@0 {
 104                                 compatible = "samsung,exynos4210-sysram";
 105                                 reg = <0x0 0x1000>;
 106                         };
 107
 108                         smp-sysram@2f000 {
 109                                 compatible = "samsung,exynos4210-sysram-ns";
 110                                 reg = <0x2f000 0x1000>;
 111                         };
 112                 };
 113
 114                 pd_gsc: gsc-power-domain@10044000 {
 115                         compatible = "samsung,exynos4210-pd";
 116                         reg = <0x10044000 0x20>;
 117                         #power-domain-cells = <0>;
 118                         label = "GSC";
 119                 };
 120
 121                 pd_mfc: mfc-power-domain@10044040 {
 122                         compatible = "samsung,exynos4210-pd";
 123                         reg = <0x10044040 0x20>;
 124                         #power-domain-cells = <0>;
 125                         label = "MFC";
 126                 };
 127
 128                 pd_disp1: disp1-power-domain@100440A0 {
 129                         compatible = "samsung,exynos4210-pd";
 130                         reg = <0x100440A0 0x20>;
 131                         #power-domain-cells = <0>;
 132                         label = "DISP1";
 133                         clocks = <&clock CLK_FIN_PLL>,
 134                                  <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
 135                                  <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
 136                         clock-names = "oscclk", "clk0", "clk1";
 137                 };
 138
 139                 clock: clock-controller@10010000 {
 140                         compatible = "samsung,exynos5250-clock";
 141                         reg = <0x10010000 0x30000>;
 142                         #clock-cells = <1>;
 143                 };
 144
 145                 clock_audss: audss-clock-controller@3810000 {
 146                         compatible = "samsung,exynos5250-audss-clock";
 147                         reg = <0x03810000 0x0C>;
 148                         #clock-cells = <1>;
 149                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
 150                                  <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
 151                         clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
 152                 };
 153
 154                 timer {
 155                         compatible = "arm,armv7-timer";
 156                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 157                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 158                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 159                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 160                         /*
 161                          * Unfortunately we need this since some versions
 162                          * of U-Boot on Exynos don't set the CNTFRQ register,
 163                          * so we need the value from DT.
 164                          */
 165                         clock-frequency = <24000000>;
 166                 };
 167
 168                 mct@101C0000 {
 169                         compatible = "samsung,exynos4210-mct";
 170                         reg = <0x101C0000 0x800>;
 171                         interrupt-controller;
 172                         #interrupt-cells = <2>;
 173                         interrupt-parent = <&mct_map>;
 174                         interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 175                                      <4 0>, <5 0>;
 176                         clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 177                         clock-names = "fin_pll", "mct";
 178
 179                         mct_map: mct-map {
 180                                 #interrupt-cells = <2>;
 181                                 #address-cells = <0>;
 182                                 #size-cells = <0>;
 183                                 interrupt-map = <0x0 0 &combiner 23 3>,
 184                                                 <0x1 0 &combiner 23 4>,
 185                                                 <0x2 0 &combiner 25 2>,
 186                                                 <0x3 0 &combiner 25 3>,
 187                                                 <0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
 188                                                 <0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
 189                         };
 190                 };
 191
 192                 pmu {
 193                         compatible = "arm,cortex-a15-pmu";
 194                         interrupt-parent = <&combiner>;
 195                         interrupts = <1 2>, <22 4>;
 196                 };
 197
 198                 pinctrl_0: pinctrl@11400000 {
 199                         compatible = "samsung,exynos5250-pinctrl";
 200                         reg = <0x11400000 0x1000>;
 201                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 202
 203                         wakup_eint: wakeup-interrupt-controller {
 204                                 compatible = "samsung,exynos4210-wakeup-eint";
 205                                 interrupt-parent = <&gic>;
 206                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 207                         };
 208                 };
 209
 210                 pinctrl_1: pinctrl@13400000 {
 211                         compatible = "samsung,exynos5250-pinctrl";
 212                         reg = <0x13400000 0x1000>;
 213                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 214                 };
 215
 216                 pinctrl_2: pinctrl@10d10000 {
 217                         compatible = "samsung,exynos5250-pinctrl";
 218                         reg = <0x10d10000 0x1000>;
 219                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 220                 };
 221
 222                 pinctrl_3: pinctrl@3860000 {
 223                         compatible = "samsung,exynos5250-pinctrl";
 224                         reg = <0x03860000 0x1000>;
 225                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 226                 };
 227
 228                 pmu_system_controller: system-controller@10040000 {
 229                         compatible = "samsung,exynos5250-pmu", "syscon";
 230                         reg = <0x10040000 0x5000>;
 231                         clock-names = "clkout16";
 232                         clocks = <&clock CLK_FIN_PLL>;
 233                         #clock-cells = <1>;
 234                         interrupt-controller;
 235                         #interrupt-cells = <3>;
 236                         interrupt-parent = <&gic>;
 237                 };
 238
 239                 watchdog@101D0000 {
 240                         compatible = "samsung,exynos5250-wdt";
 241                         reg = <0x101D0000 0x100>;
 242                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 243                         clocks = <&clock CLK_WDT>;
 244                         clock-names = "watchdog";
 245                         samsung,syscon-phandle = <&pmu_system_controller>;
 246                 };
 247
 248                 g2d@10850000 {
 249                         compatible = "samsung,exynos5250-g2d";
 250                         reg = <0x10850000 0x1000>;
 251                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 252                         clocks = <&clock CLK_G2D>;
 253                         clock-names = "fimg2d";
 254                         iommus = <&sysmmu_g2d>;
 255                 };
 256
 257                 mfc: codec@11000000 {
 258                         compatible = "samsung,mfc-v6";
 259                         reg = <0x11000000 0x10000>;
 260                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 261                         power-domains = <&pd_mfc>;
 262                         clocks = <&clock CLK_MFC>;
 263                         clock-names = "mfc";
 264                         iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 265                         iommu-names = "left", "right";
 266                 };
 267
 268                 rotator: rotator@11C00000 {
 269                         compatible = "samsung,exynos5250-rotator";
 270                         reg = <0x11C00000 0x64>;
 271                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 272                         clocks = <&clock CLK_ROTATOR>;
 273                         clock-names = "rotator";
 274                         iommus = <&sysmmu_rotator>;
 275                 };
 276
 277                 tmu: tmu@10060000 {
 278                         compatible = "samsung,exynos5250-tmu";
 279                         reg = <0x10060000 0x100>;
 280                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 281                         clocks = <&clock CLK_TMU>;
 282                         clock-names = "tmu_apbif";
 283                         #include "exynos4412-tmu-sensor-conf.dtsi"
 284                 };
 285
 286                 sata: sata@122F0000 {
 287                         compatible = "snps,dwc-ahci";
 288                         samsung,sata-freq = <66>;
 289                         reg = <0x122F0000 0x1ff>;
 290                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 291                         clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
 292                         clock-names = "sata", "sclk_sata";
 293                         phys = <&sata_phy>;
 294                         phy-names = "sata-phy";
 295                         status = "disabled";
 296                 };
 297
 298                 sata_phy: sata-phy@12170000 {
 299                         compatible = "samsung,exynos5250-sata-phy";
 300                         reg = <0x12170000 0x1ff>;
 301                         clocks = <&clock CLK_SATA_PHYCTRL>;
 302                         clock-names = "sata_phyctrl";
 303                         #phy-cells = <0>;
 304                         samsung,syscon-phandle = <&pmu_system_controller>;
 305                         status = "disabled";
 306                 };
 307
 308                 /* i2c_0-3 are defined in exynos5.dtsi */
 309                 i2c_4: i2c@12CA0000 {
 310                         compatible = "samsung,s3c2440-i2c";
 311                         reg = <0x12CA0000 0x100>;
 312                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 313                         #address-cells = <1>;
 314                         #size-cells = <0>;
 315                         clocks = <&clock CLK_I2C4>;
 316                         clock-names = "i2c";
 317                         pinctrl-names = "default";
 318                         pinctrl-0 = <&i2c4_bus>;
 319                         status = "disabled";
 320                 };
 321
 322                 i2c_5: i2c@12CB0000 {
 323                         compatible = "samsung,s3c2440-i2c";
 324                         reg = <0x12CB0000 0x100>;
 325                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 326                         #address-cells = <1>;
 327                         #size-cells = <0>;
 328                         clocks = <&clock CLK_I2C5>;
 329                         clock-names = "i2c";
 330                         pinctrl-names = "default";
 331                         pinctrl-0 = <&i2c5_bus>;
 332                         status = "disabled";
 333                 };
 334
 335                 i2c_6: i2c@12CC0000 {
 336                         compatible = "samsung,s3c2440-i2c";
 337                         reg = <0x12CC0000 0x100>;
 338                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                         clocks = <&clock CLK_I2C6>;
 342                         clock-names = "i2c";
 343                         pinctrl-names = "default";
 344                         pinctrl-0 = <&i2c6_bus>;
 345                         status = "disabled";
 346                 };
 347
 348                 i2c_7: i2c@12CD0000 {
 349                         compatible = "samsung,s3c2440-i2c";
 350                         reg = <0x12CD0000 0x100>;
 351                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 352                         #address-cells = <1>;
 353                         #size-cells = <0>;
 354                         clocks = <&clock CLK_I2C7>;
 355                         clock-names = "i2c";
 356                         pinctrl-names = "default";
 357                         pinctrl-0 = <&i2c7_bus>;
 358                         status = "disabled";
 359                 };
 360
 361                 i2c_8: i2c@12CE0000 {
 362                         compatible = "samsung,s3c2440-hdmiphy-i2c";
 363                         reg = <0x12CE0000 0x1000>;
 364                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                         clocks = <&clock CLK_I2C_HDMI>;
 368                         clock-names = "i2c";
 369                         status = "disabled";
 370
 371                         hdmiphy: hdmiphy@38 {
 372                                 compatible = "samsung,exynos4212-hdmiphy";
 373                                 reg = <0x38>;
 374                         };
 375                 };
 376
 377                 i2c_9: i2c@121D0000 {
 378                         compatible = "samsung,exynos5-sata-phy-i2c";
 379                         reg = <0x121D0000 0x100>;
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         clocks = <&clock CLK_SATA_PHYI2C>;
 383                         clock-names = "i2c";
 384                         status = "disabled";
 385                 };
 386
 387                 spi_0: spi@12d20000 {
 388                         compatible = "samsung,exynos4210-spi";
 389                         status = "disabled";
 390                         reg = <0x12d20000 0x100>;
 391                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 392                         dmas = <&pdma0 5
 393                                 &pdma0 4>;
 394                         dma-names = "tx", "rx";
 395                         #address-cells = <1>;
 396                         #size-cells = <0>;
 397                         clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 398                         clock-names = "spi", "spi_busclk0";
 399                         pinctrl-names = "default";
 400                         pinctrl-0 = <&spi0_bus>;
 401                 };
 402
 403                 spi_1: spi@12d30000 {
 404                         compatible = "samsung,exynos4210-spi";
 405                         status = "disabled";
 406                         reg = <0x12d30000 0x100>;
 407                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 408                         dmas = <&pdma1 5
 409                                 &pdma1 4>;
 410                         dma-names = "tx", "rx";
 411                         #address-cells = <1>;
 412                         #size-cells = <0>;
 413                         clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 414                         clock-names = "spi", "spi_busclk0";
 415                         pinctrl-names = "default";
 416                         pinctrl-0 = <&spi1_bus>;
 417                 };
 418
 419                 spi_2: spi@12d40000 {
 420                         compatible = "samsung,exynos4210-spi";
 421                         status = "disabled";
 422                         reg = <0x12d40000 0x100>;
 423                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 424                         dmas = <&pdma0 7
 425                                 &pdma0 6>;
 426                         dma-names = "tx", "rx";
 427                         #address-cells = <1>;
 428                         #size-cells = <0>;
 429                         clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 430                         clock-names = "spi", "spi_busclk0";
 431                         pinctrl-names = "default";
 432                         pinctrl-0 = <&spi2_bus>;
 433                 };
 434
 435                 mmc_0: mmc@12200000 {
 436                         compatible = "samsung,exynos5250-dw-mshc";
 437                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 438                         #address-cells = <1>;
 439                         #size-cells = <0>;
 440                         reg = <0x12200000 0x1000>;
 441                         clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 442                         clock-names = "biu", "ciu";
 443                         fifo-depth = <0x80>;
 444                         status = "disabled";
 445                 };
 446
 447                 mmc_1: mmc@12210000 {
 448                         compatible = "samsung,exynos5250-dw-mshc";
 449                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 450                         #address-cells = <1>;
 451                         #size-cells = <0>;
 452                         reg = <0x12210000 0x1000>;
 453                         clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 454                         clock-names = "biu", "ciu";
 455                         fifo-depth = <0x80>;
 456                         status = "disabled";
 457                 };
 458
 459                 mmc_2: mmc@12220000 {
 460                         compatible = "samsung,exynos5250-dw-mshc";
 461                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 462                         #address-cells = <1>;
 463                         #size-cells = <0>;
 464                         reg = <0x12220000 0x1000>;
 465                         clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 466                         clock-names = "biu", "ciu";
 467                         fifo-depth = <0x80>;
 468                         status = "disabled";
 469                 };
 470
 471                 mmc_3: mmc@12230000 {
 472                         compatible = "samsung,exynos5250-dw-mshc";
 473                         reg = <0x12230000 0x1000>;
 474                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 475                         #address-cells = <1>;
 476                         #size-cells = <0>;
 477                         clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 478                         clock-names = "biu", "ciu";
 479                         fifo-depth = <0x80>;
 480                         status = "disabled";
 481                 };
 482
 483                 i2s0: i2s@3830000 {
 484                         compatible = "samsung,s5pv210-i2s";
 485                         status = "disabled";
 486                         reg = <0x03830000 0x100>;
 487                         dmas = <&pdma0 10
 488                                 &pdma0 9
 489                                 &pdma0 8>;
 490                         dma-names = "tx", "rx", "tx-sec";
 491                         clocks = <&clock_audss EXYNOS_I2S_BUS>,
 492                                 <&clock_audss EXYNOS_I2S_BUS>,
 493                                 <&clock_audss EXYNOS_SCLK_I2S>;
 494                         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 495                         samsung,idma-addr = <0x03000000>;
 496                         pinctrl-names = "default";
 497                         pinctrl-0 = <&i2s0_bus>;
 498                 };
 499
 500                 i2s1: i2s@12D60000 {
 501                         compatible = "samsung,s3c6410-i2s";
 502                         status = "disabled";
 503                         reg = <0x12D60000 0x100>;
 504                         dmas = <&pdma1 12
 505                                 &pdma1 11>;
 506                         dma-names = "tx", "rx";
 507                         clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
 508                         clock-names = "iis", "i2s_opclk0";
 509                         pinctrl-names = "default";
 510                         pinctrl-0 = <&i2s1_bus>;
 511                 };
 512
 513                 i2s2: i2s@12D70000 {
 514                         compatible = "samsung,s3c6410-i2s";
 515                         status = "disabled";
 516                         reg = <0x12D70000 0x100>;
 517                         dmas = <&pdma0 12
 518                                 &pdma0 11>;
 519                         dma-names = "tx", "rx";
 520                         clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
 521                         clock-names = "iis", "i2s_opclk0";
 522                         pinctrl-names = "default";
 523                         pinctrl-0 = <&i2s2_bus>;
 524                 };
 525
 526                 usb_dwc3 {
 527                         compatible = "samsung,exynos5250-dwusb3";
 528                         clocks = <&clock CLK_USB3>;
 529                         clock-names = "usbdrd30";
 530                         #address-cells = <1>;
 531                         #size-cells = <1>;
 532                         ranges;
 533
 534                         usbdrd_dwc3: dwc3@12000000 {
 535                                 compatible = "synopsys,dwc3";
 536                                 reg = <0x12000000 0x10000>;
 537                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 538                                 phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
 539                                 phy-names = "usb2-phy", "usb3-phy";
 540                         };
 541                 };
 542
 543                 usbdrd_phy: phy@12100000 {
 544                         compatible = "samsung,exynos5250-usbdrd-phy";
 545                         reg = <0x12100000 0x100>;
 546                         clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
 547                         clock-names = "phy", "ref";
 548                         samsung,pmu-syscon = <&pmu_system_controller>;
 549                         #phy-cells = <1>;
 550                 };
 551
 552                 ehci: usb@12110000 {
 553                         compatible = "samsung,exynos4210-ehci";
 554                         reg = <0x12110000 0x100>;
 555                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 556
 557                         clocks = <&clock CLK_USB2>;
 558                         clock-names = "usbhost";
 559                         #address-cells = <1>;
 560                         #size-cells = <0>;
 561                         port@0 {
 562                                 reg = <0>;
 563                                 phys = <&usb2_phy_gen 1>;
 564                         };
 565                 };
 566
 567                 ohci: usb@12120000 {
 568                         compatible = "samsung,exynos4210-ohci";
 569                         reg = <0x12120000 0x100>;
 570                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 571
 572                         clocks = <&clock CLK_USB2>;
 573                         clock-names = "usbhost";
 574                         #address-cells = <1>;
 575                         #size-cells = <0>;
 576                         port@0 {
 577                                 reg = <0>;
 578                                 phys = <&usb2_phy_gen 1>;
 579                         };
 580                 };
 581
 582                 usb2_phy_gen: phy@12130000 {
 583                         compatible = "samsung,exynos5250-usb2-phy";
 584                         reg = <0x12130000 0x100>;
 585                         clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
 586                         clock-names = "phy", "ref";
 587                         #phy-cells = <1>;
 588                         samsung,sysreg-phandle = <&sysreg_system_controller>;
 589                         samsung,pmureg-phandle = <&pmu_system_controller>;
 590                 };
 591
 592                 amba {
 593                         #address-cells = <1>;
 594                         #size-cells = <1>;
 595                         compatible = "simple-bus";
 596                         interrupt-parent = <&gic>;
 597                         ranges;
 598
 599                         pdma0: pdma@121A0000 {
 600                                 compatible = "arm,pl330", "arm,primecell";
 601                                 reg = <0x121A0000 0x1000>;
 602                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 603                                 clocks = <&clock CLK_PDMA0>;
 604                                 clock-names = "apb_pclk";
 605                                 #dma-cells = <1>;
 606                                 #dma-channels = <8>;
 607                                 #dma-requests = <32>;
 608                         };
 609
 610                         pdma1: pdma@121B0000 {
 611                                 compatible = "arm,pl330", "arm,primecell";
 612                                 reg = <0x121B0000 0x1000>;
 613                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 614                                 clocks = <&clock CLK_PDMA1>;
 615                                 clock-names = "apb_pclk";
 616                                 #dma-cells = <1>;
 617                                 #dma-channels = <8>;
 618                                 #dma-requests = <32>;
 619                         };
 620
 621                         mdma0: mdma@10800000 {
 622                                 compatible = "arm,pl330", "arm,primecell";
 623                                 reg = <0x10800000 0x1000>;
 624                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 625                                 clocks = <&clock CLK_MDMA0>;
 626                                 clock-names = "apb_pclk";
 627                                 #dma-cells = <1>;
 628                                 #dma-channels = <8>;
 629                                 #dma-requests = <1>;
 630                         };
 631
 632                         mdma1: mdma@11C10000 {
 633                                 compatible = "arm,pl330", "arm,primecell";
 634                                 reg = <0x11C10000 0x1000>;
 635                                 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
 636                                 clocks = <&clock CLK_MDMA1>;
 637                                 clock-names = "apb_pclk";
 638                                 #dma-cells = <1>;
 639                                 #dma-channels = <8>;
 640                                 #dma-requests = <1>;
 641                         };
 642                 };
 643
 644                 gsc_0:  gsc@13e00000 {
 645                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 646                         reg = <0x13e00000 0x1000>;
 647                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 648                         power-domains = <&pd_gsc>;
 649                         clocks = <&clock CLK_GSCL0>;
 650                         clock-names = "gscl";
 651                         iommu = <&sysmmu_gsc0>;
 652                 };
 653
 654                 gsc_1:  gsc@13e10000 {
 655                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 656                         reg = <0x13e10000 0x1000>;
 657                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 658                         power-domains = <&pd_gsc>;
 659                         clocks = <&clock CLK_GSCL1>;
 660                         clock-names = "gscl";
 661                         iommu = <&sysmmu_gsc1>;
 662                 };
 663
 664                 gsc_2:  gsc@13e20000 {
 665                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 666                         reg = <0x13e20000 0x1000>;
 667                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 668                         power-domains = <&pd_gsc>;
 669                         clocks = <&clock CLK_GSCL2>;
 670                         clock-names = "gscl";
 671                         iommu = <&sysmmu_gsc2>;
 672                 };
 673
 674                 gsc_3:  gsc@13e30000 {
 675                         compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 676                         reg = <0x13e30000 0x1000>;
 677                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 678                         power-domains = <&pd_gsc>;
 679                         clocks = <&clock CLK_GSCL3>;
 680                         clock-names = "gscl";
 681                         iommu = <&sysmmu_gsc3>;
 682                 };
 683
 684                 hdmi: hdmi@14530000 {
 685                         compatible = "samsung,exynos4212-hdmi";
 686                         reg = <0x14530000 0x70000>;
 687                         power-domains = <&pd_disp1>;
 688                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 689                         clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 690                                  <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 691                                  <&clock CLK_MOUT_HDMI>;
 692                         clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 693                                         "sclk_hdmiphy", "mout_hdmi";
 694                         samsung,syscon-phandle = <&pmu_system_controller>;
 695                         phy = <&hdmiphy>;
 696                         status = "disabled";
 697                 };
 698
 699                 hdmicec: cec@101B0000 {
 700                         compatible = "samsung,s5p-cec";
 701                         reg = <0x101B0000 0x200>;
 702                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 703                         clocks = <&clock CLK_HDMI_CEC>;
 704                         clock-names = "hdmicec";
 705                         samsung,syscon-phandle = <&pmu_system_controller>;
 706                         hdmi-phandle = <&hdmi>;
 707                         pinctrl-names = "default";
 708                         pinctrl-0 = <&hdmi_cec>;
 709                         status = "disabled";
 710                 };
 711
 712                 mixer: mixer@14450000 {
 713                         compatible = "samsung,exynos5250-mixer";
 714                         reg = <0x14450000 0x10000>;
 715                         power-domains = <&pd_disp1>;
 716                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 717                         clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 718                                  <&clock CLK_SCLK_HDMI>;
 719                         clock-names = "mixer", "hdmi", "sclk_hdmi";
 720                         iommus = <&sysmmu_tv>;
 721                         status = "disabled";
 722                 };
 723
 724                 dp_phy: video-phy {
 725                         compatible = "samsung,exynos5250-dp-video-phy";
 726                         samsung,pmu-syscon = <&pmu_system_controller>;
 727                         #phy-cells = <0>;
 728                 };
 729
 730                 adc: adc@12D10000 {
 731                         compatible = "samsung,exynos-adc-v1";
 732                         reg = <0x12D10000 0x100>;
 733                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 734                         clocks = <&clock CLK_ADC>;
 735                         clock-names = "adc";
 736                         #io-channel-cells = <1>;
 737                         io-channel-ranges;
 738                         samsung,syscon-phandle = <&pmu_system_controller>;
 739                         status = "disabled";
 740                 };
 741
 742                 sss@10830000 {
 743                         compatible = "samsung,exynos4210-secss";
 744                         reg = <0x10830000 0x300>;
 745                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 746                         clocks = <&clock CLK_SSS>;
 747                         clock-names = "secss";
 748                 };
 749
 750                 sysmmu_g2d: sysmmu@10A60000 {
 751                         compatible = "samsung,exynos-sysmmu";
 752                         reg = <0x10A60000 0x1000>;
 753                         interrupt-parent = <&combiner>;
 754                         interrupts = <24 5>;
 755                         clock-names = "sysmmu", "master";
 756                         clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
 757                         #iommu-cells = <0>;
 758                 };
 759
 760                 sysmmu_mfc_r: sysmmu@11200000 {
 761                         compatible = "samsung,exynos-sysmmu";
 762                         reg = <0x11200000 0x1000>;
 763                         interrupt-parent = <&combiner>;
 764                         interrupts = <6 2>;
 765                         power-domains = <&pd_mfc>;
 766                         clock-names = "sysmmu", "master";
 767                         clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 768                         #iommu-cells = <0>;
 769                 };
 770
 771                 sysmmu_mfc_l: sysmmu@11210000 {
 772                         compatible = "samsung,exynos-sysmmu";
 773                         reg = <0x11210000 0x1000>;
 774                         interrupt-parent = <&combiner>;
 775                         interrupts = <8 5>;
 776                         power-domains = <&pd_mfc>;
 777                         clock-names = "sysmmu", "master";
 778                         clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 779                         #iommu-cells = <0>;
 780                 };
 781
 782                 sysmmu_rotator: sysmmu@11D40000 {
 783                         compatible = "samsung,exynos-sysmmu";
 784                         reg = <0x11D40000 0x1000>;
 785                         interrupt-parent = <&combiner>;
 786                         interrupts = <4 0>;
 787                         clock-names = "sysmmu", "master";
 788                         clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 789                         #iommu-cells = <0>;
 790                 };
 791
 792                 sysmmu_jpeg: sysmmu@11F20000 {
 793                         compatible = "samsung,exynos-sysmmu";
 794                         reg = <0x11F20000 0x1000>;
 795                         interrupt-parent = <&combiner>;
 796                         interrupts = <4 2>;
 797                         power-domains = <&pd_gsc>;
 798                         clock-names = "sysmmu", "master";
 799                         clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 800                         #iommu-cells = <0>;
 801                 };
 802
 803                 sysmmu_fimc_isp: sysmmu@13260000 {
 804                         compatible = "samsung,exynos-sysmmu";
 805                         reg = <0x13260000 0x1000>;
 806                         interrupt-parent = <&combiner>;
 807                         interrupts = <10 6>;
 808                         clock-names = "sysmmu";
 809                         clocks = <&clock CLK_SMMU_FIMC_ISP>;
 810                         #iommu-cells = <0>;
 811                 };
 812
 813                 sysmmu_fimc_drc: sysmmu@13270000 {
 814                         compatible = "samsung,exynos-sysmmu";
 815                         reg = <0x13270000 0x1000>;
 816                         interrupt-parent = <&combiner>;
 817                         interrupts = <11 6>;
 818                         clock-names = "sysmmu";
 819                         clocks = <&clock CLK_SMMU_FIMC_DRC>;
 820                         #iommu-cells = <0>;
 821                 };
 822
 823                 sysmmu_fimc_fd: sysmmu@132A0000 {
 824                         compatible = "samsung,exynos-sysmmu";
 825                         reg = <0x132A0000 0x1000>;
 826                         interrupt-parent = <&combiner>;
 827                         interrupts = <5 0>;
 828                         clock-names = "sysmmu";
 829                         clocks = <&clock CLK_SMMU_FIMC_FD>;
 830                         #iommu-cells = <0>;
 831                 };
 832
 833                 sysmmu_fimc_scc: sysmmu@13280000 {
 834                         compatible = "samsung,exynos-sysmmu";
 835                         reg = <0x13280000 0x1000>;
 836                         interrupt-parent = <&combiner>;
 837                         interrupts = <5 2>;
 838                         clock-names = "sysmmu";
 839                         clocks = <&clock CLK_SMMU_FIMC_SCC>;
 840                         #iommu-cells = <0>;
 841                 };
 842
 843                 sysmmu_fimc_scp: sysmmu@13290000 {
 844                         compatible = "samsung,exynos-sysmmu";
 845                         reg = <0x13290000 0x1000>;
 846                         interrupt-parent = <&combiner>;
 847                         interrupts = <3 6>;
 848                         clock-names = "sysmmu";
 849                         clocks = <&clock CLK_SMMU_FIMC_SCP>;
 850                         #iommu-cells = <0>;
 851                 };
 852
 853                 sysmmu_fimc_mcuctl: sysmmu@132B0000 {
 854                         compatible = "samsung,exynos-sysmmu";
 855                         reg = <0x132B0000 0x1000>;
 856                         interrupt-parent = <&combiner>;
 857                         interrupts = <5 4>;
 858                         clock-names = "sysmmu";
 859                         clocks = <&clock CLK_SMMU_FIMC_MCU>;
 860                         #iommu-cells = <0>;
 861                 };
 862
 863                 sysmmu_fimc_odc: sysmmu@132C0000 {
 864                         compatible = "samsung,exynos-sysmmu";
 865                         reg = <0x132C0000 0x1000>;
 866                         interrupt-parent = <&combiner>;
 867                         interrupts = <11 0>;
 868                         clock-names = "sysmmu";
 869                         clocks = <&clock CLK_SMMU_FIMC_ODC>;
 870                         #iommu-cells = <0>;
 871                 };
 872
 873                 sysmmu_fimc_dis0: sysmmu@132D0000 {
 874                         compatible = "samsung,exynos-sysmmu";
 875                         reg = <0x132D0000 0x1000>;
 876                         interrupt-parent = <&combiner>;
 877                         interrupts = <10 4>;
 878                         clock-names = "sysmmu";
 879                         clocks = <&clock CLK_SMMU_FIMC_DIS0>;
 880                         #iommu-cells = <0>;
 881                 };
 882
 883                 sysmmu_fimc_dis1: sysmmu@132E0000{
 884                         compatible = "samsung,exynos-sysmmu";
 885                         reg = <0x132E0000 0x1000>;
 886                         interrupt-parent = <&combiner>;
 887                         interrupts = <9 4>;
 888                         clock-names = "sysmmu";
 889                         clocks = <&clock CLK_SMMU_FIMC_DIS1>;
 890                         #iommu-cells = <0>;
 891                 };
 892
 893                 sysmmu_fimc_3dnr: sysmmu@132F0000 {
 894                         compatible = "samsung,exynos-sysmmu";
 895                         reg = <0x132F0000 0x1000>;
 896                         interrupt-parent = <&combiner>;
 897                         interrupts = <5 6>;
 898                         clock-names = "sysmmu";
 899                         clocks = <&clock CLK_SMMU_FIMC_3DNR>;
 900                         #iommu-cells = <0>;
 901                 };
 902
 903                 sysmmu_fimc_lite0: sysmmu@13C40000 {
 904                         compatible = "samsung,exynos-sysmmu";
 905                         reg = <0x13C40000 0x1000>;
 906                         interrupt-parent = <&combiner>;
 907                         interrupts = <3 4>;
 908                         power-domains = <&pd_gsc>;
 909                         clock-names = "sysmmu", "master";
 910                         clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
 911                         #iommu-cells = <0>;
 912                 };
 913
 914                 sysmmu_fimc_lite1: sysmmu@13C50000 {
 915                         compatible = "samsung,exynos-sysmmu";
 916                         reg = <0x13C50000 0x1000>;
 917                         interrupt-parent = <&combiner>;
 918                         interrupts = <24 1>;
 919                         power-domains = <&pd_gsc>;
 920                         clock-names = "sysmmu", "master";
 921                         clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
 922                         #iommu-cells = <0>;
 923                 };
 924
 925                 sysmmu_gsc0: sysmmu@13E80000 {
 926                         compatible = "samsung,exynos-sysmmu";
 927                         reg = <0x13E80000 0x1000>;
 928                         interrupt-parent = <&combiner>;
 929                         interrupts = <2 0>;
 930                         power-domains = <&pd_gsc>;
 931                         clock-names = "sysmmu", "master";
 932                         clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
 933                         #iommu-cells = <0>;
 934                 };
 935
 936                 sysmmu_gsc1: sysmmu@13E90000 {
 937                         compatible = "samsung,exynos-sysmmu";
 938                         reg = <0x13E90000 0x1000>;
 939                         interrupt-parent = <&combiner>;
 940                         interrupts = <2 2>;
 941                         power-domains = <&pd_gsc>;
 942                         clock-names = "sysmmu", "master";
 943                         clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
 944                         #iommu-cells = <0>;
 945                 };
 946
 947                 sysmmu_gsc2: sysmmu@13EA0000 {
 948                         compatible = "samsung,exynos-sysmmu";
 949                         reg = <0x13EA0000 0x1000>;
 950                         interrupt-parent = <&combiner>;
 951                         interrupts = <2 4>;
 952                         power-domains = <&pd_gsc>;
 953                         clock-names = "sysmmu", "master";
 954                         clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
 955                         #iommu-cells = <0>;
 956                 };
 957
 958                 sysmmu_gsc3: sysmmu@13EB0000 {
 959                         compatible = "samsung,exynos-sysmmu";
 960                         reg = <0x13EB0000 0x1000>;
 961                         interrupt-parent = <&combiner>;
 962                         interrupts = <2 6>;
 963                         power-domains = <&pd_gsc>;
 964                         clock-names = "sysmmu", "master";
 965                         clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
 966                         #iommu-cells = <0>;
 967                 };
 968
 969                 sysmmu_fimd1: sysmmu@14640000 {
 970                         compatible = "samsung,exynos-sysmmu";
 971                         reg = <0x14640000 0x1000>;
 972                         interrupt-parent = <&combiner>;
 973                         interrupts = <3 2>;
 974                         power-domains = <&pd_disp1>;
 975                         clock-names = "sysmmu", "master";
 976                         clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
 977                         #iommu-cells = <0>;
 978                 };
 979
 980                 sysmmu_tv: sysmmu@14650000 {
 981                         compatible = "samsung,exynos-sysmmu";
 982                         reg = <0x14650000 0x1000>;
 983                         interrupt-parent = <&combiner>;
 984                         interrupts = <7 4>;
 985                         power-domains = <&pd_disp1>;
 986                         clock-names = "sysmmu", "master";
 987                         clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
 988                         #iommu-cells = <0>;
 989                 };
 990         };
 991
 992         thermal-zones {
 993                 cpu_thermal: cpu-thermal {
 994                         polling-delay-passive = <0>;
 995                         polling-delay = <0>;
 996                         thermal-sensors = <&tmu 0>;
 997
 998                         cooling-maps {
 999                                 map0 {
1000                                      /* Corresponds to 800MHz at freq_table */
1001                                      cooling-device = <&cpu0 9 9>;
1002                                 };
1003                                 map1 {
1004                                      /* Corresponds to 200MHz at freq_table */
1005                                      cooling-device = <&cpu0 15 15>;
1006                                };
1007                        };
1008                 };
1009         };
1010 };
1011
1012 &dp {
1013         power-domains = <&pd_disp1>;
1014         clocks = <&clock CLK_DP>;
1015         clock-names = "dp";
1016         phys = <&dp_phy>;
1017         phy-names = "dp";
1018 };
1019
1020 &fimd {
1021         power-domains = <&pd_disp1>;
1022         clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
1023         clock-names = "sclk_fimd", "fimd";
1024         iommus = <&sysmmu_fimd1>;
1025 };
1026
1027 &i2c_0 {
1028         clocks = <&clock CLK_I2C0>;
1029         clock-names = "i2c";
1030         pinctrl-names = "default";
1031         pinctrl-0 = <&i2c0_bus>;
1032 };
1033
1034 &i2c_1 {
1035         clocks = <&clock CLK_I2C1>;
1036         clock-names = "i2c";
1037         pinctrl-names = "default";
1038         pinctrl-0 = <&i2c1_bus>;
1039 };
1040
1041 &i2c_2 {
1042         clocks = <&clock CLK_I2C2>;
1043         clock-names = "i2c";
1044         pinctrl-names = "default";
1045         pinctrl-0 = <&i2c2_bus>;
1046 };
1047
1048 &i2c_3 {
1049         clocks = <&clock CLK_I2C3>;
1050         clock-names = "i2c";
1051         pinctrl-names = "default";
1052         pinctrl-0 = <&i2c3_bus>;
1053 };
1054
1055 &pwm {
1056         clocks = <&clock CLK_PWM>;
1057         clock-names = "timers";
1058 };
1059
1060 &rtc {
1061         clocks = <&clock CLK_RTC>;
1062         clock-names = "rtc";
1063         interrupt-parent = <&pmu_system_controller>;
1064         status = "disabled";
1065 };
1066
1067 &serial_0 {
1068         clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
1069         clock-names = "uart", "clk_uart_baud0";
1070         dmas = <&pdma0 13>, <&pdma0 14>;
1071         dma-names = "rx", "tx";
1072 };
1073
1074 &serial_1 {
1075         clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
1076         clock-names = "uart", "clk_uart_baud0";
1077         dmas = <&pdma1 15>, <&pdma1 16>;
1078         dma-names = "rx", "tx";
1079 };
1080
1081 &serial_2 {
1082         clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
1083         clock-names = "uart", "clk_uart_baud0";
1084         dmas = <&pdma0 15>, <&pdma0 16>;
1085         dma-names = "rx", "tx";
1086 };
1087
1088 &serial_3 {
1089         clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
1090         clock-names = "uart", "clk_uart_baud0";
1091         dmas = <&pdma1 17>, <&pdma1 18>;
1092         dma-names = "rx", "tx";
1093 };
1094
1095 #include "exynos5250-pinctrl.dtsi"