arch/arm/boot/dts/exynos4210.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Samsung's Exynos4210 SoC device tree source
   4  *
   5  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   6  *              http://www.samsung.com
   7  * Copyright (c) 2010-2011 Linaro Ltd.
   8  *              www.linaro.org
   9  *
  10  * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
  11  * based board files can include this file and provide values for board specfic
  12  * bindings.
  13  *
  14  * Note: This file does not include device nodes for all the controllers in
  15  * Exynos4210 SoC. As device tree coverage for Exynos4210 increases, additional
  16  * nodes can be added to this file.
  17  */
  18
  19 #include "exynos4.dtsi"
  20 #include "exynos4210-pinctrl.dtsi"
  21 #include "exynos4-cpu-thermal.dtsi"
  22
  23 / {
  24         compatible = "samsung,exynos4210", "samsung,exynos4";
  25
  26         aliases {
  27                 pinctrl0 = &pinctrl_0;
  28                 pinctrl1 = &pinctrl_1;
  29                 pinctrl2 = &pinctrl_2;
  30         };
  31
  32         cpus {
  33                 #address-cells = <1>;
  34                 #size-cells = <0>;
  35
  36                 cpu0: cpu@900 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a9";
  39                         reg = <0x900>;
  40                         clocks = <&clock CLK_ARM_CLK>;
  41                         clock-names = "cpu";
  42                         clock-latency = <160000>;
  43
  44                         operating-points = <
  45                                 1200000 1250000
  46                                 1000000 1150000
  47                                 800000  1075000
  48                                 500000  975000
  49                                 400000  975000
  50                                 200000  950000
  51                         >;
  52                         cooling-min-level = <4>;
  53                         cooling-max-level = <2>;
  54                         #cooling-cells = <2>; /* min followed by max */
  55                 };
  56
  57                 cpu@901 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a9";
  60                         reg = <0x901>;
  61                 };
  62         };
  63
  64         sysram: sysram@2020000 {
  65                 compatible = "mmio-sram";
  66                 reg = <0x02020000 0x20000>;
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges = <0 0x02020000 0x20000>;
  70
  71                 smp-sysram@0 {
  72                         compatible = "samsung,exynos4210-sysram";
  73                         reg = <0x0 0x1000>;
  74                 };
  75
  76                 smp-sysram@1f000 {
  77                         compatible = "samsung,exynos4210-sysram-ns";
  78                         reg = <0x1f000 0x1000>;
  79                 };
  80         };
  81
  82         pd_lcd1: lcd1-power-domain@10023ca0 {
  83                 compatible = "samsung,exynos4210-pd";
  84                 reg = <0x10023CA0 0x20>;
  85                 #power-domain-cells = <0>;
  86                 label = "LCD1";
  87         };
  88
  89         l2c: l2-cache-controller@10502000 {
  90                 compatible = "arm,pl310-cache";
  91                 reg = <0x10502000 0x1000>;
  92                 cache-unified;
  93                 cache-level = <2>;
  94                 arm,tag-latency = <2 2 1>;
  95                 arm,data-latency = <2 2 1>;
  96         };
  97
  98         mct: mct@10050000 {
  99                 compatible = "samsung,exynos4210-mct";
 100                 reg = <0x10050000 0x800>;
 101                 interrupt-parent = <&mct_map>;
 102                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
 103                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
 104                 clock-names = "fin_pll", "mct";
 105
 106                 mct_map: mct-map {
 107                         #interrupt-cells = <1>;
 108                         #address-cells = <0>;
 109                         #size-cells = <0>;
 110                         interrupt-map = <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
 111                                         <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
 112                                         <2 &combiner 12 6>,
 113                                         <3 &combiner 12 7>,
 114                                         <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
 115                                         <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
 116                 };
 117         };
 118
 119         watchdog: watchdog@10060000 {
 120                 compatible = "samsung,s3c6410-wdt";
 121                 reg = <0x10060000 0x100>;
 122                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 123                 clocks = <&clock CLK_WDT>;
 124                 clock-names = "watchdog";
 125         };
 126
 127         clock: clock-controller@10030000 {
 128                 compatible = "samsung,exynos4210-clock";
 129                 reg = <0x10030000 0x20000>;
 130                 #clock-cells = <1>;
 131         };
 132
 133         pinctrl_0: pinctrl@11400000 {
 134                 compatible = "samsung,exynos4210-pinctrl";
 135                 reg = <0x11400000 0x1000>;
 136                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 137         };
 138
 139         pinctrl_1: pinctrl@11000000 {
 140                 compatible = "samsung,exynos4210-pinctrl";
 141                 reg = <0x11000000 0x1000>;
 142                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 143
 144                 wakup_eint: wakeup-interrupt-controller {
 145                         compatible = "samsung,exynos4210-wakeup-eint";
 146                         interrupt-parent = <&gic>;
 147                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 148                 };
 149         };
 150
 151         pinctrl_2: pinctrl@3860000 {
 152                 compatible = "samsung,exynos4210-pinctrl";
 153                 reg = <0x03860000 0x1000>;
 154         };
 155
 156         tmu: tmu@100c0000 {
 157                 compatible = "samsung,exynos4210-tmu";
 158                 interrupt-parent = <&combiner>;
 159                 reg = <0x100C0000 0x100>;
 160                 interrupts = <2 4>;
 161                 clocks = <&clock CLK_TMU_APBIF>;
 162                 clock-names = "tmu_apbif";
 163                 samsung,tmu_gain = <15>;
 164                 samsung,tmu_reference_voltage = <7>;
 165                 status = "disabled";
 166         };
 167
 168         thermal-zones {
 169                 cpu_thermal: cpu-thermal {
 170                         polling-delay-passive = <0>;
 171                         polling-delay = <0>;
 172                         thermal-sensors = <&tmu 0>;
 173
 174                         trips {
 175                               cpu_alert0: cpu-alert-0 {
 176                                       temperature = <85000>; /* millicelsius */
 177                               };
 178                               cpu_alert1: cpu-alert-1 {
 179                                       temperature = <100000>; /* millicelsius */
 180                               };
 181                               cpu_alert2: cpu-alert-2 {
 182                                       temperature = <110000>; /* millicelsius */
 183                               };
 184                         };
 185                 };
 186         };
 187
 188         g2d: g2d@12800000 {
 189                 compatible = "samsung,s5pv210-g2d";
 190                 reg = <0x12800000 0x1000>;
 191                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 192                 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
 193                 clock-names = "sclk_fimg2d", "fimg2d";
 194                 power-domains = <&pd_lcd0>;
 195                 iommus = <&sysmmu_g2d>;
 196         };
 197
 198         camera {
 199                 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 200                          <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 201                 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 202
 203                 fimc_0: fimc@11800000 {
 204                         samsung,pix-limits = <4224 8192 1920 4224>;
 205                         samsung,mainscaler-ext;
 206                         samsung,cam-if;
 207                 };
 208
 209                 fimc_1: fimc@11810000 {
 210                         samsung,pix-limits = <4224 8192 1920 4224>;
 211                         samsung,mainscaler-ext;
 212                         samsung,cam-if;
 213                 };
 214
 215                 fimc_2: fimc@11820000 {
 216                         samsung,pix-limits = <4224 8192 1920 4224>;
 217                         samsung,mainscaler-ext;
 218                         samsung,lcd-wb;
 219                 };
 220
 221                 fimc_3: fimc@11830000 {
 222                         samsung,pix-limits = <1920 8192 1366 1920>;
 223                         samsung,rotators = <0>;
 224                         samsung,mainscaler-ext;
 225                         samsung,lcd-wb;
 226                 };
 227         };
 228
 229         mixer: mixer@12c10000 {
 230                 clock-names = "mixer", "hdmi", "sclk_hdmi", "vp", "mout_mixer",
 231                         "sclk_mixer";
 232                 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
 233                         <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>,
 234                         <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
 235         };
 236
 237         ppmu_lcd1: ppmu_lcd1@12240000 {
 238                 compatible = "samsung,exynos-ppmu";
 239                 reg = <0x12240000 0x2000>;
 240                 clocks = <&clock CLK_PPMULCD1>;
 241                 clock-names = "ppmu";
 242                 status = "disabled";
 243         };
 244
 245         sysmmu_g2d: sysmmu@12a20000 {
 246                 compatible = "samsung,exynos-sysmmu";
 247                 reg = <0x12A20000 0x1000>;
 248                 interrupt-parent = <&combiner>;
 249                 interrupts = <4 7>;
 250                 clock-names = "sysmmu", "master";
 251                 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
 252                 power-domains = <&pd_lcd0>;
 253                 #iommu-cells = <0>;
 254         };
 255
 256         sysmmu_fimd1: sysmmu@12220000 {
 257                 compatible = "samsung,exynos-sysmmu";
 258                 interrupt-parent = <&combiner>;
 259                 reg = <0x12220000 0x1000>;
 260                 interrupts = <5 3>;
 261                 clock-names = "sysmmu", "master";
 262                 clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
 263                 power-domains = <&pd_lcd1>;
 264                 #iommu-cells = <0>;
 265         };
 266
 267         bus_dmc: bus_dmc {
 268                 compatible = "samsung,exynos-bus";
 269                 clocks = <&clock CLK_DIV_DMC>;
 270                 clock-names = "bus";
 271                 operating-points-v2 = <&bus_dmc_opp_table>;
 272                 status = "disabled";
 273         };
 274
 275         bus_acp: bus_acp {
 276                 compatible = "samsung,exynos-bus";
 277                 clocks = <&clock CLK_DIV_ACP>;
 278                 clock-names = "bus";
 279                 operating-points-v2 = <&bus_acp_opp_table>;
 280                 status = "disabled";
 281         };
 282
 283         bus_peri: bus_peri {
 284                 compatible = "samsung,exynos-bus";
 285                 clocks = <&clock CLK_ACLK100>;
 286                 clock-names = "bus";
 287                 operating-points-v2 = <&bus_peri_opp_table>;
 288                 status = "disabled";
 289         };
 290
 291         bus_fsys: bus_fsys {
 292                 compatible = "samsung,exynos-bus";
 293                 clocks = <&clock CLK_ACLK133>;
 294                 clock-names = "bus";
 295                 operating-points-v2 = <&bus_fsys_opp_table>;
 296                 status = "disabled";
 297         };
 298
 299         bus_display: bus_display {
 300                 compatible = "samsung,exynos-bus";
 301                 clocks = <&clock CLK_ACLK160>;
 302                 clock-names = "bus";
 303                 operating-points-v2 = <&bus_display_opp_table>;
 304                 status = "disabled";
 305         };
 306
 307         bus_lcd0: bus_lcd0 {
 308                 compatible = "samsung,exynos-bus";
 309                 clocks = <&clock CLK_ACLK200>;
 310                 clock-names = "bus";
 311                 operating-points-v2 = <&bus_leftbus_opp_table>;
 312                 status = "disabled";
 313         };
 314
 315         bus_leftbus: bus_leftbus {
 316                 compatible = "samsung,exynos-bus";
 317                 clocks = <&clock CLK_DIV_GDL>;
 318                 clock-names = "bus";
 319                 operating-points-v2 = <&bus_leftbus_opp_table>;
 320                 status = "disabled";
 321         };
 322
 323         bus_rightbus: bus_rightbus {
 324                 compatible = "samsung,exynos-bus";
 325                 clocks = <&clock CLK_DIV_GDR>;
 326                 clock-names = "bus";
 327                 operating-points-v2 = <&bus_leftbus_opp_table>;
 328                 status = "disabled";
 329         };
 330
 331         bus_mfc: bus_mfc {
 332                 compatible = "samsung,exynos-bus";
 333                 clocks = <&clock CLK_SCLK_MFC>;
 334                 clock-names = "bus";
 335                 operating-points-v2 = <&bus_leftbus_opp_table>;
 336                 status = "disabled";
 337         };
 338
 339         bus_dmc_opp_table: opp_table1 {
 340                 compatible = "operating-points-v2";
 341                 opp-shared;
 342
 343                 opp-134000000 {
 344                         opp-hz = /bits/ 64 <134000000>;
 345                         opp-microvolt = <1025000>;
 346                 };
 347                 opp-267000000 {
 348                         opp-hz = /bits/ 64 <267000000>;
 349                         opp-microvolt = <1050000>;
 350                 };
 351                 opp-400000000 {
 352                         opp-hz = /bits/ 64 <400000000>;
 353                         opp-microvolt = <1150000>;
 354                 };
 355         };
 356
 357         bus_acp_opp_table: opp_table2 {
 358                 compatible = "operating-points-v2";
 359                 opp-shared;
 360
 361                 opp-134000000 {
 362                         opp-hz = /bits/ 64 <134000000>;
 363                 };
 364                 opp-160000000 {
 365                         opp-hz = /bits/ 64 <160000000>;
 366                 };
 367                 opp-200000000 {
 368                         opp-hz = /bits/ 64 <200000000>;
 369                 };
 370         };
 371
 372         bus_peri_opp_table: opp_table3 {
 373                 compatible = "operating-points-v2";
 374                 opp-shared;
 375
 376                 opp-5000000 {
 377                         opp-hz = /bits/ 64 <5000000>;
 378                 };
 379                 opp-100000000 {
 380                         opp-hz = /bits/ 64 <100000000>;
 381                 };
 382         };
 383
 384         bus_fsys_opp_table: opp_table4 {
 385                 compatible = "operating-points-v2";
 386                 opp-shared;
 387
 388                 opp-10000000 {
 389                         opp-hz = /bits/ 64 <10000000>;
 390                 };
 391                 opp-134000000 {
 392                         opp-hz = /bits/ 64 <134000000>;
 393                 };
 394         };
 395
 396         bus_display_opp_table: opp_table5 {
 397                 compatible = "operating-points-v2";
 398                 opp-shared;
 399
 400                 opp-100000000 {
 401                         opp-hz = /bits/ 64 <100000000>;
 402                 };
 403                 opp-134000000 {
 404                         opp-hz = /bits/ 64 <134000000>;
 405                 };
 406                 opp-160000000 {
 407                         opp-hz = /bits/ 64 <160000000>;
 408                 };
 409         };
 410
 411         bus_leftbus_opp_table: opp_table6 {
 412                 compatible = "operating-points-v2";
 413                 opp-shared;
 414
 415                 opp-100000000 {
 416                         opp-hz = /bits/ 64 <100000000>;
 417                 };
 418                 opp-160000000 {
 419                         opp-hz = /bits/ 64 <160000000>;
 420                 };
 421                 opp-200000000 {
 422                         opp-hz = /bits/ 64 <200000000>;
 423                 };
 424         };
 425 };
 426
 427 &gic {
 428         cpu-offset = <0x8000>;
 429 };
 430
 431 &combiner {
 432         samsung,combiner-nr = <16>;
 433         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 434                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 435                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 436                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 437                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 438                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 439                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 440                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 441                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 442                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 443                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 444                      <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 445                      <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 446                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 447                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 448                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 449 };
 450
 451 &mdma1 {
 452         power-domains = <&pd_lcd0>;
 453 };
 454
 455 &pmu_system_controller {
 456         clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
 457                         "clkout4", "clkout8", "clkout9";
 458         clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
 459                 <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
 460                 <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>;
 461         #clock-cells = <1>;
 462 };
 463
 464 &rotator {
 465         power-domains = <&pd_lcd0>;
 466 };
 467
 468 &sysmmu_rotator {
 469         power-domains = <&pd_lcd0>;
 470 };