arch/arm/boot/dts/exynos4.dtsi

   1 /*
   2  * Samsung's Exynos4 SoC series common device tree source
   3  *
   4  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2010-2011 Linaro Ltd.
   7  *              www.linaro.org
   8  *
   9  * Samsung's Exynos4 SoC series device nodes are listed in this file.  Particular
  10  * SoCs from Exynos4 series can include this file and provide values for SoCs
  11  * specfic bindings.
  12  *
  13  * Note: This file does not include device nodes for all the controllers in
  14  * Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
  15  * nodes can be added to this file.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of the GNU General Public License version 2 as
  19  * published by the Free Software Foundation.
  20  */
  21
  22 #include <dt-bindings/clock/exynos4.h>
  23 #include <dt-bindings/clock/exynos-audss-clk.h>
  24 #include <dt-bindings/interrupt-controller/arm-gic.h>
  25 #include <dt-bindings/interrupt-controller/irq.h>
  26 #include "exynos-syscon-restart.dtsi"
  27
  28 / {
  29         interrupt-parent = <&gic>;
  30         #address-cells = <1>;
  31         #size-cells = <1>;
  32
  33         aliases {
  34                 spi0 = &spi_0;
  35                 spi1 = &spi_1;
  36                 spi2 = &spi_2;
  37                 i2c0 = &i2c_0;
  38                 i2c1 = &i2c_1;
  39                 i2c2 = &i2c_2;
  40                 i2c3 = &i2c_3;
  41                 i2c4 = &i2c_4;
  42                 i2c5 = &i2c_5;
  43                 i2c6 = &i2c_6;
  44                 i2c7 = &i2c_7;
  45                 i2c8 = &i2c_8;
  46                 csis0 = &csis_0;
  47                 csis1 = &csis_1;
  48                 fimc0 = &fimc_0;
  49                 fimc1 = &fimc_1;
  50                 fimc2 = &fimc_2;
  51                 fimc3 = &fimc_3;
  52                 serial0 = &serial_0;
  53                 serial1 = &serial_1;
  54                 serial2 = &serial_2;
  55                 serial3 = &serial_3;
  56         };
  57
  58         clock_audss: clock-controller@3810000 {
  59                 compatible = "samsung,exynos4210-audss-clock";
  60                 reg = <0x03810000 0x0C>;
  61                 #clock-cells = <1>;
  62                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
  63                          <&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;
  64                 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
  65         };
  66
  67         i2s0: i2s@3830000 {
  68                 compatible = "samsung,s5pv210-i2s";
  69                 reg = <0x03830000 0x100>;
  70                 clocks = <&clock_audss EXYNOS_I2S_BUS>,
  71                          <&clock_audss EXYNOS_DOUT_AUD_BUS>,
  72                          <&clock_audss EXYNOS_SCLK_I2S>;
  73                 clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
  74                 #clock-cells = <1>;
  75                 clock-output-names = "i2s_cdclk0";
  76                 dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
  77                 dma-names = "tx", "rx", "tx-sec";
  78                 samsung,idma-addr = <0x03000000>;
  79                 #sound-dai-cells = <1>;
  80                 status = "disabled";
  81         };
  82
  83         chipid@10000000 {
  84                 compatible = "samsung,exynos4210-chipid";
  85                 reg = <0x10000000 0x100>;
  86         };
  87
  88         scu: snoop-control-unit@10500000 {
  89                 compatible = "arm,cortex-a9-scu";
  90                 reg = <0x10500000 0x2000>;
  91         };
  92
  93         memory-controller@12570000 {
  94                 compatible = "samsung,exynos4210-srom";
  95                 reg = <0x12570000 0x14>;
  96         };
  97
  98         mipi_phy: video-phy {
  99                 compatible = "samsung,s5pv210-mipi-video-phy";
 100                 #phy-cells = <1>;
 101                 syscon = <&pmu_system_controller>;
 102         };
 103
 104         pd_mfc: mfc-power-domain@10023C40 {
 105                 compatible = "samsung,exynos4210-pd";
 106                 reg = <0x10023C40 0x20>;
 107                 #power-domain-cells = <0>;
 108                 label = "MFC";
 109         };
 110
 111         pd_g3d: g3d-power-domain@10023C60 {
 112                 compatible = "samsung,exynos4210-pd";
 113                 reg = <0x10023C60 0x20>;
 114                 #power-domain-cells = <0>;
 115                 label = "G3D";
 116         };
 117
 118         pd_lcd0: lcd0-power-domain@10023C80 {
 119                 compatible = "samsung,exynos4210-pd";
 120                 reg = <0x10023C80 0x20>;
 121                 #power-domain-cells = <0>;
 122                 label = "LCD0";
 123         };
 124
 125         pd_tv: tv-power-domain@10023C20 {
 126                 compatible = "samsung,exynos4210-pd";
 127                 reg = <0x10023C20 0x20>;
 128                 #power-domain-cells = <0>;
 129                 power-domains = <&pd_lcd0>;
 130                 label = "TV";
 131         };
 132
 133         pd_cam: cam-power-domain@10023C00 {
 134                 compatible = "samsung,exynos4210-pd";
 135                 reg = <0x10023C00 0x20>;
 136                 #power-domain-cells = <0>;
 137                 label = "CAM";
 138         };
 139
 140         pd_gps: gps-power-domain@10023CE0 {
 141                 compatible = "samsung,exynos4210-pd";
 142                 reg = <0x10023CE0 0x20>;
 143                 #power-domain-cells = <0>;
 144                 label = "GPS";
 145         };
 146
 147         pd_gps_alive: gps-alive-power-domain@10023D00 {
 148                 compatible = "samsung,exynos4210-pd";
 149                 reg = <0x10023D00 0x20>;
 150                 #power-domain-cells = <0>;
 151                 label = "GPS alive";
 152         };
 153
 154         gic: interrupt-controller@10490000 {
 155                 compatible = "arm,cortex-a9-gic";
 156                 #interrupt-cells = <3>;
 157                 interrupt-controller;
 158                 reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
 159         };
 160
 161         combiner: interrupt-controller@10440000 {
 162                 compatible = "samsung,exynos4210-combiner";
 163                 #interrupt-cells = <2>;
 164                 interrupt-controller;
 165                 reg = <0x10440000 0x1000>;
 166         };
 167
 168         pmu {
 169                 compatible = "arm,cortex-a9-pmu";
 170                 interrupt-parent = <&combiner>;
 171                 interrupts = <2 2>, <3 2>;
 172         };
 173
 174         sys_reg: syscon@10010000 {
 175                 compatible = "samsung,exynos4-sysreg", "syscon";
 176                 reg = <0x10010000 0x400>;
 177         };
 178
 179         pmu_system_controller: system-controller@10020000 {
 180                 compatible = "samsung,exynos4210-pmu", "syscon";
 181                 reg = <0x10020000 0x4000>;
 182                 interrupt-controller;
 183                 #interrupt-cells = <3>;
 184                 interrupt-parent = <&gic>;
 185         };
 186
 187         dsi_0: dsi@11C80000 {
 188                 compatible = "samsung,exynos4210-mipi-dsi";
 189                 reg = <0x11C80000 0x10000>;
 190                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 191                 power-domains = <&pd_lcd0>;
 192                 phys = <&mipi_phy 1>;
 193                 phy-names = "dsim";
 194                 clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
 195                 clock-names = "bus_clk", "sclk_mipi";
 196                 status = "disabled";
 197                 #address-cells = <1>;
 198                 #size-cells = <0>;
 199         };
 200
 201         camera {
 202                 compatible = "samsung,fimc", "simple-bus";
 203                 status = "disabled";
 204                 #address-cells = <1>;
 205                 #size-cells = <1>;
 206                 #clock-cells = <1>;
 207                 clock-output-names = "cam_a_clkout", "cam_b_clkout";
 208                 ranges;
 209
 210                 fimc_0: fimc@11800000 {
 211                         compatible = "samsung,exynos4210-fimc";
 212                         reg = <0x11800000 0x1000>;
 213                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 214                         clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
 215                         clock-names = "fimc", "sclk_fimc";
 216                         power-domains = <&pd_cam>;
 217                         samsung,sysreg = <&sys_reg>;
 218                         iommus = <&sysmmu_fimc0>;
 219                         status = "disabled";
 220                 };
 221
 222                 fimc_1: fimc@11810000 {
 223                         compatible = "samsung,exynos4210-fimc";
 224                         reg = <0x11810000 0x1000>;
 225                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 226                         clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
 227                         clock-names = "fimc", "sclk_fimc";
 228                         power-domains = <&pd_cam>;
 229                         samsung,sysreg = <&sys_reg>;
 230                         iommus = <&sysmmu_fimc1>;
 231                         status = "disabled";
 232                 };
 233
 234                 fimc_2: fimc@11820000 {
 235                         compatible = "samsung,exynos4210-fimc";
 236                         reg = <0x11820000 0x1000>;
 237                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 238                         clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
 239                         clock-names = "fimc", "sclk_fimc";
 240                         power-domains = <&pd_cam>;
 241                         samsung,sysreg = <&sys_reg>;
 242                         iommus = <&sysmmu_fimc2>;
 243                         status = "disabled";
 244                 };
 245
 246                 fimc_3: fimc@11830000 {
 247                         compatible = "samsung,exynos4210-fimc";
 248                         reg = <0x11830000 0x1000>;
 249                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 250                         clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
 251                         clock-names = "fimc", "sclk_fimc";
 252                         power-domains = <&pd_cam>;
 253                         samsung,sysreg = <&sys_reg>;
 254                         iommus = <&sysmmu_fimc3>;
 255                         status = "disabled";
 256                 };
 257
 258                 csis_0: csis@11880000 {
 259                         compatible = "samsung,exynos4210-csis";
 260                         reg = <0x11880000 0x4000>;
 261                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 262                         clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
 263                         clock-names = "csis", "sclk_csis";
 264                         bus-width = <4>;
 265                         power-domains = <&pd_cam>;
 266                         phys = <&mipi_phy 0>;
 267                         phy-names = "csis";
 268                         status = "disabled";
 269                         #address-cells = <1>;
 270                         #size-cells = <0>;
 271                 };
 272
 273                 csis_1: csis@11890000 {
 274                         compatible = "samsung,exynos4210-csis";
 275                         reg = <0x11890000 0x4000>;
 276                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 277                         clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
 278                         clock-names = "csis", "sclk_csis";
 279                         bus-width = <2>;
 280                         power-domains = <&pd_cam>;
 281                         phys = <&mipi_phy 2>;
 282                         phy-names = "csis";
 283                         status = "disabled";
 284                         #address-cells = <1>;
 285                         #size-cells = <0>;
 286                 };
 287         };
 288
 289         rtc: rtc@10070000 {
 290                 compatible = "samsung,s3c6410-rtc";
 291                 reg = <0x10070000 0x100>;
 292                 interrupt-parent = <&pmu_system_controller>;
 293                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 295                 clocks = <&clock CLK_RTC>;
 296                 clock-names = "rtc";
 297                 status = "disabled";
 298         };
 299
 300         keypad: keypad@100A0000 {
 301                 compatible = "samsung,s5pv210-keypad";
 302                 reg = <0x100A0000 0x100>;
 303                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&clock CLK_KEYIF>;
 305                 clock-names = "keypad";
 306                 status = "disabled";
 307         };
 308
 309         sdhci_0: sdhci@12510000 {
 310                 compatible = "samsung,exynos4210-sdhci";
 311                 reg = <0x12510000 0x100>;
 312                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
 314                 clock-names = "hsmmc", "mmc_busclk.2";
 315                 status = "disabled";
 316         };
 317
 318         sdhci_1: sdhci@12520000 {
 319                 compatible = "samsung,exynos4210-sdhci";
 320                 reg = <0x12520000 0x100>;
 321                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 322                 clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
 323                 clock-names = "hsmmc", "mmc_busclk.2";
 324                 status = "disabled";
 325         };
 326
 327         sdhci_2: sdhci@12530000 {
 328                 compatible = "samsung,exynos4210-sdhci";
 329                 reg = <0x12530000 0x100>;
 330                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 331                 clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
 332                 clock-names = "hsmmc", "mmc_busclk.2";
 333                 status = "disabled";
 334         };
 335
 336         sdhci_3: sdhci@12540000 {
 337                 compatible = "samsung,exynos4210-sdhci";
 338                 reg = <0x12540000 0x100>;
 339                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
 341                 clock-names = "hsmmc", "mmc_busclk.2";
 342                 status = "disabled";
 343         };
 344
 345         exynos_usbphy: exynos-usbphy@125B0000 {
 346                 compatible = "samsung,exynos4210-usb2-phy";
 347                 reg = <0x125B0000 0x100>;
 348                 samsung,pmureg-phandle = <&pmu_system_controller>;
 349                 clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
 350                 clock-names = "phy", "ref";
 351                 #phy-cells = <1>;
 352                 status = "disabled";
 353         };
 354
 355         hsotg: hsotg@12480000 {
 356                 compatible = "samsung,s3c6400-hsotg";
 357                 reg = <0x12480000 0x20000>;
 358                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 359                 clocks = <&clock CLK_USB_DEVICE>;
 360                 clock-names = "otg";
 361                 phys = <&exynos_usbphy 0>;
 362                 phy-names = "usb2-phy";
 363                 status = "disabled";
 364         };
 365
 366         ehci: ehci@12580000 {
 367                 compatible = "samsung,exynos4210-ehci";
 368                 reg = <0x12580000 0x100>;
 369                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 370                 clocks = <&clock CLK_USB_HOST>;
 371                 clock-names = "usbhost";
 372                 status = "disabled";
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 port@0 {
 376                         reg = <0>;
 377                         phys = <&exynos_usbphy 1>;
 378                         status = "disabled";
 379                 };
 380                 port@1 {
 381                         reg = <1>;
 382                         phys = <&exynos_usbphy 2>;
 383                         status = "disabled";
 384                 };
 385                 port@2 {
 386                         reg = <2>;
 387                         phys = <&exynos_usbphy 3>;
 388                         status = "disabled";
 389                 };
 390         };
 391
 392         ohci: ohci@12590000 {
 393                 compatible = "samsung,exynos4210-ohci";
 394                 reg = <0x12590000 0x100>;
 395                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 396                 clocks = <&clock CLK_USB_HOST>;
 397                 clock-names = "usbhost";
 398                 status = "disabled";
 399                 #address-cells = <1>;
 400                 #size-cells = <0>;
 401                 port@0 {
 402                         reg = <0>;
 403                         phys = <&exynos_usbphy 1>;
 404                         status = "disabled";
 405                 };
 406         };
 407
 408         i2s1: i2s@13960000 {
 409                 compatible = "samsung,s3c6410-i2s";
 410                 reg = <0x13960000 0x100>;
 411                 clocks = <&clock CLK_I2S1>;
 412                 clock-names = "iis";
 413                 #clock-cells = <1>;
 414                 clock-output-names = "i2s_cdclk1";
 415                 dmas = <&pdma1 12>, <&pdma1 11>;
 416                 dma-names = "tx", "rx";
 417                 #sound-dai-cells = <1>;
 418                 status = "disabled";
 419         };
 420
 421         i2s2: i2s@13970000 {
 422                 compatible = "samsung,s3c6410-i2s";
 423                 reg = <0x13970000 0x100>;
 424                 clocks = <&clock CLK_I2S2>;
 425                 clock-names = "iis";
 426                 #clock-cells = <1>;
 427                 clock-output-names = "i2s_cdclk2";
 428                 dmas = <&pdma0 14>, <&pdma0 13>;
 429                 dma-names = "tx", "rx";
 430                 #sound-dai-cells = <1>;
 431                 status = "disabled";
 432         };
 433
 434         mfc: codec@13400000 {
 435                 compatible = "samsung,mfc-v5";
 436                 reg = <0x13400000 0x10000>;
 437                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 438                 power-domains = <&pd_mfc>;
 439                 clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
 440                 clock-names = "mfc", "sclk_mfc";
 441                 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
 442                 iommu-names = "left", "right";
 443         };
 444
 445         serial_0: serial@13800000 {
 446                 compatible = "samsung,exynos4210-uart";
 447                 reg = <0x13800000 0x100>;
 448                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 449                 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
 450                 clock-names = "uart", "clk_uart_baud0";
 451                 dmas = <&pdma0 15>, <&pdma0 16>;
 452                 dma-names = "rx", "tx";
 453                 status = "disabled";
 454         };
 455
 456         serial_1: serial@13810000 {
 457                 compatible = "samsung,exynos4210-uart";
 458                 reg = <0x13810000 0x100>;
 459                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 460                 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
 461                 clock-names = "uart", "clk_uart_baud0";
 462                 dmas = <&pdma1 15>, <&pdma1 16>;
 463                 dma-names = "rx", "tx";
 464                 status = "disabled";
 465         };
 466
 467         serial_2: serial@13820000 {
 468                 compatible = "samsung,exynos4210-uart";
 469                 reg = <0x13820000 0x100>;
 470                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 471                 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
 472                 clock-names = "uart", "clk_uart_baud0";
 473                 dmas = <&pdma0 17>, <&pdma0 18>;
 474                 dma-names = "rx", "tx";
 475                 status = "disabled";
 476         };
 477
 478         serial_3: serial@13830000 {
 479                 compatible = "samsung,exynos4210-uart";
 480                 reg = <0x13830000 0x100>;
 481                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 482                 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
 483                 clock-names = "uart", "clk_uart_baud0";
 484                 dmas = <&pdma1 17>, <&pdma1 18>;
 485                 dma-names = "rx", "tx";
 486                 status = "disabled";
 487         };
 488
 489         i2c_0: i2c@13860000 {
 490                 #address-cells = <1>;
 491                 #size-cells = <0>;
 492                 compatible = "samsung,s3c2440-i2c";
 493                 reg = <0x13860000 0x100>;
 494                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 495                 clocks = <&clock CLK_I2C0>;
 496                 clock-names = "i2c";
 497                 pinctrl-names = "default";
 498                 pinctrl-0 = <&i2c0_bus>;
 499                 status = "disabled";
 500         };
 501
 502         i2c_1: i2c@13870000 {
 503                 #address-cells = <1>;
 504                 #size-cells = <0>;
 505                 compatible = "samsung,s3c2440-i2c";
 506                 reg = <0x13870000 0x100>;
 507                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 508                 clocks = <&clock CLK_I2C1>;
 509                 clock-names = "i2c";
 510                 pinctrl-names = "default";
 511                 pinctrl-0 = <&i2c1_bus>;
 512                 status = "disabled";
 513         };
 514
 515         i2c_2: i2c@13880000 {
 516                 #address-cells = <1>;
 517                 #size-cells = <0>;
 518                 compatible = "samsung,s3c2440-i2c";
 519                 reg = <0x13880000 0x100>;
 520                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 521                 clocks = <&clock CLK_I2C2>;
 522                 clock-names = "i2c";
 523                 pinctrl-names = "default";
 524                 pinctrl-0 = <&i2c2_bus>;
 525                 status = "disabled";
 526         };
 527
 528         i2c_3: i2c@13890000 {
 529                 #address-cells = <1>;
 530                 #size-cells = <0>;
 531                 compatible = "samsung,s3c2440-i2c";
 532                 reg = <0x13890000 0x100>;
 533                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 534                 clocks = <&clock CLK_I2C3>;
 535                 clock-names = "i2c";
 536                 pinctrl-names = "default";
 537                 pinctrl-0 = <&i2c3_bus>;
 538                 status = "disabled";
 539         };
 540
 541         i2c_4: i2c@138A0000 {
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 compatible = "samsung,s3c2440-i2c";
 545                 reg = <0x138A0000 0x100>;
 546                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 547                 clocks = <&clock CLK_I2C4>;
 548                 clock-names = "i2c";
 549                 pinctrl-names = "default";
 550                 pinctrl-0 = <&i2c4_bus>;
 551                 status = "disabled";
 552         };
 553
 554         i2c_5: i2c@138B0000 {
 555                 #address-cells = <1>;
 556                 #size-cells = <0>;
 557                 compatible = "samsung,s3c2440-i2c";
 558                 reg = <0x138B0000 0x100>;
 559                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 560                 clocks = <&clock CLK_I2C5>;
 561                 clock-names = "i2c";
 562                 pinctrl-names = "default";
 563                 pinctrl-0 = <&i2c5_bus>;
 564                 status = "disabled";
 565         };
 566
 567         i2c_6: i2c@138C0000 {
 568                 #address-cells = <1>;
 569                 #size-cells = <0>;
 570                 compatible = "samsung,s3c2440-i2c";
 571                 reg = <0x138C0000 0x100>;
 572                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 573                 clocks = <&clock CLK_I2C6>;
 574                 clock-names = "i2c";
 575                 pinctrl-names = "default";
 576                 pinctrl-0 = <&i2c6_bus>;
 577                 status = "disabled";
 578         };
 579
 580         i2c_7: i2c@138D0000 {
 581                 #address-cells = <1>;
 582                 #size-cells = <0>;
 583                 compatible = "samsung,s3c2440-i2c";
 584                 reg = <0x138D0000 0x100>;
 585                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 586                 clocks = <&clock CLK_I2C7>;
 587                 clock-names = "i2c";
 588                 pinctrl-names = "default";
 589                 pinctrl-0 = <&i2c7_bus>;
 590                 status = "disabled";
 591         };
 592
 593         i2c_8: i2c@138E0000 {
 594                 #address-cells = <1>;
 595                 #size-cells = <0>;
 596                 compatible = "samsung,s3c2440-hdmiphy-i2c";
 597                 reg = <0x138E0000 0x100>;
 598                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 599                 clocks = <&clock CLK_I2C_HDMI>;
 600                 clock-names = "i2c";
 601                 status = "disabled";
 602
 603                 hdmi_i2c_phy: hdmiphy@38 {
 604                         compatible = "exynos4210-hdmiphy";
 605                         reg = <0x38>;
 606                 };
 607         };
 608
 609         spi_0: spi@13920000 {
 610                 compatible = "samsung,exynos4210-spi";
 611                 reg = <0x13920000 0x100>;
 612                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 613                 dmas = <&pdma0 7>, <&pdma0 6>;
 614                 dma-names = "tx", "rx";
 615                 #address-cells = <1>;
 616                 #size-cells = <0>;
 617                 clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
 618                 clock-names = "spi", "spi_busclk0";
 619                 pinctrl-names = "default";
 620                 pinctrl-0 = <&spi0_bus>;
 621                 status = "disabled";
 622         };
 623
 624         spi_1: spi@13930000 {
 625                 compatible = "samsung,exynos4210-spi";
 626                 reg = <0x13930000 0x100>;
 627                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 628                 dmas = <&pdma1 7>, <&pdma1 6>;
 629                 dma-names = "tx", "rx";
 630                 #address-cells = <1>;
 631                 #size-cells = <0>;
 632                 clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
 633                 clock-names = "spi", "spi_busclk0";
 634                 pinctrl-names = "default";
 635                 pinctrl-0 = <&spi1_bus>;
 636                 status = "disabled";
 637         };
 638
 639         spi_2: spi@13940000 {
 640                 compatible = "samsung,exynos4210-spi";
 641                 reg = <0x13940000 0x100>;
 642                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 643                 dmas = <&pdma0 9>, <&pdma0 8>;
 644                 dma-names = "tx", "rx";
 645                 #address-cells = <1>;
 646                 #size-cells = <0>;
 647                 clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
 648                 clock-names = "spi", "spi_busclk0";
 649                 pinctrl-names = "default";
 650                 pinctrl-0 = <&spi2_bus>;
 651                 status = "disabled";
 652         };
 653
 654         pwm: pwm@139D0000 {
 655                 compatible = "samsung,exynos4210-pwm";
 656                 reg = <0x139D0000 0x1000>;
 657                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 658                              <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
 659                              <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 660                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 661                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 662                 clocks = <&clock CLK_PWM>;
 663                 clock-names = "timers";
 664                 #pwm-cells = <3>;
 665                 status = "disabled";
 666         };
 667
 668         amba {
 669                 #address-cells = <1>;
 670                 #size-cells = <1>;
 671                 compatible = "simple-bus";
 672                 interrupt-parent = <&gic>;
 673                 ranges;
 674
 675                 pdma0: pdma@12680000 {
 676                         compatible = "arm,pl330", "arm,primecell";
 677                         reg = <0x12680000 0x1000>;
 678                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 679                         clocks = <&clock CLK_PDMA0>;
 680                         clock-names = "apb_pclk";
 681                         #dma-cells = <1>;
 682                         #dma-channels = <8>;
 683                         #dma-requests = <32>;
 684                 };
 685
 686                 pdma1: pdma@12690000 {
 687                         compatible = "arm,pl330", "arm,primecell";
 688                         reg = <0x12690000 0x1000>;
 689                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 690                         clocks = <&clock CLK_PDMA1>;
 691                         clock-names = "apb_pclk";
 692                         #dma-cells = <1>;
 693                         #dma-channels = <8>;
 694                         #dma-requests = <32>;
 695                 };
 696
 697                 mdma1: mdma@12850000 {
 698                         compatible = "arm,pl330", "arm,primecell";
 699                         reg = <0x12850000 0x1000>;
 700                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 701                         clocks = <&clock CLK_MDMA>;
 702                         clock-names = "apb_pclk";
 703                         #dma-cells = <1>;
 704                         #dma-channels = <8>;
 705                         #dma-requests = <1>;
 706                 };
 707         };
 708
 709         fimd: fimd@11c00000 {
 710                 compatible = "samsung,exynos4210-fimd";
 711                 interrupt-parent = <&combiner>;
 712                 reg = <0x11c00000 0x20000>;
 713                 interrupt-names = "fifo", "vsync", "lcd_sys";
 714                 interrupts = <11 0>, <11 1>, <11 2>;
 715                 clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
 716                 clock-names = "sclk_fimd", "fimd";
 717                 power-domains = <&pd_lcd0>;
 718                 iommus = <&sysmmu_fimd0>;
 719                 samsung,sysreg = <&sys_reg>;
 720                 status = "disabled";
 721         };
 722
 723         tmu: tmu@100C0000 {
 724                 #include "exynos4412-tmu-sensor-conf.dtsi"
 725         };
 726
 727         jpeg_codec: jpeg-codec@11840000 {
 728                 compatible = "samsung,exynos4210-jpeg";
 729                 reg = <0x11840000 0x1000>;
 730                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 731                 clocks = <&clock CLK_JPEG>;
 732                 clock-names = "jpeg";
 733                 power-domains = <&pd_cam>;
 734                 iommus = <&sysmmu_jpeg>;
 735         };
 736
 737         rotator: rotator@12810000 {
 738                 compatible = "samsung,exynos4210-rotator";
 739                 reg = <0x12810000 0x64>;
 740                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 741                 clocks = <&clock CLK_ROTATOR>;
 742                 clock-names = "rotator";
 743                 iommus = <&sysmmu_rotator>;
 744         };
 745
 746         hdmi: hdmi@12D00000 {
 747                 compatible = "samsung,exynos4210-hdmi";
 748                 reg = <0x12D00000 0x70000>;
 749                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 750                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
 751                         "mout_hdmi";
 752                 clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
 753                         <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
 754                         <&clock CLK_MOUT_HDMI>;
 755                 phy = <&hdmi_i2c_phy>;
 756                 power-domains = <&pd_tv>;
 757                 samsung,syscon-phandle = <&pmu_system_controller>;
 758                 status = "disabled";
 759         };
 760
 761         hdmicec: cec@100B0000 {
 762                 compatible = "samsung,s5p-cec";
 763                 reg = <0x100B0000 0x200>;
 764                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 765                 clocks = <&clock CLK_HDMI_CEC>;
 766                 clock-names = "hdmicec";
 767                 samsung,syscon-phandle = <&pmu_system_controller>;
 768                 hdmi-phandle = <&hdmi>;
 769                 pinctrl-names = "default";
 770                 pinctrl-0 = <&hdmi_cec>;
 771                 status = "disabled";
 772         };
 773
 774         mixer: mixer@12C10000 {
 775                 compatible = "samsung,exynos4210-mixer";
 776                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 777                 reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
 778                 power-domains = <&pd_tv>;
 779                 iommus = <&sysmmu_tv>;
 780                 status = "disabled";
 781         };
 782
 783         ppmu_dmc0: ppmu_dmc0@106a0000 {
 784                 compatible = "samsung,exynos-ppmu";
 785                 reg = <0x106a0000 0x2000>;
 786                 clocks = <&clock CLK_PPMUDMC0>;
 787                 clock-names = "ppmu";
 788                 status = "disabled";
 789         };
 790
 791         ppmu_dmc1: ppmu_dmc1@106b0000 {
 792                 compatible = "samsung,exynos-ppmu";
 793                 reg = <0x106b0000 0x2000>;
 794                 clocks = <&clock CLK_PPMUDMC1>;
 795                 clock-names = "ppmu";
 796                 status = "disabled";
 797         };
 798
 799         ppmu_cpu: ppmu_cpu@106c0000 {
 800                 compatible = "samsung,exynos-ppmu";
 801                 reg = <0x106c0000 0x2000>;
 802                 clocks = <&clock CLK_PPMUCPU>;
 803                 clock-names = "ppmu";
 804                 status = "disabled";
 805         };
 806
 807         ppmu_acp: ppmu_acp@10ae0000 {
 808                 compatible = "samsung,exynos-ppmu";
 809                 reg = <0x106e0000 0x2000>;
 810                 status = "disabled";
 811         };
 812
 813         ppmu_rightbus: ppmu_rightbus@112a0000 {
 814                 compatible = "samsung,exynos-ppmu";
 815                 reg = <0x112a0000 0x2000>;
 816                 clocks = <&clock CLK_PPMURIGHT>;
 817                 clock-names = "ppmu";
 818                 status = "disabled";
 819         };
 820
 821         ppmu_leftbus: ppmu_leftbus0@116a0000 {
 822                 compatible = "samsung,exynos-ppmu";
 823                 reg = <0x116a0000 0x2000>;
 824                 clocks = <&clock CLK_PPMULEFT>;
 825                 clock-names = "ppmu";
 826                 status = "disabled";
 827         };
 828
 829         ppmu_camif: ppmu_camif@11ac0000 {
 830                 compatible = "samsung,exynos-ppmu";
 831                 reg = <0x11ac0000 0x2000>;
 832                 clocks = <&clock CLK_PPMUCAMIF>;
 833                 clock-names = "ppmu";
 834                 status = "disabled";
 835         };
 836
 837         ppmu_lcd0: ppmu_lcd0@11e40000 {
 838                 compatible = "samsung,exynos-ppmu";
 839                 reg = <0x11e40000 0x2000>;
 840                 clocks = <&clock CLK_PPMULCD0>;
 841                 clock-names = "ppmu";
 842                 status = "disabled";
 843         };
 844
 845         ppmu_fsys: ppmu_g3d@12630000 {
 846                 compatible = "samsung,exynos-ppmu";
 847                 reg = <0x12630000 0x2000>;
 848                 status = "disabled";
 849         };
 850
 851         ppmu_image: ppmu_image@12aa0000 {
 852                 compatible = "samsung,exynos-ppmu";
 853                 reg = <0x12aa0000 0x2000>;
 854                 clocks = <&clock CLK_PPMUIMAGE>;
 855                 clock-names = "ppmu";
 856                 status = "disabled";
 857         };
 858
 859         ppmu_tv: ppmu_tv@12e40000 {
 860                 compatible = "samsung,exynos-ppmu";
 861                 reg = <0x12e40000 0x2000>;
 862                 clocks = <&clock CLK_PPMUTV>;
 863                 clock-names = "ppmu";
 864                 status = "disabled";
 865         };
 866
 867         ppmu_g3d: ppmu_g3d@13220000 {
 868                 compatible = "samsung,exynos-ppmu";
 869                 reg = <0x13220000 0x2000>;
 870                 clocks = <&clock CLK_PPMUG3D>;
 871                 clock-names = "ppmu";
 872                 status = "disabled";
 873         };
 874
 875         ppmu_mfc_left: ppmu_mfc_left@13660000 {
 876                 compatible = "samsung,exynos-ppmu";
 877                 reg = <0x13660000 0x2000>;
 878                 clocks = <&clock CLK_PPMUMFC_L>;
 879                 clock-names = "ppmu";
 880                 status = "disabled";
 881         };
 882
 883         ppmu_mfc_right: ppmu_mfc_right@13670000 {
 884                 compatible = "samsung,exynos-ppmu";
 885                 reg = <0x13670000 0x2000>;
 886                 clocks = <&clock CLK_PPMUMFC_R>;
 887                 clock-names = "ppmu";
 888                 status = "disabled";
 889         };
 890
 891         sysmmu_mfc_l: sysmmu@13620000 {
 892                 compatible = "samsung,exynos-sysmmu";
 893                 reg = <0x13620000 0x1000>;
 894                 interrupt-parent = <&combiner>;
 895                 interrupts = <5 5>;
 896                 clock-names = "sysmmu", "master";
 897                 clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
 898                 power-domains = <&pd_mfc>;
 899                 #iommu-cells = <0>;
 900         };
 901
 902         sysmmu_mfc_r: sysmmu@13630000 {
 903                 compatible = "samsung,exynos-sysmmu";
 904                 reg = <0x13630000 0x1000>;
 905                 interrupt-parent = <&combiner>;
 906                 interrupts = <5 6>;
 907                 clock-names = "sysmmu", "master";
 908                 clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
 909                 power-domains = <&pd_mfc>;
 910                 #iommu-cells = <0>;
 911         };
 912
 913         sysmmu_tv: sysmmu@12E20000 {
 914                 compatible = "samsung,exynos-sysmmu";
 915                 reg = <0x12E20000 0x1000>;
 916                 interrupt-parent = <&combiner>;
 917                 interrupts = <5 4>;
 918                 clock-names = "sysmmu", "master";
 919                 clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
 920                 power-domains = <&pd_tv>;
 921                 #iommu-cells = <0>;
 922         };
 923
 924         sysmmu_fimc0: sysmmu@11A20000 {
 925                 compatible = "samsung,exynos-sysmmu";
 926                 reg = <0x11A20000 0x1000>;
 927                 interrupt-parent = <&combiner>;
 928                 interrupts = <4 2>;
 929                 clock-names = "sysmmu", "master";
 930                 clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
 931                 power-domains = <&pd_cam>;
 932                 #iommu-cells = <0>;
 933         };
 934
 935         sysmmu_fimc1: sysmmu@11A30000 {
 936                 compatible = "samsung,exynos-sysmmu";
 937                 reg = <0x11A30000 0x1000>;
 938                 interrupt-parent = <&combiner>;
 939                 interrupts = <4 3>;
 940                 clock-names = "sysmmu", "master";
 941                 clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
 942                 power-domains = <&pd_cam>;
 943                 #iommu-cells = <0>;
 944         };
 945
 946         sysmmu_fimc2: sysmmu@11A40000 {
 947                 compatible = "samsung,exynos-sysmmu";
 948                 reg = <0x11A40000 0x1000>;
 949                 interrupt-parent = <&combiner>;
 950                 interrupts = <4 4>;
 951                 clock-names = "sysmmu", "master";
 952                 clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
 953                 power-domains = <&pd_cam>;
 954                 #iommu-cells = <0>;
 955         };
 956
 957         sysmmu_fimc3: sysmmu@11A50000 {
 958                 compatible = "samsung,exynos-sysmmu";
 959                 reg = <0x11A50000 0x1000>;
 960                 interrupt-parent = <&combiner>;
 961                 interrupts = <4 5>;
 962                 clock-names = "sysmmu", "master";
 963                 clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
 964                 power-domains = <&pd_cam>;
 965                 #iommu-cells = <0>;
 966         };
 967
 968         sysmmu_jpeg: sysmmu@11A60000 {
 969                 compatible = "samsung,exynos-sysmmu";
 970                 reg = <0x11A60000 0x1000>;
 971                 interrupt-parent = <&combiner>;
 972                 interrupts = <4 6>;
 973                 clock-names = "sysmmu", "master";
 974                 clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
 975                 power-domains = <&pd_cam>;
 976                 #iommu-cells = <0>;
 977         };
 978
 979         sysmmu_rotator: sysmmu@12A30000 {
 980                 compatible = "samsung,exynos-sysmmu";
 981                 reg = <0x12A30000 0x1000>;
 982                 interrupt-parent = <&combiner>;
 983                 interrupts = <5 0>;
 984                 clock-names = "sysmmu", "master";
 985                 clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
 986                 #iommu-cells = <0>;
 987         };
 988
 989         sysmmu_fimd0: sysmmu@11E20000 {
 990                 compatible = "samsung,exynos-sysmmu";
 991                 reg = <0x11E20000 0x1000>;
 992                 interrupt-parent = <&combiner>;
 993                 interrupts = <5 2>;
 994                 clock-names = "sysmmu", "master";
 995                 clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
 996                 power-domains = <&pd_lcd0>;
 997                 #iommu-cells = <0>;
 998         };
 999
1000         sss: sss@10830000 {
1001                 compatible = "samsung,exynos4210-secss";
1002                 reg = <0x10830000 0x300>;
1003                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1004                 clocks = <&clock CLK_SSS>;
1005                 clock-names = "secss";
1006         };
1007
1008         prng: rng@10830400 {
1009                 compatible = "samsung,exynos4-rng";
1010                 reg = <0x10830400 0x200>;
1011                 clocks = <&clock CLK_SSS>;
1012                 clock-names = "secss";
1013         };
1014 };