1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos3250 SoC device tree source
5 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
6 * http://www.samsung.com
8 * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
9 * based board files can include this file and provide values for board specfic
12 * Note: This file does not include device nodes for all the controllers in
13 * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
14 * nodes can be added to this file.
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
23 compatible = "samsung,exynos3250";
24 interrupt-parent = <&gic>;
29 pinctrl0 = &pinctrl_0;
30 pinctrl1 = &pinctrl_1;
55 compatible = "arm,cortex-a7";
57 clock-frequency = <1000000000>;
58 clocks = <&cmu CLK_ARM_CLK>;
78 compatible = "arm,cortex-a7";
80 clock-frequency = <1000000000>;
81 clocks = <&cmu CLK_ARM_CLK>;
101 #address-cells = <1>;
105 compatible = "fixed-clock";
107 clock-frequency = <0>;
109 clock-output-names = "xusbxti";
113 compatible = "fixed-clock";
115 clock-frequency = <0>;
117 clock-output-names = "xxti";
121 compatible = "fixed-clock";
123 clock-frequency = <0>;
125 clock-output-names = "xtcxo";
130 compatible = "arm,cortex-a7-pmu";
131 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
136 compatible = "simple-bus";
137 #address-cells = <1>;
142 compatible = "mmio-sram";
143 reg = <0x02020000 0x40000>;
144 #address-cells = <1>;
146 ranges = <0 0x02020000 0x40000>;
149 compatible = "samsung,exynos4210-sysram";
154 compatible = "samsung,exynos4210-sysram-ns";
155 reg = <0x3f000 0x1000>;
160 compatible = "samsung,exynos4210-chipid";
161 reg = <0x10000000 0x100>;
164 sys_reg: syscon@10010000 {
165 compatible = "samsung,exynos3-sysreg", "syscon";
166 reg = <0x10010000 0x400>;
169 pmu_system_controller: system-controller@10020000 {
170 compatible = "samsung,exynos3250-pmu", "syscon";
171 reg = <0x10020000 0x4000>;
172 interrupt-controller;
173 #interrupt-cells = <3>;
174 interrupt-parent = <&gic>;
175 clock-names = "clkout8";
176 clocks = <&cmu CLK_FIN_PLL>;
180 mipi_phy: video-phy {
181 compatible = "samsung,s5pv210-mipi-video-phy";
183 syscon = <&pmu_system_controller>;
186 pd_cam: power-domain@10023c00 {
187 compatible = "samsung,exynos4210-pd";
188 reg = <0x10023C00 0x20>;
189 #power-domain-cells = <0>;
193 pd_mfc: power-domain@10023c40 {
194 compatible = "samsung,exynos4210-pd";
195 reg = <0x10023C40 0x20>;
196 #power-domain-cells = <0>;
200 pd_g3d: power-domain@10023c60 {
201 compatible = "samsung,exynos4210-pd";
202 reg = <0x10023C60 0x20>;
203 #power-domain-cells = <0>;
207 pd_lcd0: power-domain@10023c80 {
208 compatible = "samsung,exynos4210-pd";
209 reg = <0x10023C80 0x20>;
210 #power-domain-cells = <0>;
214 pd_isp: power-domain@10023ca0 {
215 compatible = "samsung,exynos4210-pd";
216 reg = <0x10023CA0 0x20>;
217 #power-domain-cells = <0>;
221 cmu: clock-controller@10030000 {
222 compatible = "samsung,exynos3250-cmu";
223 reg = <0x10030000 0x20000>;
225 assigned-clocks = <&cmu CLK_MOUT_ACLK_400_MCUISP_SUB>,
226 <&cmu CLK_MOUT_ACLK_266_SUB>;
227 assigned-clock-parents = <&cmu CLK_FIN_PLL>,
231 cmu_dmc: clock-controller@105c0000 {
232 compatible = "samsung,exynos3250-cmu-dmc";
233 reg = <0x105C0000 0x2000>;
238 compatible = "samsung,s3c6410-rtc";
239 reg = <0x10070000 0x100>;
240 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
242 interrupt-parent = <&pmu_system_controller>;
247 compatible = "samsung,exynos3250-tmu";
248 reg = <0x100C0000 0x100>;
249 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&cmu CLK_TMU_APBIF>;
251 clock-names = "tmu_apbif";
252 #thermal-sensor-cells = <0>;
256 gic: interrupt-controller@10481000 {
257 compatible = "arm,cortex-a15-gic";
258 #interrupt-cells = <3>;
259 interrupt-controller;
260 reg = <0x10481000 0x1000>,
264 interrupts = <GIC_PPI 9
265 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
269 compatible = "samsung,exynos4210-mct";
270 reg = <0x10050000 0x800>;
271 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
280 clock-names = "fin_pll", "mct";
283 pinctrl_1: pinctrl@11000000 {
284 compatible = "samsung,exynos3250-pinctrl";
285 reg = <0x11000000 0x1000>;
286 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
288 wakeup-interrupt-controller {
289 compatible = "samsung,exynos4210-wakeup-eint";
290 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
294 pinctrl_0: pinctrl@11400000 {
295 compatible = "samsung,exynos3250-pinctrl";
296 reg = <0x11400000 0x1000>;
297 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
300 jpeg: codec@11830000 {
301 compatible = "samsung,exynos3250-jpeg";
302 reg = <0x11830000 0x1000>;
303 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&cmu CLK_JPEG>, <&cmu CLK_SCLK_JPEG>;
305 clock-names = "jpeg", "sclk";
306 power-domains = <&pd_cam>;
307 assigned-clocks = <&cmu CLK_MOUT_CAM_BLK>, <&cmu CLK_SCLK_JPEG>;
308 assigned-clock-rates = <0>, <150000000>;
309 assigned-clock-parents = <&cmu CLK_DIV_MPLL_PRE>;
310 iommus = <&sysmmu_jpeg>;
314 sysmmu_jpeg: sysmmu@11a60000 {
315 compatible = "samsung,exynos-sysmmu";
316 reg = <0x11a60000 0x1000>;
317 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
319 clock-names = "sysmmu", "master";
320 clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
321 power-domains = <&pd_cam>;
325 fimd: fimd@11c00000 {
326 compatible = "samsung,exynos3250-fimd";
327 reg = <0x11c00000 0x30000>;
328 interrupt-names = "fifo", "vsync", "lcd_sys";
329 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>;
333 clock-names = "sclk_fimd", "fimd";
334 power-domains = <&pd_lcd0>;
335 iommus = <&sysmmu_fimd0>;
336 samsung,sysreg = <&sys_reg>;
340 dsi_0: dsi@11c80000 {
341 compatible = "samsung,exynos3250-mipi-dsi";
342 reg = <0x11C80000 0x10000>;
343 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
344 samsung,phy-type = <0>;
345 power-domains = <&pd_lcd0>;
346 phys = <&mipi_phy 1>;
348 clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>;
349 clock-names = "bus_clk", "pll_clk";
350 #address-cells = <1>;
355 sysmmu_fimd0: sysmmu@11e20000 {
356 compatible = "samsung,exynos-sysmmu";
357 reg = <0x11e20000 0x1000>;
358 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
360 clock-names = "sysmmu", "master";
361 clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
362 power-domains = <&pd_lcd0>;
366 hsotg: hsotg@12480000 {
367 compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
368 reg = <0x12480000 0x20000>;
369 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&cmu CLK_USBOTG>;
372 phys = <&exynos_usbphy 0>;
373 phy-names = "usb2-phy";
377 mshc_0: mshc@12510000 {
378 compatible = "samsung,exynos5420-dw-mshc";
379 reg = <0x12510000 0x1000>;
380 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
382 clock-names = "biu", "ciu";
384 #address-cells = <1>;
389 mshc_1: mshc@12520000 {
390 compatible = "samsung,exynos5420-dw-mshc";
391 reg = <0x12520000 0x1000>;
392 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
394 clock-names = "biu", "ciu";
396 #address-cells = <1>;
401 mshc_2: mshc@12530000 {
402 compatible = "samsung,exynos5250-dw-mshc";
403 reg = <0x12530000 0x1000>;
404 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
406 clock-names = "biu", "ciu";
408 #address-cells = <1>;
413 exynos_usbphy: exynos-usbphy@125b0000 {
414 compatible = "samsung,exynos3250-usb2-phy";
415 reg = <0x125B0000 0x100>;
416 samsung,pmureg-phandle = <&pmu_system_controller>;
417 clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>;
418 clock-names = "phy", "ref";
424 compatible = "simple-bus";
425 #address-cells = <1>;
429 pdma0: pdma@12680000 {
430 compatible = "arm,pl330", "arm,primecell";
431 reg = <0x12680000 0x1000>;
432 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cmu CLK_PDMA0>;
434 clock-names = "apb_pclk";
437 #dma-requests = <32>;
440 pdma1: pdma@12690000 {
441 compatible = "arm,pl330", "arm,primecell";
442 reg = <0x12690000 0x1000>;
443 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&cmu CLK_PDMA1>;
445 clock-names = "apb_pclk";
448 #dma-requests = <32>;
453 compatible = "samsung,exynos3250-adc",
454 "samsung,exynos-adc-v2";
455 reg = <0x126C0000 0x100>;
456 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
457 clock-names = "adc", "sclk";
458 clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
459 #io-channel-cells = <1>;
461 samsung,syscon-phandle = <&pmu_system_controller>;
465 mfc: codec@13400000 {
466 compatible = "samsung,mfc-v7";
467 reg = <0x13400000 0x10000>;
468 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
469 clock-names = "mfc", "sclk_mfc";
470 clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
471 power-domains = <&pd_mfc>;
472 iommus = <&sysmmu_mfc>;
475 sysmmu_mfc: sysmmu@13620000 {
476 compatible = "samsung,exynos-sysmmu";
477 reg = <0x13620000 0x1000>;
478 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
480 clock-names = "sysmmu", "master";
481 clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
482 power-domains = <&pd_mfc>;
486 serial_0: serial@13800000 {
487 compatible = "samsung,exynos4210-uart";
488 reg = <0x13800000 0x100>;
489 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
490 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
491 clock-names = "uart", "clk_uart_baud0";
492 pinctrl-names = "default";
493 pinctrl-0 = <&uart0_data &uart0_fctl>;
497 serial_1: serial@13810000 {
498 compatible = "samsung,exynos4210-uart";
499 reg = <0x13810000 0x100>;
500 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
502 clock-names = "uart", "clk_uart_baud0";
503 pinctrl-names = "default";
504 pinctrl-0 = <&uart1_data>;
508 serial_2: serial@13820000 {
509 compatible = "samsung,exynos4210-uart";
510 reg = <0x13820000 0x100>;
511 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
513 clock-names = "uart", "clk_uart_baud0";
514 pinctrl-names = "default";
515 pinctrl-0 = <&uart2_data>;
519 i2c_0: i2c@13860000 {
520 #address-cells = <1>;
522 compatible = "samsung,s3c2440-i2c";
523 reg = <0x13860000 0x100>;
524 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cmu CLK_I2C0>;
527 pinctrl-names = "default";
528 pinctrl-0 = <&i2c0_bus>;
532 i2c_1: i2c@13870000 {
533 #address-cells = <1>;
535 compatible = "samsung,s3c2440-i2c";
536 reg = <0x13870000 0x100>;
537 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
538 clocks = <&cmu CLK_I2C1>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&i2c1_bus>;
545 i2c_2: i2c@13880000 {
546 #address-cells = <1>;
548 compatible = "samsung,s3c2440-i2c";
549 reg = <0x13880000 0x100>;
550 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
551 clocks = <&cmu CLK_I2C2>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c2_bus>;
558 i2c_3: i2c@13890000 {
559 #address-cells = <1>;
561 compatible = "samsung,s3c2440-i2c";
562 reg = <0x13890000 0x100>;
563 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&cmu CLK_I2C3>;
566 pinctrl-names = "default";
567 pinctrl-0 = <&i2c3_bus>;
571 i2c_4: i2c@138a0000 {
572 #address-cells = <1>;
574 compatible = "samsung,s3c2440-i2c";
575 reg = <0x138A0000 0x100>;
576 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&cmu CLK_I2C4>;
579 pinctrl-names = "default";
580 pinctrl-0 = <&i2c4_bus>;
584 i2c_5: i2c@138b0000 {
585 #address-cells = <1>;
587 compatible = "samsung,s3c2440-i2c";
588 reg = <0x138B0000 0x100>;
589 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cmu CLK_I2C5>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&i2c5_bus>;
597 i2c_6: i2c@138c0000 {
598 #address-cells = <1>;
600 compatible = "samsung,s3c2440-i2c";
601 reg = <0x138C0000 0x100>;
602 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
603 clocks = <&cmu CLK_I2C6>;
605 pinctrl-names = "default";
606 pinctrl-0 = <&i2c6_bus>;
610 i2c_7: i2c@138d0000 {
611 #address-cells = <1>;
613 compatible = "samsung,s3c2440-i2c";
614 reg = <0x138D0000 0x100>;
615 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&cmu CLK_I2C7>;
618 pinctrl-names = "default";
619 pinctrl-0 = <&i2c7_bus>;
623 spi_0: spi@13920000 {
624 compatible = "samsung,exynos4210-spi";
625 reg = <0x13920000 0x100>;
626 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
627 dmas = <&pdma0 7>, <&pdma0 6>;
628 dma-names = "tx", "rx";
629 #address-cells = <1>;
631 clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
632 clock-names = "spi", "spi_busclk0";
633 samsung,spi-src-clk = <0>;
634 pinctrl-names = "default";
635 pinctrl-0 = <&spi0_bus>;
639 spi_1: spi@13930000 {
640 compatible = "samsung,exynos4210-spi";
641 reg = <0x13930000 0x100>;
642 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
643 dmas = <&pdma1 7>, <&pdma1 6>;
644 dma-names = "tx", "rx";
645 #address-cells = <1>;
647 clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
648 clock-names = "spi", "spi_busclk0";
649 samsung,spi-src-clk = <0>;
650 pinctrl-names = "default";
651 pinctrl-0 = <&spi1_bus>;
656 compatible = "samsung,s3c6410-i2s";
657 reg = <0x13970000 0x100>;
658 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
660 clock-names = "iis", "i2s_opclk0";
661 dmas = <&pdma0 14>, <&pdma0 13>;
662 dma-names = "tx", "rx";
663 pinctrl-0 = <&i2s2_bus>;
664 pinctrl-names = "default";
669 compatible = "samsung,exynos4210-pwm";
670 reg = <0x139D0000 0x1000>;
671 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
680 ppmu_dmc0: ppmu_dmc0@106a0000 {
681 compatible = "samsung,exynos-ppmu";
682 reg = <0x106a0000 0x2000>;
686 ppmu_dmc1: ppmu_dmc1@106b0000 {
687 compatible = "samsung,exynos-ppmu";
688 reg = <0x106b0000 0x2000>;
692 ppmu_cpu: ppmu_cpu@106c0000 {
693 compatible = "samsung,exynos-ppmu";
694 reg = <0x106c0000 0x2000>;
698 ppmu_rightbus: ppmu_rightbus@112a0000 {
699 compatible = "samsung,exynos-ppmu";
700 reg = <0x112a0000 0x2000>;
701 clocks = <&cmu CLK_PPMURIGHT>;
702 clock-names = "ppmu";
706 ppmu_leftbus: ppmu_leftbus0@116a0000 {
707 compatible = "samsung,exynos-ppmu";
708 reg = <0x116a0000 0x2000>;
709 clocks = <&cmu CLK_PPMULEFT>;
710 clock-names = "ppmu";
714 ppmu_camif: ppmu_camif@11ac0000 {
715 compatible = "samsung,exynos-ppmu";
716 reg = <0x11ac0000 0x2000>;
717 clocks = <&cmu CLK_PPMUCAMIF>;
718 clock-names = "ppmu";
722 ppmu_lcd0: ppmu_lcd0@11e40000 {
723 compatible = "samsung,exynos-ppmu";
724 reg = <0x11e40000 0x2000>;
725 clocks = <&cmu CLK_PPMULCD0>;
726 clock-names = "ppmu";
730 ppmu_fsys: ppmu_fsys@12630000 {
731 compatible = "samsung,exynos-ppmu";
732 reg = <0x12630000 0x2000>;
733 clocks = <&cmu CLK_PPMUFILE>;
734 clock-names = "ppmu";
738 ppmu_g3d: ppmu_g3d@13220000 {
739 compatible = "samsung,exynos-ppmu";
740 reg = <0x13220000 0x2000>;
741 clocks = <&cmu CLK_PPMUG3D>;
742 clock-names = "ppmu";
746 ppmu_mfc: ppmu_mfc@13660000 {
747 compatible = "samsung,exynos-ppmu";
748 reg = <0x13660000 0x2000>;
749 clocks = <&cmu CLK_PPMUMFC_L>;
750 clock-names = "ppmu";
755 compatible = "samsung,exynos-bus";
756 clocks = <&cmu_dmc CLK_DIV_DMC>;
758 operating-points-v2 = <&bus_dmc_opp_table>;
762 bus_dmc_opp_table: opp_table1 {
763 compatible = "operating-points-v2";
767 opp-hz = /bits/ 64 <50000000>;
768 opp-microvolt = <800000>;
771 opp-hz = /bits/ 64 <100000000>;
772 opp-microvolt = <800000>;
775 opp-hz = /bits/ 64 <134000000>;
776 opp-microvolt = <800000>;
779 opp-hz = /bits/ 64 <200000000>;
780 opp-microvolt = <825000>;
783 opp-hz = /bits/ 64 <400000000>;
784 opp-microvolt = <875000>;
788 bus_leftbus: bus_leftbus {
789 compatible = "samsung,exynos-bus";
790 clocks = <&cmu CLK_DIV_GDL>;
792 operating-points-v2 = <&bus_leftbus_opp_table>;
796 bus_rightbus: bus_rightbus {
797 compatible = "samsung,exynos-bus";
798 clocks = <&cmu CLK_DIV_GDR>;
800 operating-points-v2 = <&bus_leftbus_opp_table>;
805 compatible = "samsung,exynos-bus";
806 clocks = <&cmu CLK_DIV_ACLK_160>;
808 operating-points-v2 = <&bus_leftbus_opp_table>;
813 compatible = "samsung,exynos-bus";
814 clocks = <&cmu CLK_DIV_ACLK_200>;
816 operating-points-v2 = <&bus_leftbus_opp_table>;
820 bus_mcuisp: bus_mcuisp {
821 compatible = "samsung,exynos-bus";
822 clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
824 operating-points-v2 = <&bus_mcuisp_opp_table>;
829 compatible = "samsung,exynos-bus";
830 clocks = <&cmu CLK_DIV_ACLK_266>;
832 operating-points-v2 = <&bus_isp_opp_table>;
836 bus_peril: bus_peril {
837 compatible = "samsung,exynos-bus";
838 clocks = <&cmu CLK_DIV_ACLK_100>;
840 operating-points-v2 = <&bus_peril_opp_table>;
845 compatible = "samsung,exynos-bus";
846 clocks = <&cmu CLK_SCLK_MFC>;
848 operating-points-v2 = <&bus_leftbus_opp_table>;
852 bus_leftbus_opp_table: opp_table2 {
853 compatible = "operating-points-v2";
857 opp-hz = /bits/ 64 <50000000>;
858 opp-microvolt = <900000>;
861 opp-hz = /bits/ 64 <80000000>;
862 opp-microvolt = <900000>;
865 opp-hz = /bits/ 64 <100000000>;
866 opp-microvolt = <1000000>;
869 opp-hz = /bits/ 64 <134000000>;
870 opp-microvolt = <1000000>;
873 opp-hz = /bits/ 64 <200000000>;
874 opp-microvolt = <1000000>;
878 bus_mcuisp_opp_table: opp_table3 {
879 compatible = "operating-points-v2";
883 opp-hz = /bits/ 64 <50000000>;
886 opp-hz = /bits/ 64 <80000000>;
889 opp-hz = /bits/ 64 <100000000>;
892 opp-hz = /bits/ 64 <200000000>;
895 opp-hz = /bits/ 64 <400000000>;
899 bus_isp_opp_table: opp_table4 {
900 compatible = "operating-points-v2";
904 opp-hz = /bits/ 64 <50000000>;
907 opp-hz = /bits/ 64 <80000000>;
910 opp-hz = /bits/ 64 <100000000>;
913 opp-hz = /bits/ 64 <200000000>;
916 opp-hz = /bits/ 64 <300000000>;
920 bus_peril_opp_table: opp_table5 {
921 compatible = "operating-points-v2";
925 opp-hz = /bits/ 64 <50000000>;
928 opp-hz = /bits/ 64 <80000000>;
931 opp-hz = /bits/ 64 <100000000>;
937 #include "exynos3250-pinctrl.dtsi"
938 #include "exynos-syscon-restart.dtsi"