arch/arm/boot/dts/exynos3250.dtsi

   1 /*
   2  * Samsung's Exynos3250 SoC device tree source
   3  *
   4  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19
  20 #include "skeleton.dtsi"
  21 #include <dt-bindings/clock/exynos3250.h>
  22
  23 / {
  24         compatible = "samsung,exynos3250";
  25         interrupt-parent = <&gic>;
  26
  27         aliases {
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 mshc0 = &mshc_0;
  31                 mshc1 = &mshc_1;
  32                 spi0 = &spi_0;
  33                 spi1 = &spi_1;
  34                 i2c0 = &i2c_0;
  35                 i2c1 = &i2c_1;
  36                 i2c2 = &i2c_2;
  37                 i2c3 = &i2c_3;
  38                 i2c4 = &i2c_4;
  39                 i2c5 = &i2c_5;
  40                 i2c6 = &i2c_6;
  41                 i2c7 = &i2c_7;
  42                 serial0 = &serial_0;
  43                 serial1 = &serial_1;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49
  50                 cpu0: cpu@0 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a7";
  53                         reg = <0>;
  54                         clock-frequency = <1000000000>;
  55                 };
  56
  57                 cpu1: cpu@1 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a7";
  60                         reg = <1>;
  61                         clock-frequency = <1000000000>;
  62                 };
  63         };
  64
  65         soc: soc {
  66                 compatible = "simple-bus";
  67                 #address-cells = <1>;
  68                 #size-cells = <1>;
  69                 ranges;
  70
  71                 fixed-rate-clocks {
  72                         #address-cells = <1>;
  73                         #size-cells = <0>;
  74
  75                         xusbxti: clock@0 {
  76                                 compatible = "fixed-clock";
  77                                 #address-cells = <1>;
  78                                 #size-cells = <0>;
  79                                 reg = <0>;
  80                                 clock-frequency = <0>;
  81                                 #clock-cells = <0>;
  82                                 clock-output-names = "xusbxti";
  83                         };
  84
  85                         xxti: clock@1 {
  86                                 compatible = "fixed-clock";
  87                                 reg = <1>;
  88                                 clock-frequency = <0>;
  89                                 #clock-cells = <0>;
  90                                 clock-output-names = "xxti";
  91                         };
  92
  93                         xtcxo: clock@2 {
  94                                 compatible = "fixed-clock";
  95                                 reg = <2>;
  96                                 clock-frequency = <0>;
  97                                 #clock-cells = <0>;
  98                                 clock-output-names = "xtcxo";
  99                         };
 100                 };
 101
 102                 sysram@02020000 {
 103                         compatible = "mmio-sram";
 104                         reg = <0x02020000 0x40000>;
 105                         #address-cells = <1>;
 106                         #size-cells = <1>;
 107                         ranges = <0 0x02020000 0x40000>;
 108
 109                         smp-sysram@0 {
 110                                 compatible = "samsung,exynos4210-sysram";
 111                                 reg = <0x0 0x1000>;
 112                         };
 113
 114                         smp-sysram@3f000 {
 115                                 compatible = "samsung,exynos4210-sysram-ns";
 116                                 reg = <0x3f000 0x1000>;
 117                         };
 118                 };
 119
 120                 chipid@10000000 {
 121                         compatible = "samsung,exynos4210-chipid";
 122                         reg = <0x10000000 0x100>;
 123                 };
 124
 125                 sys_reg: syscon@10010000 {
 126                         compatible = "samsung,exynos3-sysreg", "syscon";
 127                         reg = <0x10010000 0x400>;
 128                 };
 129
 130                 pmu_system_controller: system-controller@10020000 {
 131                         compatible = "samsung,exynos3250-pmu", "syscon";
 132                         reg = <0x10020000 0x4000>;
 133                 };
 134
 135                 pd_cam: cam-power-domain@10023C00 {
 136                         compatible = "samsung,exynos4210-pd";
 137                         reg = <0x10023C00 0x20>;
 138                 };
 139
 140                 pd_mfc: mfc-power-domain@10023C40 {
 141                         compatible = "samsung,exynos4210-pd";
 142                         reg = <0x10023C40 0x20>;
 143                 };
 144
 145                 pd_g3d: g3d-power-domain@10023C60 {
 146                         compatible = "samsung,exynos4210-pd";
 147                         reg = <0x10023C60 0x20>;
 148                 };
 149
 150                 pd_lcd0: lcd0-power-domain@10023C80 {
 151                         compatible = "samsung,exynos4210-pd";
 152                         reg = <0x10023C80 0x20>;
 153                 };
 154
 155                 pd_isp: isp-power-domain@10023CA0 {
 156                         compatible = "samsung,exynos4210-pd";
 157                         reg = <0x10023CA0 0x20>;
 158                 };
 159
 160                 cmu: clock-controller@10030000 {
 161                         compatible = "samsung,exynos3250-cmu";
 162                         reg = <0x10030000 0x20000>;
 163                         #clock-cells = <1>;
 164                 };
 165
 166                 rtc: rtc@10070000 {
 167                         compatible = "samsung,s3c6410-rtc";
 168                         reg = <0x10070000 0x100>;
 169                         interrupts = <0 73 0>, <0 74 0>;
 170                         status = "disabled";
 171                 };
 172
 173                 tmu: tmu@100C0000 {
 174                         compatible = "samsung,exynos3250-tmu";
 175                         reg = <0x100C0000 0x100>;
 176                         interrupts = <0 216 0>;
 177                         clocks = <&cmu CLK_TMU_APBIF>;
 178                         clock-names = "tmu_apbif";
 179                         status = "disabled";
 180                 };
 181
 182                 gic: interrupt-controller@10481000 {
 183                         compatible = "arm,cortex-a15-gic";
 184                         #interrupt-cells = <3>;
 185                         interrupt-controller;
 186                         reg = <0x10481000 0x1000>,
 187                               <0x10482000 0x1000>,
 188                               <0x10484000 0x2000>,
 189                               <0x10486000 0x2000>;
 190                         interrupts = <1 9 0xf04>;
 191                 };
 192
 193                 mct@10050000 {
 194                         compatible = "samsung,exynos4210-mct";
 195                         reg = <0x10050000 0x800>;
 196                         interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
 197                                      <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
 198                         clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
 199                         clock-names = "fin_pll", "mct";
 200                 };
 201
 202                 pinctrl_1: pinctrl@11000000 {
 203                         compatible = "samsung,exynos3250-pinctrl";
 204                         reg = <0x11000000 0x1000>;
 205                         interrupts = <0 225 0>;
 206
 207                         wakeup-interrupt-controller {
 208                                 compatible = "samsung,exynos4210-wakeup-eint";
 209                                 interrupts = <0 48 0>;
 210                         };
 211                 };
 212
 213                 pinctrl_0: pinctrl@11400000 {
 214                         compatible = "samsung,exynos3250-pinctrl";
 215                         reg = <0x11400000 0x1000>;
 216                         interrupts = <0 240 0>;
 217                 };
 218
 219                 mshc_0: mshc@12510000 {
 220                         compatible = "samsung,exynos5250-dw-mshc";
 221                         reg = <0x12510000 0x1000>;
 222                         interrupts = <0 142 0>;
 223                         clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
 224                         clock-names = "biu", "ciu";
 225                         fifo-depth = <0x80>;
 226                         #address-cells = <1>;
 227                         #size-cells = <0>;
 228                         status = "disabled";
 229                 };
 230
 231                 mshc_1: mshc@12520000 {
 232                         compatible = "samsung,exynos5250-dw-mshc";
 233                         reg = <0x12520000 0x1000>;
 234                         interrupts = <0 143 0>;
 235                         clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
 236                         clock-names = "biu", "ciu";
 237                         fifo-depth = <0x80>;
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         status = "disabled";
 241                 };
 242
 243                 amba {
 244                         compatible = "arm,amba-bus";
 245                         #address-cells = <1>;
 246                         #size-cells = <1>;
 247                         ranges;
 248
 249                         pdma0: pdma@12680000 {
 250                                 compatible = "arm,pl330", "arm,primecell";
 251                                 reg = <0x12680000 0x1000>;
 252                                 interrupts = <0 138 0>;
 253                                 clocks = <&cmu CLK_PDMA0>;
 254                                 clock-names = "apb_pclk";
 255                                 #dma-cells = <1>;
 256                                 #dma-channels = <8>;
 257                                 #dma-requests = <32>;
 258                         };
 259
 260                         pdma1: pdma@12690000 {
 261                                 compatible = "arm,pl330", "arm,primecell";
 262                                 reg = <0x12690000 0x1000>;
 263                                 interrupts = <0 139 0>;
 264                                 clocks = <&cmu CLK_PDMA1>;
 265                                 clock-names = "apb_pclk";
 266                                 #dma-cells = <1>;
 267                                 #dma-channels = <8>;
 268                                 #dma-requests = <32>;
 269                         };
 270                 };
 271
 272                 adc: adc@126C0000 {
 273                         compatible = "samsung,exynos3250-adc",
 274                                      "samsung,exynos-adc-v2";
 275                         reg = <0x126C0000 0x100>, <0x10020718 0x4>;
 276                         interrupts = <0 137 0>;
 277                         clock-names = "adc", "sclk";
 278                         clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
 279                         #io-channel-cells = <1>;
 280                         io-channel-ranges;
 281                         status = "disabled";
 282                 };
 283
 284                 serial_0: serial@13800000 {
 285                         compatible = "samsung,exynos4210-uart";
 286                         reg = <0x13800000 0x100>;
 287                         interrupts = <0 109 0>;
 288                         clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
 289                         clock-names = "uart", "clk_uart_baud0";
 290                         pinctrl-names = "default";
 291                         pinctrl-0 = <&uart0_data &uart0_fctl>;
 292                         status = "disabled";
 293                 };
 294
 295                 serial_1: serial@13810000 {
 296                         compatible = "samsung,exynos4210-uart";
 297                         reg = <0x13810000 0x100>;
 298                         interrupts = <0 110 0>;
 299                         clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
 300                         clock-names = "uart", "clk_uart_baud0";
 301                         pinctrl-names = "default";
 302                         pinctrl-0 = <&uart1_data>;
 303                         status = "disabled";
 304                 };
 305
 306                 i2c_0: i2c@13860000 {
 307                         #address-cells = <1>;
 308                         #size-cells = <0>;
 309                         compatible = "samsung,s3c2440-i2c";
 310                         reg = <0x13860000 0x100>;
 311                         interrupts = <0 113 0>;
 312                         clocks = <&cmu CLK_I2C0>;
 313                         clock-names = "i2c";
 314                         pinctrl-names = "default";
 315                         pinctrl-0 = <&i2c0_bus>;
 316                         status = "disabled";
 317                 };
 318
 319                 i2c_1: i2c@13870000 {
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322                         compatible = "samsung,s3c2440-i2c";
 323                         reg = <0x13870000 0x100>;
 324                         interrupts = <0 114 0>;
 325                         clocks = <&cmu CLK_I2C1>;
 326                         clock-names = "i2c";
 327                         pinctrl-names = "default";
 328                         pinctrl-0 = <&i2c1_bus>;
 329                         status = "disabled";
 330                 };
 331
 332                 i2c_2: i2c@13880000 {
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         compatible = "samsung,s3c2440-i2c";
 336                         reg = <0x13880000 0x100>;
 337                         interrupts = <0 115 0>;
 338                         clocks = <&cmu CLK_I2C2>;
 339                         clock-names = "i2c";
 340                         pinctrl-names = "default";
 341                         pinctrl-0 = <&i2c2_bus>;
 342                         status = "disabled";
 343                 };
 344
 345                 i2c_3: i2c@13890000 {
 346                         #address-cells = <1>;
 347                         #size-cells = <0>;
 348                         compatible = "samsung,s3c2440-i2c";
 349                         reg = <0x13890000 0x100>;
 350                         interrupts = <0 116 0>;
 351                         clocks = <&cmu CLK_I2C3>;
 352                         clock-names = "i2c";
 353                         pinctrl-names = "default";
 354                         pinctrl-0 = <&i2c3_bus>;
 355                         status = "disabled";
 356                 };
 357
 358                 i2c_4: i2c@138A0000 {
 359                         #address-cells = <1>;
 360                         #size-cells = <0>;
 361                         compatible = "samsung,s3c2440-i2c";
 362                         reg = <0x138A0000 0x100>;
 363                         interrupts = <0 117 0>;
 364                         clocks = <&cmu CLK_I2C4>;
 365                         clock-names = "i2c";
 366                         pinctrl-names = "default";
 367                         pinctrl-0 = <&i2c4_bus>;
 368                         status = "disabled";
 369                 };
 370
 371                 i2c_5: i2c@138B0000 {
 372                         #address-cells = <1>;
 373                         #size-cells = <0>;
 374                         compatible = "samsung,s3c2440-i2c";
 375                         reg = <0x138B0000 0x100>;
 376                         interrupts = <0 118 0>;
 377                         clocks = <&cmu CLK_I2C5>;
 378                         clock-names = "i2c";
 379                         pinctrl-names = "default";
 380                         pinctrl-0 = <&i2c5_bus>;
 381                         status = "disabled";
 382                 };
 383
 384                 i2c_6: i2c@138C0000 {
 385                         #address-cells = <1>;
 386                         #size-cells = <0>;
 387                         compatible = "samsung,s3c2440-i2c";
 388                         reg = <0x138C0000 0x100>;
 389                         interrupts = <0 119 0>;
 390                         clocks = <&cmu CLK_I2C6>;
 391                         clock-names = "i2c";
 392                         pinctrl-names = "default";
 393                         pinctrl-0 = <&i2c6_bus>;
 394                         status = "disabled";
 395                 };
 396
 397                 i2c_7: i2c@138D0000 {
 398                         #address-cells = <1>;
 399                         #size-cells = <0>;
 400                         compatible = "samsung,s3c2440-i2c";
 401                         reg = <0x138D0000 0x100>;
 402                         interrupts = <0 120 0>;
 403                         clocks = <&cmu CLK_I2C7>;
 404                         clock-names = "i2c";
 405                         pinctrl-names = "default";
 406                         pinctrl-0 = <&i2c7_bus>;
 407                         status = "disabled";
 408                 };
 409
 410                 spi_0: spi@13920000 {
 411                         compatible = "samsung,exynos4210-spi";
 412                         reg = <0x13920000 0x100>;
 413                         interrupts = <0 121 0>;
 414                         dmas = <&pdma0 7>, <&pdma0 6>;
 415                         dma-names = "tx", "rx";
 416                         #address-cells = <1>;
 417                         #size-cells = <0>;
 418                         clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
 419                         clock-names = "spi", "spi_busclk0";
 420                         samsung,spi-src-clk = <0>;
 421                         pinctrl-names = "default";
 422                         pinctrl-0 = <&spi0_bus>;
 423                         status = "disabled";
 424                 };
 425
 426                 spi_1: spi@13930000 {
 427                         compatible = "samsung,exynos4210-spi";
 428                         reg = <0x13930000 0x100>;
 429                         interrupts = <0 122 0>;
 430                         dmas = <&pdma1 7>, <&pdma1 6>;
 431                         dma-names = "tx", "rx";
 432                         #address-cells = <1>;
 433                         #size-cells = <0>;
 434                         clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
 435                         clock-names = "spi", "spi_busclk0";
 436                         samsung,spi-src-clk = <0>;
 437                         pinctrl-names = "default";
 438                         pinctrl-0 = <&spi1_bus>;
 439                         status = "disabled";
 440                 };
 441
 442                 i2s2: i2s@13970000 {
 443                         compatible = "samsung,s3c6410-i2s";
 444                         reg = <0x13970000 0x100>;
 445                         interrupts = <0 126 0>;
 446                         clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
 447                         clock-names = "iis", "i2s_opclk0";
 448                         dmas = <&pdma0 14>, <&pdma0 13>;
 449                         dma-names = "tx", "rx";
 450                         pinctrl-0 = <&i2s2_bus>;
 451                         pinctrl-names = "default";
 452                         status = "disabled";
 453                 };
 454
 455                 pwm: pwm@139D0000 {
 456                         compatible = "samsung,exynos4210-pwm";
 457                         reg = <0x139D0000 0x1000>;
 458                         interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
 459                                      <0 107 0>, <0 108 0>;
 460                         #pwm-cells = <3>;
 461                         status = "disabled";
 462                 };
 463
 464                 pmu {
 465                         compatible = "arm,cortex-a7-pmu";
 466                         interrupts = <0 18 0>, <0 19 0>;
 467                 };
 468         };
 469 };
 470
 471 #include "exynos3250-pinctrl.dtsi"