Merge tag 'iwlwifi-next-for-kalle-2016-07-01' of git://git.kernel.org/pub/scm/linux...
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / dra7xx-clocks.dtsi
1 /*
2  * Device Tree Source for DRA7xx clock data
3  *
4  * Copyright (C) 2013 Texas Instruments, Inc.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 &cm_core_aon_clocks {
11         atl_clkin0_ck: atl_clkin0_ck {
12                 #clock-cells = <0>;
13                 compatible = "ti,dra7-atl-clock";
14                 clocks = <&atl_gfclk_mux>;
15         };
16
17         atl_clkin1_ck: atl_clkin1_ck {
18                 #clock-cells = <0>;
19                 compatible = "ti,dra7-atl-clock";
20                 clocks = <&atl_gfclk_mux>;
21         };
22
23         atl_clkin2_ck: atl_clkin2_ck {
24                 #clock-cells = <0>;
25                 compatible = "ti,dra7-atl-clock";
26                 clocks = <&atl_gfclk_mux>;
27         };
28
29         atl_clkin3_ck: atl_clkin3_ck {
30                 #clock-cells = <0>;
31                 compatible = "ti,dra7-atl-clock";
32                 clocks = <&atl_gfclk_mux>;
33         };
34
35         hdmi_clkin_ck: hdmi_clkin_ck {
36                 #clock-cells = <0>;
37                 compatible = "fixed-clock";
38                 clock-frequency = <0>;
39         };
40
41         mlb_clkin_ck: mlb_clkin_ck {
42                 #clock-cells = <0>;
43                 compatible = "fixed-clock";
44                 clock-frequency = <0>;
45         };
46
47         mlbp_clkin_ck: mlbp_clkin_ck {
48                 #clock-cells = <0>;
49                 compatible = "fixed-clock";
50                 clock-frequency = <0>;
51         };
52
53         pciesref_acs_clk_ck: pciesref_acs_clk_ck {
54                 #clock-cells = <0>;
55                 compatible = "fixed-clock";
56                 clock-frequency = <100000000>;
57         };
58
59         ref_clkin0_ck: ref_clkin0_ck {
60                 #clock-cells = <0>;
61                 compatible = "fixed-clock";
62                 clock-frequency = <0>;
63         };
64
65         ref_clkin1_ck: ref_clkin1_ck {
66                 #clock-cells = <0>;
67                 compatible = "fixed-clock";
68                 clock-frequency = <0>;
69         };
70
71         ref_clkin2_ck: ref_clkin2_ck {
72                 #clock-cells = <0>;
73                 compatible = "fixed-clock";
74                 clock-frequency = <0>;
75         };
76
77         ref_clkin3_ck: ref_clkin3_ck {
78                 #clock-cells = <0>;
79                 compatible = "fixed-clock";
80                 clock-frequency = <0>;
81         };
82
83         rmii_clk_ck: rmii_clk_ck {
84                 #clock-cells = <0>;
85                 compatible = "fixed-clock";
86                 clock-frequency = <0>;
87         };
88
89         sdvenc_clkin_ck: sdvenc_clkin_ck {
90                 #clock-cells = <0>;
91                 compatible = "fixed-clock";
92                 clock-frequency = <0>;
93         };
94
95         secure_32k_clk_src_ck: secure_32k_clk_src_ck {
96                 #clock-cells = <0>;
97                 compatible = "fixed-clock";
98                 clock-frequency = <32768>;
99         };
100
101         sys_clk32_crystal_ck: sys_clk32_crystal_ck {
102                 #clock-cells = <0>;
103                 compatible = "fixed-clock";
104                 clock-frequency = <32768>;
105         };
106
107         sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
108                 #clock-cells = <0>;
109                 compatible = "fixed-factor-clock";
110                 clocks = <&sys_clkin1>;
111                 clock-mult = <1>;
112                 clock-div = <610>;
113         };
114
115         virt_12000000_ck: virt_12000000_ck {
116                 #clock-cells = <0>;
117                 compatible = "fixed-clock";
118                 clock-frequency = <12000000>;
119         };
120
121         virt_13000000_ck: virt_13000000_ck {
122                 #clock-cells = <0>;
123                 compatible = "fixed-clock";
124                 clock-frequency = <13000000>;
125         };
126
127         virt_16800000_ck: virt_16800000_ck {
128                 #clock-cells = <0>;
129                 compatible = "fixed-clock";
130                 clock-frequency = <16800000>;
131         };
132
133         virt_19200000_ck: virt_19200000_ck {
134                 #clock-cells = <0>;
135                 compatible = "fixed-clock";
136                 clock-frequency = <19200000>;
137         };
138
139         virt_20000000_ck: virt_20000000_ck {
140                 #clock-cells = <0>;
141                 compatible = "fixed-clock";
142                 clock-frequency = <20000000>;
143         };
144
145         virt_26000000_ck: virt_26000000_ck {
146                 #clock-cells = <0>;
147                 compatible = "fixed-clock";
148                 clock-frequency = <26000000>;
149         };
150
151         virt_27000000_ck: virt_27000000_ck {
152                 #clock-cells = <0>;
153                 compatible = "fixed-clock";
154                 clock-frequency = <27000000>;
155         };
156
157         virt_38400000_ck: virt_38400000_ck {
158                 #clock-cells = <0>;
159                 compatible = "fixed-clock";
160                 clock-frequency = <38400000>;
161         };
162
163         sys_clkin2: sys_clkin2 {
164                 #clock-cells = <0>;
165                 compatible = "fixed-clock";
166                 clock-frequency = <22579200>;
167         };
168
169         usb_otg_clkin_ck: usb_otg_clkin_ck {
170                 #clock-cells = <0>;
171                 compatible = "fixed-clock";
172                 clock-frequency = <0>;
173         };
174
175         video1_clkin_ck: video1_clkin_ck {
176                 #clock-cells = <0>;
177                 compatible = "fixed-clock";
178                 clock-frequency = <0>;
179         };
180
181         video1_m2_clkin_ck: video1_m2_clkin_ck {
182                 #clock-cells = <0>;
183                 compatible = "fixed-clock";
184                 clock-frequency = <0>;
185         };
186
187         video2_clkin_ck: video2_clkin_ck {
188                 #clock-cells = <0>;
189                 compatible = "fixed-clock";
190                 clock-frequency = <0>;
191         };
192
193         video2_m2_clkin_ck: video2_m2_clkin_ck {
194                 #clock-cells = <0>;
195                 compatible = "fixed-clock";
196                 clock-frequency = <0>;
197         };
198
199         dpll_abe_ck: dpll_abe_ck@1e0 {
200                 #clock-cells = <0>;
201                 compatible = "ti,omap4-dpll-m4xen-clock";
202                 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
203                 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
204         };
205
206         dpll_abe_x2_ck: dpll_abe_x2_ck {
207                 #clock-cells = <0>;
208                 compatible = "ti,omap4-dpll-x2-clock";
209                 clocks = <&dpll_abe_ck>;
210         };
211
212         dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
213                 #clock-cells = <0>;
214                 compatible = "ti,divider-clock";
215                 clocks = <&dpll_abe_x2_ck>;
216                 ti,max-div = <31>;
217                 ti,autoidle-shift = <8>;
218                 reg = <0x01f0>;
219                 ti,index-starts-at-one;
220                 ti,invert-autoidle-bit;
221         };
222
223         abe_clk: abe_clk@108 {
224                 #clock-cells = <0>;
225                 compatible = "ti,divider-clock";
226                 clocks = <&dpll_abe_m2x2_ck>;
227                 ti,max-div = <4>;
228                 reg = <0x0108>;
229                 ti,index-power-of-two;
230         };
231
232         dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
233                 #clock-cells = <0>;
234                 compatible = "ti,divider-clock";
235                 clocks = <&dpll_abe_ck>;
236                 ti,max-div = <31>;
237                 ti,autoidle-shift = <8>;
238                 reg = <0x01f0>;
239                 ti,index-starts-at-one;
240                 ti,invert-autoidle-bit;
241         };
242
243         dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
244                 #clock-cells = <0>;
245                 compatible = "ti,divider-clock";
246                 clocks = <&dpll_abe_x2_ck>;
247                 ti,max-div = <31>;
248                 ti,autoidle-shift = <8>;
249                 reg = <0x01f4>;
250                 ti,index-starts-at-one;
251                 ti,invert-autoidle-bit;
252         };
253
254         dpll_core_byp_mux: dpll_core_byp_mux@12c {
255                 #clock-cells = <0>;
256                 compatible = "ti,mux-clock";
257                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
258                 ti,bit-shift = <23>;
259                 reg = <0x012c>;
260         };
261
262         dpll_core_ck: dpll_core_ck@120 {
263                 #clock-cells = <0>;
264                 compatible = "ti,omap4-dpll-core-clock";
265                 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
266                 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
267         };
268
269         dpll_core_x2_ck: dpll_core_x2_ck {
270                 #clock-cells = <0>;
271                 compatible = "ti,omap4-dpll-x2-clock";
272                 clocks = <&dpll_core_ck>;
273         };
274
275         dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
276                 #clock-cells = <0>;
277                 compatible = "ti,divider-clock";
278                 clocks = <&dpll_core_x2_ck>;
279                 ti,max-div = <63>;
280                 ti,autoidle-shift = <8>;
281                 reg = <0x013c>;
282                 ti,index-starts-at-one;
283                 ti,invert-autoidle-bit;
284         };
285
286         mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
287                 #clock-cells = <0>;
288                 compatible = "fixed-factor-clock";
289                 clocks = <&dpll_core_h12x2_ck>;
290                 clock-mult = <1>;
291                 clock-div = <1>;
292         };
293
294         dpll_mpu_ck: dpll_mpu_ck@160 {
295                 #clock-cells = <0>;
296                 compatible = "ti,omap5-mpu-dpll-clock";
297                 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
298                 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
299         };
300
301         dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
302                 #clock-cells = <0>;
303                 compatible = "ti,divider-clock";
304                 clocks = <&dpll_mpu_ck>;
305                 ti,max-div = <31>;
306                 ti,autoidle-shift = <8>;
307                 reg = <0x0170>;
308                 ti,index-starts-at-one;
309                 ti,invert-autoidle-bit;
310         };
311
312         mpu_dclk_div: mpu_dclk_div {
313                 #clock-cells = <0>;
314                 compatible = "fixed-factor-clock";
315                 clocks = <&dpll_mpu_m2_ck>;
316                 clock-mult = <1>;
317                 clock-div = <1>;
318         };
319
320         dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
321                 #clock-cells = <0>;
322                 compatible = "fixed-factor-clock";
323                 clocks = <&dpll_core_h12x2_ck>;
324                 clock-mult = <1>;
325                 clock-div = <1>;
326         };
327
328         dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
329                 #clock-cells = <0>;
330                 compatible = "ti,mux-clock";
331                 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
332                 ti,bit-shift = <23>;
333                 reg = <0x0240>;
334         };
335
336         dpll_dsp_ck: dpll_dsp_ck@234 {
337                 #clock-cells = <0>;
338                 compatible = "ti,omap4-dpll-clock";
339                 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
340                 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
341         };
342
343         dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
344                 #clock-cells = <0>;
345                 compatible = "ti,divider-clock";
346                 clocks = <&dpll_dsp_ck>;
347                 ti,max-div = <31>;
348                 ti,autoidle-shift = <8>;
349                 reg = <0x0244>;
350                 ti,index-starts-at-one;
351                 ti,invert-autoidle-bit;
352         };
353
354         iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
355                 #clock-cells = <0>;
356                 compatible = "fixed-factor-clock";
357                 clocks = <&dpll_core_h12x2_ck>;
358                 clock-mult = <1>;
359                 clock-div = <1>;
360         };
361
362         dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
363                 #clock-cells = <0>;
364                 compatible = "ti,mux-clock";
365                 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
366                 ti,bit-shift = <23>;
367                 reg = <0x01ac>;
368         };
369
370         dpll_iva_ck: dpll_iva_ck@1a0 {
371                 #clock-cells = <0>;
372                 compatible = "ti,omap4-dpll-clock";
373                 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
374                 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
375         };
376
377         dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
378                 #clock-cells = <0>;
379                 compatible = "ti,divider-clock";
380                 clocks = <&dpll_iva_ck>;
381                 ti,max-div = <31>;
382                 ti,autoidle-shift = <8>;
383                 reg = <0x01b0>;
384                 ti,index-starts-at-one;
385                 ti,invert-autoidle-bit;
386         };
387
388         iva_dclk: iva_dclk {
389                 #clock-cells = <0>;
390                 compatible = "fixed-factor-clock";
391                 clocks = <&dpll_iva_m2_ck>;
392                 clock-mult = <1>;
393                 clock-div = <1>;
394         };
395
396         dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
397                 #clock-cells = <0>;
398                 compatible = "ti,mux-clock";
399                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
400                 ti,bit-shift = <23>;
401                 reg = <0x02e4>;
402         };
403
404         dpll_gpu_ck: dpll_gpu_ck@2d8 {
405                 #clock-cells = <0>;
406                 compatible = "ti,omap4-dpll-clock";
407                 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
408                 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
409         };
410
411         dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
412                 #clock-cells = <0>;
413                 compatible = "ti,divider-clock";
414                 clocks = <&dpll_gpu_ck>;
415                 ti,max-div = <31>;
416                 ti,autoidle-shift = <8>;
417                 reg = <0x02e8>;
418                 ti,index-starts-at-one;
419                 ti,invert-autoidle-bit;
420         };
421
422         dpll_core_m2_ck: dpll_core_m2_ck@130 {
423                 #clock-cells = <0>;
424                 compatible = "ti,divider-clock";
425                 clocks = <&dpll_core_ck>;
426                 ti,max-div = <31>;
427                 ti,autoidle-shift = <8>;
428                 reg = <0x0130>;
429                 ti,index-starts-at-one;
430                 ti,invert-autoidle-bit;
431         };
432
433         core_dpll_out_dclk_div: core_dpll_out_dclk_div {
434                 #clock-cells = <0>;
435                 compatible = "fixed-factor-clock";
436                 clocks = <&dpll_core_m2_ck>;
437                 clock-mult = <1>;
438                 clock-div = <1>;
439         };
440
441         dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
442                 #clock-cells = <0>;
443                 compatible = "ti,mux-clock";
444                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
445                 ti,bit-shift = <23>;
446                 reg = <0x021c>;
447         };
448
449         dpll_ddr_ck: dpll_ddr_ck@210 {
450                 #clock-cells = <0>;
451                 compatible = "ti,omap4-dpll-clock";
452                 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
453                 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
454         };
455
456         dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
457                 #clock-cells = <0>;
458                 compatible = "ti,divider-clock";
459                 clocks = <&dpll_ddr_ck>;
460                 ti,max-div = <31>;
461                 ti,autoidle-shift = <8>;
462                 reg = <0x0220>;
463                 ti,index-starts-at-one;
464                 ti,invert-autoidle-bit;
465         };
466
467         dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
468                 #clock-cells = <0>;
469                 compatible = "ti,mux-clock";
470                 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
471                 ti,bit-shift = <23>;
472                 reg = <0x02b4>;
473         };
474
475         dpll_gmac_ck: dpll_gmac_ck@2a8 {
476                 #clock-cells = <0>;
477                 compatible = "ti,omap4-dpll-clock";
478                 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
479                 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
480         };
481
482         dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
483                 #clock-cells = <0>;
484                 compatible = "ti,divider-clock";
485                 clocks = <&dpll_gmac_ck>;
486                 ti,max-div = <31>;
487                 ti,autoidle-shift = <8>;
488                 reg = <0x02b8>;
489                 ti,index-starts-at-one;
490                 ti,invert-autoidle-bit;
491         };
492
493         video2_dclk_div: video2_dclk_div {
494                 #clock-cells = <0>;
495                 compatible = "fixed-factor-clock";
496                 clocks = <&video2_m2_clkin_ck>;
497                 clock-mult = <1>;
498                 clock-div = <1>;
499         };
500
501         video1_dclk_div: video1_dclk_div {
502                 #clock-cells = <0>;
503                 compatible = "fixed-factor-clock";
504                 clocks = <&video1_m2_clkin_ck>;
505                 clock-mult = <1>;
506                 clock-div = <1>;
507         };
508
509         hdmi_dclk_div: hdmi_dclk_div {
510                 #clock-cells = <0>;
511                 compatible = "fixed-factor-clock";
512                 clocks = <&hdmi_clkin_ck>;
513                 clock-mult = <1>;
514                 clock-div = <1>;
515         };
516
517         per_dpll_hs_clk_div: per_dpll_hs_clk_div {
518                 #clock-cells = <0>;
519                 compatible = "fixed-factor-clock";
520                 clocks = <&dpll_abe_m3x2_ck>;
521                 clock-mult = <1>;
522                 clock-div = <2>;
523         };
524
525         usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
526                 #clock-cells = <0>;
527                 compatible = "fixed-factor-clock";
528                 clocks = <&dpll_abe_m3x2_ck>;
529                 clock-mult = <1>;
530                 clock-div = <3>;
531         };
532
533         eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
534                 #clock-cells = <0>;
535                 compatible = "fixed-factor-clock";
536                 clocks = <&dpll_core_h12x2_ck>;
537                 clock-mult = <1>;
538                 clock-div = <1>;
539         };
540
541         dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
542                 #clock-cells = <0>;
543                 compatible = "ti,mux-clock";
544                 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
545                 ti,bit-shift = <23>;
546                 reg = <0x0290>;
547         };
548
549         dpll_eve_ck: dpll_eve_ck@284 {
550                 #clock-cells = <0>;
551                 compatible = "ti,omap4-dpll-clock";
552                 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
553                 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
554         };
555
556         dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
557                 #clock-cells = <0>;
558                 compatible = "ti,divider-clock";
559                 clocks = <&dpll_eve_ck>;
560                 ti,max-div = <31>;
561                 ti,autoidle-shift = <8>;
562                 reg = <0x0294>;
563                 ti,index-starts-at-one;
564                 ti,invert-autoidle-bit;
565         };
566
567         eve_dclk_div: eve_dclk_div {
568                 #clock-cells = <0>;
569                 compatible = "fixed-factor-clock";
570                 clocks = <&dpll_eve_m2_ck>;
571                 clock-mult = <1>;
572                 clock-div = <1>;
573         };
574
575         dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
576                 #clock-cells = <0>;
577                 compatible = "ti,divider-clock";
578                 clocks = <&dpll_core_x2_ck>;
579                 ti,max-div = <63>;
580                 ti,autoidle-shift = <8>;
581                 reg = <0x0140>;
582                 ti,index-starts-at-one;
583                 ti,invert-autoidle-bit;
584         };
585
586         dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
587                 #clock-cells = <0>;
588                 compatible = "ti,divider-clock";
589                 clocks = <&dpll_core_x2_ck>;
590                 ti,max-div = <63>;
591                 ti,autoidle-shift = <8>;
592                 reg = <0x0144>;
593                 ti,index-starts-at-one;
594                 ti,invert-autoidle-bit;
595         };
596
597         dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
598                 #clock-cells = <0>;
599                 compatible = "ti,divider-clock";
600                 clocks = <&dpll_core_x2_ck>;
601                 ti,max-div = <63>;
602                 ti,autoidle-shift = <8>;
603                 reg = <0x0154>;
604                 ti,index-starts-at-one;
605                 ti,invert-autoidle-bit;
606         };
607
608         dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
609                 #clock-cells = <0>;
610                 compatible = "ti,divider-clock";
611                 clocks = <&dpll_core_x2_ck>;
612                 ti,max-div = <63>;
613                 ti,autoidle-shift = <8>;
614                 reg = <0x0158>;
615                 ti,index-starts-at-one;
616                 ti,invert-autoidle-bit;
617         };
618
619         dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
620                 #clock-cells = <0>;
621                 compatible = "ti,divider-clock";
622                 clocks = <&dpll_core_x2_ck>;
623                 ti,max-div = <63>;
624                 ti,autoidle-shift = <8>;
625                 reg = <0x015c>;
626                 ti,index-starts-at-one;
627                 ti,invert-autoidle-bit;
628         };
629
630         dpll_ddr_x2_ck: dpll_ddr_x2_ck {
631                 #clock-cells = <0>;
632                 compatible = "ti,omap4-dpll-x2-clock";
633                 clocks = <&dpll_ddr_ck>;
634         };
635
636         dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
637                 #clock-cells = <0>;
638                 compatible = "ti,divider-clock";
639                 clocks = <&dpll_ddr_x2_ck>;
640                 ti,max-div = <63>;
641                 ti,autoidle-shift = <8>;
642                 reg = <0x0228>;
643                 ti,index-starts-at-one;
644                 ti,invert-autoidle-bit;
645         };
646
647         dpll_dsp_x2_ck: dpll_dsp_x2_ck {
648                 #clock-cells = <0>;
649                 compatible = "ti,omap4-dpll-x2-clock";
650                 clocks = <&dpll_dsp_ck>;
651         };
652
653         dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
654                 #clock-cells = <0>;
655                 compatible = "ti,divider-clock";
656                 clocks = <&dpll_dsp_x2_ck>;
657                 ti,max-div = <31>;
658                 ti,autoidle-shift = <8>;
659                 reg = <0x0248>;
660                 ti,index-starts-at-one;
661                 ti,invert-autoidle-bit;
662         };
663
664         dpll_gmac_x2_ck: dpll_gmac_x2_ck {
665                 #clock-cells = <0>;
666                 compatible = "ti,omap4-dpll-x2-clock";
667                 clocks = <&dpll_gmac_ck>;
668         };
669
670         dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
671                 #clock-cells = <0>;
672                 compatible = "ti,divider-clock";
673                 clocks = <&dpll_gmac_x2_ck>;
674                 ti,max-div = <63>;
675                 ti,autoidle-shift = <8>;
676                 reg = <0x02c0>;
677                 ti,index-starts-at-one;
678                 ti,invert-autoidle-bit;
679         };
680
681         dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
682                 #clock-cells = <0>;
683                 compatible = "ti,divider-clock";
684                 clocks = <&dpll_gmac_x2_ck>;
685                 ti,max-div = <63>;
686                 ti,autoidle-shift = <8>;
687                 reg = <0x02c4>;
688                 ti,index-starts-at-one;
689                 ti,invert-autoidle-bit;
690         };
691
692         dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
693                 #clock-cells = <0>;
694                 compatible = "ti,divider-clock";
695                 clocks = <&dpll_gmac_x2_ck>;
696                 ti,max-div = <63>;
697                 ti,autoidle-shift = <8>;
698                 reg = <0x02c8>;
699                 ti,index-starts-at-one;
700                 ti,invert-autoidle-bit;
701         };
702
703         dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
704                 #clock-cells = <0>;
705                 compatible = "ti,divider-clock";
706                 clocks = <&dpll_gmac_x2_ck>;
707                 ti,max-div = <31>;
708                 ti,autoidle-shift = <8>;
709                 reg = <0x02bc>;
710                 ti,index-starts-at-one;
711                 ti,invert-autoidle-bit;
712         };
713
714         gmii_m_clk_div: gmii_m_clk_div {
715                 #clock-cells = <0>;
716                 compatible = "fixed-factor-clock";
717                 clocks = <&dpll_gmac_h11x2_ck>;
718                 clock-mult = <1>;
719                 clock-div = <2>;
720         };
721
722         hdmi_clk2_div: hdmi_clk2_div {
723                 #clock-cells = <0>;
724                 compatible = "fixed-factor-clock";
725                 clocks = <&hdmi_clkin_ck>;
726                 clock-mult = <1>;
727                 clock-div = <1>;
728         };
729
730         hdmi_div_clk: hdmi_div_clk {
731                 #clock-cells = <0>;
732                 compatible = "fixed-factor-clock";
733                 clocks = <&hdmi_clkin_ck>;
734                 clock-mult = <1>;
735                 clock-div = <1>;
736         };
737
738         l3_iclk_div: l3_iclk_div@100 {
739                 #clock-cells = <0>;
740                 compatible = "ti,divider-clock";
741                 ti,max-div = <2>;
742                 ti,bit-shift = <4>;
743                 reg = <0x0100>;
744                 clocks = <&dpll_core_h12x2_ck>;
745                 ti,index-power-of-two;
746         };
747
748         l4_root_clk_div: l4_root_clk_div {
749                 #clock-cells = <0>;
750                 compatible = "fixed-factor-clock";
751                 clocks = <&l3_iclk_div>;
752                 clock-mult = <1>;
753                 clock-div = <2>;
754         };
755
756         video1_clk2_div: video1_clk2_div {
757                 #clock-cells = <0>;
758                 compatible = "fixed-factor-clock";
759                 clocks = <&video1_clkin_ck>;
760                 clock-mult = <1>;
761                 clock-div = <1>;
762         };
763
764         video1_div_clk: video1_div_clk {
765                 #clock-cells = <0>;
766                 compatible = "fixed-factor-clock";
767                 clocks = <&video1_clkin_ck>;
768                 clock-mult = <1>;
769                 clock-div = <1>;
770         };
771
772         video2_clk2_div: video2_clk2_div {
773                 #clock-cells = <0>;
774                 compatible = "fixed-factor-clock";
775                 clocks = <&video2_clkin_ck>;
776                 clock-mult = <1>;
777                 clock-div = <1>;
778         };
779
780         video2_div_clk: video2_div_clk {
781                 #clock-cells = <0>;
782                 compatible = "fixed-factor-clock";
783                 clocks = <&video2_clkin_ck>;
784                 clock-mult = <1>;
785                 clock-div = <1>;
786         };
787
788         ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
789                 #clock-cells = <0>;
790                 compatible = "ti,mux-clock";
791                 clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
792                 ti,bit-shift = <24>;
793                 reg = <0x0520>;
794         };
795
796         mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
797                 #clock-cells = <0>;
798                 compatible = "ti,mux-clock";
799                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
800                 ti,bit-shift = <28>;
801                 reg = <0x0550>;
802         };
803
804         mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
805                 #clock-cells = <0>;
806                 compatible = "ti,mux-clock";
807                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
808                 ti,bit-shift = <24>;
809                 reg = <0x0550>;
810         };
811
812         mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
813                 #clock-cells = <0>;
814                 compatible = "ti,mux-clock";
815                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
816                 ti,bit-shift = <22>;
817                 reg = <0x0550>;
818         };
819
820         timer5_gfclk_mux: timer5_gfclk_mux@558 {
821                 #clock-cells = <0>;
822                 compatible = "ti,mux-clock";
823                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
824                 ti,bit-shift = <24>;
825                 reg = <0x0558>;
826         };
827
828         timer6_gfclk_mux: timer6_gfclk_mux@560 {
829                 #clock-cells = <0>;
830                 compatible = "ti,mux-clock";
831                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
832                 ti,bit-shift = <24>;
833                 reg = <0x0560>;
834         };
835
836         timer7_gfclk_mux: timer7_gfclk_mux@568 {
837                 #clock-cells = <0>;
838                 compatible = "ti,mux-clock";
839                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
840                 ti,bit-shift = <24>;
841                 reg = <0x0568>;
842         };
843
844         timer8_gfclk_mux: timer8_gfclk_mux@570 {
845                 #clock-cells = <0>;
846                 compatible = "ti,mux-clock";
847                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
848                 ti,bit-shift = <24>;
849                 reg = <0x0570>;
850         };
851
852         uart6_gfclk_mux: uart6_gfclk_mux@580 {
853                 #clock-cells = <0>;
854                 compatible = "ti,mux-clock";
855                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
856                 ti,bit-shift = <24>;
857                 reg = <0x0580>;
858         };
859
860         dummy_ck: dummy_ck {
861                 #clock-cells = <0>;
862                 compatible = "fixed-clock";
863                 clock-frequency = <0>;
864         };
865 };
866 &prm_clocks {
867         sys_clkin1: sys_clkin1@110 {
868                 #clock-cells = <0>;
869                 compatible = "ti,mux-clock";
870                 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
871                 reg = <0x0110>;
872                 ti,index-starts-at-one;
873         };
874
875         abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
876                 #clock-cells = <0>;
877                 compatible = "ti,mux-clock";
878                 clocks = <&sys_clkin1>, <&sys_clkin2>;
879                 reg = <0x0118>;
880         };
881
882         abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
883                 #clock-cells = <0>;
884                 compatible = "ti,mux-clock";
885                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
886                 reg = <0x0114>;
887         };
888
889         abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
890                 #clock-cells = <0>;
891                 compatible = "ti,mux-clock";
892                 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
893                 reg = <0x010c>;
894         };
895
896         abe_24m_fclk: abe_24m_fclk@11c {
897                 #clock-cells = <0>;
898                 compatible = "ti,divider-clock";
899                 clocks = <&dpll_abe_m2x2_ck>;
900                 reg = <0x011c>;
901                 ti,dividers = <8>, <16>;
902         };
903
904         aess_fclk: aess_fclk@178 {
905                 #clock-cells = <0>;
906                 compatible = "ti,divider-clock";
907                 clocks = <&abe_clk>;
908                 reg = <0x0178>;
909                 ti,max-div = <2>;
910         };
911
912         abe_giclk_div: abe_giclk_div@174 {
913                 #clock-cells = <0>;
914                 compatible = "ti,divider-clock";
915                 clocks = <&aess_fclk>;
916                 reg = <0x0174>;
917                 ti,max-div = <2>;
918         };
919
920         abe_lp_clk_div: abe_lp_clk_div@1d8 {
921                 #clock-cells = <0>;
922                 compatible = "ti,divider-clock";
923                 clocks = <&dpll_abe_m2x2_ck>;
924                 reg = <0x01d8>;
925                 ti,dividers = <16>, <32>;
926         };
927
928         abe_sys_clk_div: abe_sys_clk_div@120 {
929                 #clock-cells = <0>;
930                 compatible = "ti,divider-clock";
931                 clocks = <&sys_clkin1>;
932                 reg = <0x0120>;
933                 ti,max-div = <2>;
934         };
935
936         adc_gfclk_mux: adc_gfclk_mux@1dc {
937                 #clock-cells = <0>;
938                 compatible = "ti,mux-clock";
939                 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
940                 reg = <0x01dc>;
941         };
942
943         sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
944                 #clock-cells = <0>;
945                 compatible = "ti,divider-clock";
946                 clocks = <&sys_clkin1>;
947                 ti,max-div = <64>;
948                 reg = <0x01c8>;
949                 ti,index-power-of-two;
950         };
951
952         sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
953                 #clock-cells = <0>;
954                 compatible = "ti,divider-clock";
955                 clocks = <&sys_clkin2>;
956                 ti,max-div = <64>;
957                 reg = <0x01cc>;
958                 ti,index-power-of-two;
959         };
960
961         per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
962                 #clock-cells = <0>;
963                 compatible = "ti,divider-clock";
964                 clocks = <&dpll_abe_m2_ck>;
965                 ti,max-div = <64>;
966                 reg = <0x01bc>;
967                 ti,index-power-of-two;
968         };
969
970         dsp_gclk_div: dsp_gclk_div@18c {
971                 #clock-cells = <0>;
972                 compatible = "ti,divider-clock";
973                 clocks = <&dpll_dsp_m2_ck>;
974                 ti,max-div = <64>;
975                 reg = <0x018c>;
976                 ti,index-power-of-two;
977         };
978
979         gpu_dclk: gpu_dclk@1a0 {
980                 #clock-cells = <0>;
981                 compatible = "ti,divider-clock";
982                 clocks = <&dpll_gpu_m2_ck>;
983                 ti,max-div = <64>;
984                 reg = <0x01a0>;
985                 ti,index-power-of-two;
986         };
987
988         emif_phy_dclk_div: emif_phy_dclk_div@190 {
989                 #clock-cells = <0>;
990                 compatible = "ti,divider-clock";
991                 clocks = <&dpll_ddr_m2_ck>;
992                 ti,max-div = <64>;
993                 reg = <0x0190>;
994                 ti,index-power-of-two;
995         };
996
997         gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
998                 #clock-cells = <0>;
999                 compatible = "ti,divider-clock";
1000                 clocks = <&dpll_gmac_m2_ck>;
1001                 ti,max-div = <64>;
1002                 reg = <0x019c>;
1003                 ti,index-power-of-two;
1004         };
1005
1006         l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
1007                 #clock-cells = <0>;
1008                 compatible = "ti,divider-clock";
1009                 clocks = <&dpll_usb_m2_ck>;
1010                 ti,max-div = <64>;
1011                 reg = <0x01ac>;
1012                 ti,index-power-of-two;
1013         };
1014
1015         usb_otg_dclk_div: usb_otg_dclk_div@184 {
1016                 #clock-cells = <0>;
1017                 compatible = "ti,divider-clock";
1018                 clocks = <&usb_otg_clkin_ck>;
1019                 ti,max-div = <64>;
1020                 reg = <0x0184>;
1021                 ti,index-power-of-two;
1022         };
1023
1024         sata_dclk_div: sata_dclk_div@1c0 {
1025                 #clock-cells = <0>;
1026                 compatible = "ti,divider-clock";
1027                 clocks = <&sys_clkin1>;
1028                 ti,max-div = <64>;
1029                 reg = <0x01c0>;
1030                 ti,index-power-of-two;
1031         };
1032
1033         pcie2_dclk_div: pcie2_dclk_div@1b8 {
1034                 #clock-cells = <0>;
1035                 compatible = "ti,divider-clock";
1036                 clocks = <&dpll_pcie_ref_m2_ck>;
1037                 ti,max-div = <64>;
1038                 reg = <0x01b8>;
1039                 ti,index-power-of-two;
1040         };
1041
1042         pcie_dclk_div: pcie_dclk_div@1b4 {
1043                 #clock-cells = <0>;
1044                 compatible = "ti,divider-clock";
1045                 clocks = <&apll_pcie_m2_ck>;
1046                 ti,max-div = <64>;
1047                 reg = <0x01b4>;
1048                 ti,index-power-of-two;
1049         };
1050
1051         emu_dclk_div: emu_dclk_div@194 {
1052                 #clock-cells = <0>;
1053                 compatible = "ti,divider-clock";
1054                 clocks = <&sys_clkin1>;
1055                 ti,max-div = <64>;
1056                 reg = <0x0194>;
1057                 ti,index-power-of-two;
1058         };
1059
1060         secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
1061                 #clock-cells = <0>;
1062                 compatible = "ti,divider-clock";
1063                 clocks = <&secure_32k_clk_src_ck>;
1064                 ti,max-div = <64>;
1065                 reg = <0x01c4>;
1066                 ti,index-power-of-two;
1067         };
1068
1069         clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
1070                 #clock-cells = <0>;
1071                 compatible = "ti,mux-clock";
1072                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1073                 reg = <0x0158>;
1074         };
1075
1076         clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
1077                 #clock-cells = <0>;
1078                 compatible = "ti,mux-clock";
1079                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1080                 reg = <0x015c>;
1081         };
1082
1083         clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
1084                 #clock-cells = <0>;
1085                 compatible = "ti,mux-clock";
1086                 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1087                 reg = <0x0160>;
1088         };
1089
1090         custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1091                 #clock-cells = <0>;
1092                 compatible = "fixed-factor-clock";
1093                 clocks = <&sys_clkin1>;
1094                 clock-mult = <1>;
1095                 clock-div = <2>;
1096         };
1097
1098         eve_clk: eve_clk@180 {
1099                 #clock-cells = <0>;
1100                 compatible = "ti,mux-clock";
1101                 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1102                 reg = <0x0180>;
1103         };
1104
1105         hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
1106                 #clock-cells = <0>;
1107                 compatible = "ti,mux-clock";
1108                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1109                 reg = <0x0164>;
1110         };
1111
1112         mlb_clk: mlb_clk@134 {
1113                 #clock-cells = <0>;
1114                 compatible = "ti,divider-clock";
1115                 clocks = <&mlb_clkin_ck>;
1116                 ti,max-div = <64>;
1117                 reg = <0x0134>;
1118                 ti,index-power-of-two;
1119         };
1120
1121         mlbp_clk: mlbp_clk@130 {
1122                 #clock-cells = <0>;
1123                 compatible = "ti,divider-clock";
1124                 clocks = <&mlbp_clkin_ck>;
1125                 ti,max-div = <64>;
1126                 reg = <0x0130>;
1127                 ti,index-power-of-two;
1128         };
1129
1130         per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
1131                 #clock-cells = <0>;
1132                 compatible = "ti,divider-clock";
1133                 clocks = <&dpll_abe_m2_ck>;
1134                 ti,max-div = <64>;
1135                 reg = <0x0138>;
1136                 ti,index-power-of-two;
1137         };
1138
1139         timer_sys_clk_div: timer_sys_clk_div@144 {
1140                 #clock-cells = <0>;
1141                 compatible = "ti,divider-clock";
1142                 clocks = <&sys_clkin1>;
1143                 reg = <0x0144>;
1144                 ti,max-div = <2>;
1145         };
1146
1147         video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
1148                 #clock-cells = <0>;
1149                 compatible = "ti,mux-clock";
1150                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1151                 reg = <0x0168>;
1152         };
1153
1154         video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
1155                 #clock-cells = <0>;
1156                 compatible = "ti,mux-clock";
1157                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1158                 reg = <0x016c>;
1159         };
1160
1161         wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
1162                 #clock-cells = <0>;
1163                 compatible = "ti,mux-clock";
1164                 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1165                 reg = <0x0108>;
1166         };
1167
1168         gpio1_dbclk: gpio1_dbclk@1838 {
1169                 #clock-cells = <0>;
1170                 compatible = "ti,gate-clock";
1171                 clocks = <&sys_32k_ck>;
1172                 ti,bit-shift = <8>;
1173                 reg = <0x1838>;
1174         };
1175
1176         dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
1177                 #clock-cells = <0>;
1178                 compatible = "ti,mux-clock";
1179                 clocks = <&sys_clkin1>, <&sys_clkin2>;
1180                 ti,bit-shift = <24>;
1181                 reg = <0x1888>;
1182         };
1183
1184         timer1_gfclk_mux: timer1_gfclk_mux@1840 {
1185                 #clock-cells = <0>;
1186                 compatible = "ti,mux-clock";
1187                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1188                 ti,bit-shift = <24>;
1189                 reg = <0x1840>;
1190         };
1191
1192         uart10_gfclk_mux: uart10_gfclk_mux@1880 {
1193                 #clock-cells = <0>;
1194                 compatible = "ti,mux-clock";
1195                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1196                 ti,bit-shift = <24>;
1197                 reg = <0x1880>;
1198         };
1199 };
1200 &cm_core_clocks {
1201         dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
1202                 #clock-cells = <0>;
1203                 compatible = "ti,omap4-dpll-clock";
1204                 clocks = <&sys_clkin1>, <&sys_clkin1>;
1205                 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1206         };
1207
1208         dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
1209                 #clock-cells = <0>;
1210                 compatible = "ti,divider-clock";
1211                 clocks = <&dpll_pcie_ref_ck>;
1212                 ti,max-div = <31>;
1213                 ti,autoidle-shift = <8>;
1214                 reg = <0x0210>;
1215                 ti,index-starts-at-one;
1216                 ti,invert-autoidle-bit;
1217         };
1218
1219         apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1220                 compatible = "ti,mux-clock";
1221                 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1222                 #clock-cells = <0>;
1223                 reg = <0x021c 0x4>;
1224                 ti,bit-shift = <7>;
1225         };
1226
1227         apll_pcie_ck: apll_pcie_ck@21c {
1228                 #clock-cells = <0>;
1229                 compatible = "ti,dra7-apll-clock";
1230                 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1231                 reg = <0x021c>, <0x0220>;
1232         };
1233
1234         optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
1235                 compatible = "ti,gate-clock";
1236                 clocks = <&sys_32k_ck>;
1237                 #clock-cells = <0>;
1238                 reg = <0x13b0>;
1239                 ti,bit-shift = <8>;
1240         };
1241
1242         optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
1243                 compatible = "ti,gate-clock";
1244                 clocks = <&sys_32k_ck>;
1245                 #clock-cells = <0>;
1246                 reg = <0x13b8>;
1247                 ti,bit-shift = <8>;
1248         };
1249
1250         optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1251                 compatible = "ti,divider-clock";
1252                 clocks = <&apll_pcie_ck>;
1253                 #clock-cells = <0>;
1254                 reg = <0x021c>;
1255                 ti,dividers = <2>, <1>;
1256                 ti,bit-shift = <8>;
1257                 ti,max-div = <2>;
1258         };
1259
1260         optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
1261                 compatible = "ti,gate-clock";
1262                 clocks = <&apll_pcie_ck>;
1263                 #clock-cells = <0>;
1264                 reg = <0x13b0>;
1265                 ti,bit-shift = <9>;
1266         };
1267
1268         optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
1269                 compatible = "ti,gate-clock";
1270                 clocks = <&apll_pcie_ck>;
1271                 #clock-cells = <0>;
1272                 reg = <0x13b8>;
1273                 ti,bit-shift = <9>;
1274         };
1275
1276         optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
1277                 compatible = "ti,gate-clock";
1278                 clocks = <&optfclk_pciephy_div>;
1279                 #clock-cells = <0>;
1280                 reg = <0x13b0>;
1281                 ti,bit-shift = <10>;
1282         };
1283
1284         optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
1285                 compatible = "ti,gate-clock";
1286                 clocks = <&optfclk_pciephy_div>;
1287                 #clock-cells = <0>;
1288                 reg = <0x13b8>;
1289                 ti,bit-shift = <10>;
1290         };
1291
1292         apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1293                 #clock-cells = <0>;
1294                 compatible = "fixed-factor-clock";
1295                 clocks = <&apll_pcie_ck>;
1296                 clock-mult = <1>;
1297                 clock-div = <1>;
1298         };
1299
1300         apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1301                 #clock-cells = <0>;
1302                 compatible = "fixed-factor-clock";
1303                 clocks = <&apll_pcie_ck>;
1304                 clock-mult = <1>;
1305                 clock-div = <1>;
1306         };
1307
1308         apll_pcie_m2_ck: apll_pcie_m2_ck {
1309                 #clock-cells = <0>;
1310                 compatible = "fixed-factor-clock";
1311                 clocks = <&apll_pcie_ck>;
1312                 clock-mult = <1>;
1313                 clock-div = <1>;
1314         };
1315
1316         dpll_per_byp_mux: dpll_per_byp_mux@14c {
1317                 #clock-cells = <0>;
1318                 compatible = "ti,mux-clock";
1319                 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1320                 ti,bit-shift = <23>;
1321                 reg = <0x014c>;
1322         };
1323
1324         dpll_per_ck: dpll_per_ck@140 {
1325                 #clock-cells = <0>;
1326                 compatible = "ti,omap4-dpll-clock";
1327                 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1328                 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1329         };
1330
1331         dpll_per_m2_ck: dpll_per_m2_ck@150 {
1332                 #clock-cells = <0>;
1333                 compatible = "ti,divider-clock";
1334                 clocks = <&dpll_per_ck>;
1335                 ti,max-div = <31>;
1336                 ti,autoidle-shift = <8>;
1337                 reg = <0x0150>;
1338                 ti,index-starts-at-one;
1339                 ti,invert-autoidle-bit;
1340         };
1341
1342         func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1343                 #clock-cells = <0>;
1344                 compatible = "fixed-factor-clock";
1345                 clocks = <&dpll_per_m2_ck>;
1346                 clock-mult = <1>;
1347                 clock-div = <1>;
1348         };
1349
1350         dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
1351                 #clock-cells = <0>;
1352                 compatible = "ti,mux-clock";
1353                 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1354                 ti,bit-shift = <23>;
1355                 reg = <0x018c>;
1356         };
1357
1358         dpll_usb_ck: dpll_usb_ck@180 {
1359                 #clock-cells = <0>;
1360                 compatible = "ti,omap4-dpll-j-type-clock";
1361                 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1362                 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1363         };
1364
1365         dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
1366                 #clock-cells = <0>;
1367                 compatible = "ti,divider-clock";
1368                 clocks = <&dpll_usb_ck>;
1369                 ti,max-div = <127>;
1370                 ti,autoidle-shift = <8>;
1371                 reg = <0x0190>;
1372                 ti,index-starts-at-one;
1373                 ti,invert-autoidle-bit;
1374         };
1375
1376         dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
1377                 #clock-cells = <0>;
1378                 compatible = "ti,divider-clock";
1379                 clocks = <&dpll_pcie_ref_ck>;
1380                 ti,max-div = <127>;
1381                 ti,autoidle-shift = <8>;
1382                 reg = <0x0210>;
1383                 ti,index-starts-at-one;
1384                 ti,invert-autoidle-bit;
1385         };
1386
1387         dpll_per_x2_ck: dpll_per_x2_ck {
1388                 #clock-cells = <0>;
1389                 compatible = "ti,omap4-dpll-x2-clock";
1390                 clocks = <&dpll_per_ck>;
1391         };
1392
1393         dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
1394                 #clock-cells = <0>;
1395                 compatible = "ti,divider-clock";
1396                 clocks = <&dpll_per_x2_ck>;
1397                 ti,max-div = <63>;
1398                 ti,autoidle-shift = <8>;
1399                 reg = <0x0158>;
1400                 ti,index-starts-at-one;
1401                 ti,invert-autoidle-bit;
1402         };
1403
1404         dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
1405                 #clock-cells = <0>;
1406                 compatible = "ti,divider-clock";
1407                 clocks = <&dpll_per_x2_ck>;
1408                 ti,max-div = <63>;
1409                 ti,autoidle-shift = <8>;
1410                 reg = <0x015c>;
1411                 ti,index-starts-at-one;
1412                 ti,invert-autoidle-bit;
1413         };
1414
1415         dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
1416                 #clock-cells = <0>;
1417                 compatible = "ti,divider-clock";
1418                 clocks = <&dpll_per_x2_ck>;
1419                 ti,max-div = <63>;
1420                 ti,autoidle-shift = <8>;
1421                 reg = <0x0160>;
1422                 ti,index-starts-at-one;
1423                 ti,invert-autoidle-bit;
1424         };
1425
1426         dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
1427                 #clock-cells = <0>;
1428                 compatible = "ti,divider-clock";
1429                 clocks = <&dpll_per_x2_ck>;
1430                 ti,max-div = <63>;
1431                 ti,autoidle-shift = <8>;
1432                 reg = <0x0164>;
1433                 ti,index-starts-at-one;
1434                 ti,invert-autoidle-bit;
1435         };
1436
1437         dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
1438                 #clock-cells = <0>;
1439                 compatible = "ti,divider-clock";
1440                 clocks = <&dpll_per_x2_ck>;
1441                 ti,max-div = <31>;
1442                 ti,autoidle-shift = <8>;
1443                 reg = <0x0150>;
1444                 ti,index-starts-at-one;
1445                 ti,invert-autoidle-bit;
1446         };
1447
1448         dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1449                 #clock-cells = <0>;
1450                 compatible = "fixed-factor-clock";
1451                 clocks = <&dpll_usb_ck>;
1452                 clock-mult = <1>;
1453                 clock-div = <1>;
1454         };
1455
1456         func_128m_clk: func_128m_clk {
1457                 #clock-cells = <0>;
1458                 compatible = "fixed-factor-clock";
1459                 clocks = <&dpll_per_h11x2_ck>;
1460                 clock-mult = <1>;
1461                 clock-div = <2>;
1462         };
1463
1464         func_12m_fclk: func_12m_fclk {
1465                 #clock-cells = <0>;
1466                 compatible = "fixed-factor-clock";
1467                 clocks = <&dpll_per_m2x2_ck>;
1468                 clock-mult = <1>;
1469                 clock-div = <16>;
1470         };
1471
1472         func_24m_clk: func_24m_clk {
1473                 #clock-cells = <0>;
1474                 compatible = "fixed-factor-clock";
1475                 clocks = <&dpll_per_m2_ck>;
1476                 clock-mult = <1>;
1477                 clock-div = <4>;
1478         };
1479
1480         func_48m_fclk: func_48m_fclk {
1481                 #clock-cells = <0>;
1482                 compatible = "fixed-factor-clock";
1483                 clocks = <&dpll_per_m2x2_ck>;
1484                 clock-mult = <1>;
1485                 clock-div = <4>;
1486         };
1487
1488         func_96m_fclk: func_96m_fclk {
1489                 #clock-cells = <0>;
1490                 compatible = "fixed-factor-clock";
1491                 clocks = <&dpll_per_m2x2_ck>;
1492                 clock-mult = <1>;
1493                 clock-div = <2>;
1494         };
1495
1496         l3init_60m_fclk: l3init_60m_fclk@104 {
1497                 #clock-cells = <0>;
1498                 compatible = "ti,divider-clock";
1499                 clocks = <&dpll_usb_m2_ck>;
1500                 reg = <0x0104>;
1501                 ti,dividers = <1>, <8>;
1502         };
1503
1504         clkout2_clk: clkout2_clk@6b0 {
1505                 #clock-cells = <0>;
1506                 compatible = "ti,gate-clock";
1507                 clocks = <&clkoutmux2_clk_mux>;
1508                 ti,bit-shift = <8>;
1509                 reg = <0x06b0>;
1510         };
1511
1512         l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
1513                 #clock-cells = <0>;
1514                 compatible = "ti,gate-clock";
1515                 clocks = <&dpll_usb_clkdcoldo>;
1516                 ti,bit-shift = <8>;
1517                 reg = <0x06c0>;
1518         };
1519
1520         dss_32khz_clk: dss_32khz_clk@1120 {
1521                 #clock-cells = <0>;
1522                 compatible = "ti,gate-clock";
1523                 clocks = <&sys_32k_ck>;
1524                 ti,bit-shift = <11>;
1525                 reg = <0x1120>;
1526         };
1527
1528         dss_48mhz_clk: dss_48mhz_clk@1120 {
1529                 #clock-cells = <0>;
1530                 compatible = "ti,gate-clock";
1531                 clocks = <&func_48m_fclk>;
1532                 ti,bit-shift = <9>;
1533                 reg = <0x1120>;
1534         };
1535
1536         dss_dss_clk: dss_dss_clk@1120 {
1537                 #clock-cells = <0>;
1538                 compatible = "ti,gate-clock";
1539                 clocks = <&dpll_per_h12x2_ck>;
1540                 ti,bit-shift = <8>;
1541                 reg = <0x1120>;
1542                 ti,set-rate-parent;
1543         };
1544
1545         dss_hdmi_clk: dss_hdmi_clk@1120 {
1546                 #clock-cells = <0>;
1547                 compatible = "ti,gate-clock";
1548                 clocks = <&hdmi_dpll_clk_mux>;
1549                 ti,bit-shift = <10>;
1550                 reg = <0x1120>;
1551         };
1552
1553         dss_video1_clk: dss_video1_clk@1120 {
1554                 #clock-cells = <0>;
1555                 compatible = "ti,gate-clock";
1556                 clocks = <&video1_dpll_clk_mux>;
1557                 ti,bit-shift = <12>;
1558                 reg = <0x1120>;
1559         };
1560
1561         dss_video2_clk: dss_video2_clk@1120 {
1562                 #clock-cells = <0>;
1563                 compatible = "ti,gate-clock";
1564                 clocks = <&video2_dpll_clk_mux>;
1565                 ti,bit-shift = <13>;
1566                 reg = <0x1120>;
1567         };
1568
1569         gpio2_dbclk: gpio2_dbclk@1760 {
1570                 #clock-cells = <0>;
1571                 compatible = "ti,gate-clock";
1572                 clocks = <&sys_32k_ck>;
1573                 ti,bit-shift = <8>;
1574                 reg = <0x1760>;
1575         };
1576
1577         gpio3_dbclk: gpio3_dbclk@1768 {
1578                 #clock-cells = <0>;
1579                 compatible = "ti,gate-clock";
1580                 clocks = <&sys_32k_ck>;
1581                 ti,bit-shift = <8>;
1582                 reg = <0x1768>;
1583         };
1584
1585         gpio4_dbclk: gpio4_dbclk@1770 {
1586                 #clock-cells = <0>;
1587                 compatible = "ti,gate-clock";
1588                 clocks = <&sys_32k_ck>;
1589                 ti,bit-shift = <8>;
1590                 reg = <0x1770>;
1591         };
1592
1593         gpio5_dbclk: gpio5_dbclk@1778 {
1594                 #clock-cells = <0>;
1595                 compatible = "ti,gate-clock";
1596                 clocks = <&sys_32k_ck>;
1597                 ti,bit-shift = <8>;
1598                 reg = <0x1778>;
1599         };
1600
1601         gpio6_dbclk: gpio6_dbclk@1780 {
1602                 #clock-cells = <0>;
1603                 compatible = "ti,gate-clock";
1604                 clocks = <&sys_32k_ck>;
1605                 ti,bit-shift = <8>;
1606                 reg = <0x1780>;
1607         };
1608
1609         gpio7_dbclk: gpio7_dbclk@1810 {
1610                 #clock-cells = <0>;
1611                 compatible = "ti,gate-clock";
1612                 clocks = <&sys_32k_ck>;
1613                 ti,bit-shift = <8>;
1614                 reg = <0x1810>;
1615         };
1616
1617         gpio8_dbclk: gpio8_dbclk@1818 {
1618                 #clock-cells = <0>;
1619                 compatible = "ti,gate-clock";
1620                 clocks = <&sys_32k_ck>;
1621                 ti,bit-shift = <8>;
1622                 reg = <0x1818>;
1623         };
1624
1625         mmc1_clk32k: mmc1_clk32k@1328 {
1626                 #clock-cells = <0>;
1627                 compatible = "ti,gate-clock";
1628                 clocks = <&sys_32k_ck>;
1629                 ti,bit-shift = <8>;
1630                 reg = <0x1328>;
1631         };
1632
1633         mmc2_clk32k: mmc2_clk32k@1330 {
1634                 #clock-cells = <0>;
1635                 compatible = "ti,gate-clock";
1636                 clocks = <&sys_32k_ck>;
1637                 ti,bit-shift = <8>;
1638                 reg = <0x1330>;
1639         };
1640
1641         mmc3_clk32k: mmc3_clk32k@1820 {
1642                 #clock-cells = <0>;
1643                 compatible = "ti,gate-clock";
1644                 clocks = <&sys_32k_ck>;
1645                 ti,bit-shift = <8>;
1646                 reg = <0x1820>;
1647         };
1648
1649         mmc4_clk32k: mmc4_clk32k@1828 {
1650                 #clock-cells = <0>;
1651                 compatible = "ti,gate-clock";
1652                 clocks = <&sys_32k_ck>;
1653                 ti,bit-shift = <8>;
1654                 reg = <0x1828>;
1655         };
1656
1657         sata_ref_clk: sata_ref_clk@1388 {
1658                 #clock-cells = <0>;
1659                 compatible = "ti,gate-clock";
1660                 clocks = <&sys_clkin1>;
1661                 ti,bit-shift = <8>;
1662                 reg = <0x1388>;
1663         };
1664
1665         usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
1666                 #clock-cells = <0>;
1667                 compatible = "ti,gate-clock";
1668                 clocks = <&l3init_960m_gfclk>;
1669                 ti,bit-shift = <8>;
1670                 reg = <0x13f0>;
1671         };
1672
1673         usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
1674                 #clock-cells = <0>;
1675                 compatible = "ti,gate-clock";
1676                 clocks = <&l3init_960m_gfclk>;
1677                 ti,bit-shift = <8>;
1678                 reg = <0x1340>;
1679         };
1680
1681         usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
1682                 #clock-cells = <0>;
1683                 compatible = "ti,gate-clock";
1684                 clocks = <&sys_32k_ck>;
1685                 ti,bit-shift = <8>;
1686                 reg = <0x0640>;
1687         };
1688
1689         usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
1690                 #clock-cells = <0>;
1691                 compatible = "ti,gate-clock";
1692                 clocks = <&sys_32k_ck>;
1693                 ti,bit-shift = <8>;
1694                 reg = <0x0688>;
1695         };
1696
1697         usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
1698                 #clock-cells = <0>;
1699                 compatible = "ti,gate-clock";
1700                 clocks = <&sys_32k_ck>;
1701                 ti,bit-shift = <8>;
1702                 reg = <0x0698>;
1703         };
1704
1705         atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
1706                 #clock-cells = <0>;
1707                 compatible = "ti,mux-clock";
1708                 clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
1709                 ti,bit-shift = <24>;
1710                 reg = <0x0c00>;
1711         };
1712
1713         atl_gfclk_mux: atl_gfclk_mux@c00 {
1714                 #clock-cells = <0>;
1715                 compatible = "ti,mux-clock";
1716                 clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
1717                 ti,bit-shift = <26>;
1718                 reg = <0x0c00>;
1719         };
1720
1721         gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@13d0 {
1722                 #clock-cells = <0>;
1723                 compatible = "ti,divider-clock";
1724                 clocks = <&dpll_gmac_m2_ck>;
1725                 ti,bit-shift = <24>;
1726                 reg = <0x13d0>;
1727                 ti,dividers = <2>;
1728         };
1729
1730         gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
1731                 #clock-cells = <0>;
1732                 compatible = "ti,mux-clock";
1733                 clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
1734                 ti,bit-shift = <25>;
1735                 reg = <0x13d0>;
1736         };
1737
1738         gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
1739                 #clock-cells = <0>;
1740                 compatible = "ti,mux-clock";
1741                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1742                 ti,bit-shift = <24>;
1743                 reg = <0x1220>;
1744         };
1745
1746         gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
1747                 #clock-cells = <0>;
1748                 compatible = "ti,mux-clock";
1749                 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1750                 ti,bit-shift = <26>;
1751                 reg = <0x1220>;
1752         };
1753
1754         l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
1755                 #clock-cells = <0>;
1756                 compatible = "ti,divider-clock";
1757                 clocks = <&wkupaon_iclk_mux>;
1758                 ti,bit-shift = <24>;
1759                 reg = <0x0e50>;
1760                 ti,dividers = <8>, <16>, <32>;
1761         };
1762
1763         mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
1764                 #clock-cells = <0>;
1765                 compatible = "ti,mux-clock";
1766                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1767                 ti,bit-shift = <28>;
1768                 reg = <0x1860>;
1769         };
1770
1771         mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
1772                 #clock-cells = <0>;
1773                 compatible = "ti,mux-clock";
1774                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1775                 ti,bit-shift = <24>;
1776                 reg = <0x1860>;
1777         };
1778
1779         mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
1780                 #clock-cells = <0>;
1781                 compatible = "ti,mux-clock";
1782                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1783                 ti,bit-shift = <22>;
1784                 reg = <0x1860>;
1785         };
1786
1787         mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
1788                 #clock-cells = <0>;
1789                 compatible = "ti,mux-clock";
1790                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1791                 ti,bit-shift = <24>;
1792                 reg = <0x1868>;
1793         };
1794
1795         mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
1796                 #clock-cells = <0>;
1797                 compatible = "ti,mux-clock";
1798                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1799                 ti,bit-shift = <22>;
1800                 reg = <0x1868>;
1801         };
1802
1803         mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
1804                 #clock-cells = <0>;
1805                 compatible = "ti,mux-clock";
1806                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1807                 ti,bit-shift = <24>;
1808                 reg = <0x1898>;
1809         };
1810
1811         mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
1812                 #clock-cells = <0>;
1813                 compatible = "ti,mux-clock";
1814                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1815                 ti,bit-shift = <22>;
1816                 reg = <0x1898>;
1817         };
1818
1819         mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
1820                 #clock-cells = <0>;
1821                 compatible = "ti,mux-clock";
1822                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1823                 ti,bit-shift = <24>;
1824                 reg = <0x1878>;
1825         };
1826
1827         mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
1828                 #clock-cells = <0>;
1829                 compatible = "ti,mux-clock";
1830                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1831                 ti,bit-shift = <22>;
1832                 reg = <0x1878>;
1833         };
1834
1835         mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
1836                 #clock-cells = <0>;
1837                 compatible = "ti,mux-clock";
1838                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1839                 ti,bit-shift = <24>;
1840                 reg = <0x1904>;
1841         };
1842
1843         mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
1844                 #clock-cells = <0>;
1845                 compatible = "ti,mux-clock";
1846                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1847                 ti,bit-shift = <22>;
1848                 reg = <0x1904>;
1849         };
1850
1851         mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
1852                 #clock-cells = <0>;
1853                 compatible = "ti,mux-clock";
1854                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1855                 ti,bit-shift = <24>;
1856                 reg = <0x1908>;
1857         };
1858
1859         mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
1860                 #clock-cells = <0>;
1861                 compatible = "ti,mux-clock";
1862                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1863                 ti,bit-shift = <22>;
1864                 reg = <0x1908>;
1865         };
1866
1867         mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
1868                 #clock-cells = <0>;
1869                 compatible = "ti,mux-clock";
1870                 clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
1871                 ti,bit-shift = <22>;
1872                 reg = <0x1890>;
1873         };
1874
1875         mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
1876                 #clock-cells = <0>;
1877                 compatible = "ti,mux-clock";
1878                 clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
1879                 ti,bit-shift = <24>;
1880                 reg = <0x1890>;
1881         };
1882
1883         mmc1_fclk_mux: mmc1_fclk_mux@1328 {
1884                 #clock-cells = <0>;
1885                 compatible = "ti,mux-clock";
1886                 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1887                 ti,bit-shift = <24>;
1888                 reg = <0x1328>;
1889         };
1890
1891         mmc1_fclk_div: mmc1_fclk_div@1328 {
1892                 #clock-cells = <0>;
1893                 compatible = "ti,divider-clock";
1894                 clocks = <&mmc1_fclk_mux>;
1895                 ti,bit-shift = <25>;
1896                 ti,max-div = <4>;
1897                 reg = <0x1328>;
1898                 ti,index-power-of-two;
1899         };
1900
1901         mmc2_fclk_mux: mmc2_fclk_mux@1330 {
1902                 #clock-cells = <0>;
1903                 compatible = "ti,mux-clock";
1904                 clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
1905                 ti,bit-shift = <24>;
1906                 reg = <0x1330>;
1907         };
1908
1909         mmc2_fclk_div: mmc2_fclk_div@1330 {
1910                 #clock-cells = <0>;
1911                 compatible = "ti,divider-clock";
1912                 clocks = <&mmc2_fclk_mux>;
1913                 ti,bit-shift = <25>;
1914                 ti,max-div = <4>;
1915                 reg = <0x1330>;
1916                 ti,index-power-of-two;
1917         };
1918
1919         mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
1920                 #clock-cells = <0>;
1921                 compatible = "ti,mux-clock";
1922                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1923                 ti,bit-shift = <24>;
1924                 reg = <0x1820>;
1925         };
1926
1927         mmc3_gfclk_div: mmc3_gfclk_div@1820 {
1928                 #clock-cells = <0>;
1929                 compatible = "ti,divider-clock";
1930                 clocks = <&mmc3_gfclk_mux>;
1931                 ti,bit-shift = <25>;
1932                 ti,max-div = <4>;
1933                 reg = <0x1820>;
1934                 ti,index-power-of-two;
1935         };
1936
1937         mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
1938                 #clock-cells = <0>;
1939                 compatible = "ti,mux-clock";
1940                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
1941                 ti,bit-shift = <24>;
1942                 reg = <0x1828>;
1943         };
1944
1945         mmc4_gfclk_div: mmc4_gfclk_div@1828 {
1946                 #clock-cells = <0>;
1947                 compatible = "ti,divider-clock";
1948                 clocks = <&mmc4_gfclk_mux>;
1949                 ti,bit-shift = <25>;
1950                 ti,max-div = <4>;
1951                 reg = <0x1828>;
1952                 ti,index-power-of-two;
1953         };
1954
1955         qspi_gfclk_mux: qspi_gfclk_mux@1838 {
1956                 #clock-cells = <0>;
1957                 compatible = "ti,mux-clock";
1958                 clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
1959                 ti,bit-shift = <24>;
1960                 reg = <0x1838>;
1961         };
1962
1963         qspi_gfclk_div: qspi_gfclk_div@1838 {
1964                 #clock-cells = <0>;
1965                 compatible = "ti,divider-clock";
1966                 clocks = <&qspi_gfclk_mux>;
1967                 ti,bit-shift = <25>;
1968                 ti,max-div = <4>;
1969                 reg = <0x1838>;
1970                 ti,index-power-of-two;
1971         };
1972
1973         timer10_gfclk_mux: timer10_gfclk_mux@1728 {
1974                 #clock-cells = <0>;
1975                 compatible = "ti,mux-clock";
1976                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1977                 ti,bit-shift = <24>;
1978                 reg = <0x1728>;
1979         };
1980
1981         timer11_gfclk_mux: timer11_gfclk_mux@1730 {
1982                 #clock-cells = <0>;
1983                 compatible = "ti,mux-clock";
1984                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1985                 ti,bit-shift = <24>;
1986                 reg = <0x1730>;
1987         };
1988
1989         timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
1990                 #clock-cells = <0>;
1991                 compatible = "ti,mux-clock";
1992                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
1993                 ti,bit-shift = <24>;
1994                 reg = <0x17c8>;
1995         };
1996
1997         timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
1998                 #clock-cells = <0>;
1999                 compatible = "ti,mux-clock";
2000                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2001                 ti,bit-shift = <24>;
2002                 reg = <0x17d0>;
2003         };
2004
2005         timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
2006                 #clock-cells = <0>;
2007                 compatible = "ti,mux-clock";
2008                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2009                 ti,bit-shift = <24>;
2010                 reg = <0x17d8>;
2011         };
2012
2013         timer16_gfclk_mux: timer16_gfclk_mux@1830 {
2014                 #clock-cells = <0>;
2015                 compatible = "ti,mux-clock";
2016                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2017                 ti,bit-shift = <24>;
2018                 reg = <0x1830>;
2019         };
2020
2021         timer2_gfclk_mux: timer2_gfclk_mux@1738 {
2022                 #clock-cells = <0>;
2023                 compatible = "ti,mux-clock";
2024                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2025                 ti,bit-shift = <24>;
2026                 reg = <0x1738>;
2027         };
2028
2029         timer3_gfclk_mux: timer3_gfclk_mux@1740 {
2030                 #clock-cells = <0>;
2031                 compatible = "ti,mux-clock";
2032                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2033                 ti,bit-shift = <24>;
2034                 reg = <0x1740>;
2035         };
2036
2037         timer4_gfclk_mux: timer4_gfclk_mux@1748 {
2038                 #clock-cells = <0>;
2039                 compatible = "ti,mux-clock";
2040                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2041                 ti,bit-shift = <24>;
2042                 reg = <0x1748>;
2043         };
2044
2045         timer9_gfclk_mux: timer9_gfclk_mux@1750 {
2046                 #clock-cells = <0>;
2047                 compatible = "ti,mux-clock";
2048                 clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
2049                 ti,bit-shift = <24>;
2050                 reg = <0x1750>;
2051         };
2052
2053         uart1_gfclk_mux: uart1_gfclk_mux@1840 {
2054                 #clock-cells = <0>;
2055                 compatible = "ti,mux-clock";
2056                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2057                 ti,bit-shift = <24>;
2058                 reg = <0x1840>;
2059         };
2060
2061         uart2_gfclk_mux: uart2_gfclk_mux@1848 {
2062                 #clock-cells = <0>;
2063                 compatible = "ti,mux-clock";
2064                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2065                 ti,bit-shift = <24>;
2066                 reg = <0x1848>;
2067         };
2068
2069         uart3_gfclk_mux: uart3_gfclk_mux@1850 {
2070                 #clock-cells = <0>;
2071                 compatible = "ti,mux-clock";
2072                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2073                 ti,bit-shift = <24>;
2074                 reg = <0x1850>;
2075         };
2076
2077         uart4_gfclk_mux: uart4_gfclk_mux@1858 {
2078                 #clock-cells = <0>;
2079                 compatible = "ti,mux-clock";
2080                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2081                 ti,bit-shift = <24>;
2082                 reg = <0x1858>;
2083         };
2084
2085         uart5_gfclk_mux: uart5_gfclk_mux@1870 {
2086                 #clock-cells = <0>;
2087                 compatible = "ti,mux-clock";
2088                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2089                 ti,bit-shift = <24>;
2090                 reg = <0x1870>;
2091         };
2092
2093         uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
2094                 #clock-cells = <0>;
2095                 compatible = "ti,mux-clock";
2096                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2097                 ti,bit-shift = <24>;
2098                 reg = <0x18d0>;
2099         };
2100
2101         uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
2102                 #clock-cells = <0>;
2103                 compatible = "ti,mux-clock";
2104                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2105                 ti,bit-shift = <24>;
2106                 reg = <0x18e0>;
2107         };
2108
2109         uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
2110                 #clock-cells = <0>;
2111                 compatible = "ti,mux-clock";
2112                 clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
2113                 ti,bit-shift = <24>;
2114                 reg = <0x18e8>;
2115         };
2116
2117         vip1_gclk_mux: vip1_gclk_mux@1020 {
2118                 #clock-cells = <0>;
2119                 compatible = "ti,mux-clock";
2120                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2121                 ti,bit-shift = <24>;
2122                 reg = <0x1020>;
2123         };
2124
2125         vip2_gclk_mux: vip2_gclk_mux@1028 {
2126                 #clock-cells = <0>;
2127                 compatible = "ti,mux-clock";
2128                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2129                 ti,bit-shift = <24>;
2130                 reg = <0x1028>;
2131         };
2132
2133         vip3_gclk_mux: vip3_gclk_mux@1030 {
2134                 #clock-cells = <0>;
2135                 compatible = "ti,mux-clock";
2136                 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
2137                 ti,bit-shift = <24>;
2138                 reg = <0x1030>;
2139         };
2140 };
2141
2142 &cm_core_clockdomains {
2143         coreaon_clkdm: coreaon_clkdm {
2144                 compatible = "ti,clockdomain";
2145                 clocks = <&dpll_usb_ck>;
2146         };
2147 };
2148
2149 &scm_conf_clocks {
2150         dss_deshdcp_clk: dss_deshdcp_clk@558 {
2151                 #clock-cells = <0>;
2152                 compatible = "ti,gate-clock";
2153                 clocks = <&l3_iclk_div>;
2154                 ti,bit-shift = <0>;
2155                 reg = <0x558>;
2156         };
2157
2158        ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
2159                 #clock-cells = <0>;
2160                 compatible = "ti,gate-clock";
2161                 clocks = <&l4_root_clk_div>;
2162                 ti,bit-shift = <20>;
2163                 reg = <0x0558>;
2164         };
2165
2166         ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
2167                 #clock-cells = <0>;
2168                 compatible = "ti,gate-clock";
2169                 clocks = <&l4_root_clk_div>;
2170                 ti,bit-shift = <21>;
2171                 reg = <0x0558>;
2172         };
2173
2174         ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
2175                 #clock-cells = <0>;
2176                 compatible = "ti,gate-clock";
2177                 clocks = <&l4_root_clk_div>;
2178                 ti,bit-shift = <22>;
2179                 reg = <0x0558>;
2180         };
2181
2182         sys_32k_ck: sys_32k_ck {
2183                 #clock-cells = <0>;
2184                 compatible = "ti,mux-clock";
2185                 clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
2186                 ti,bit-shift = <8>;
2187                 reg = <0x6c4>;
2188         };
2189 };