arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2018 Texas Instruments
   3 // MMC IOdelay values for TI's DRA76x and AM576x SoCs.
   4 // Author: Sekhar Nori <nsekhar@ti.com>
   5
   6 /*
   7  * Rules for modifying this file:
   8  * a) Update of this file should typically correspond to a datamanual revision.
   9  *    Datamanual revision that was used should be updated in comment below.
  10  *    If there is no update to datamanual, do not update the values. If you
  11  *    need to use values different from that recommended by the datamanual
  12  *    for your design, then you should consider adding values to the device-
  13  *    -tree file for your board directly.
  14  * b) We keep the mode names as close to the datamanual as possible. So
  15  *    if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
  16  *    we follow that in code too.
  17  * c) If the values change between multiple revisions of silicon, we add
  18  *    a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
  19  *    'rev20' for PG 2.0 and so on.
  20  * d) The node name and node label should be the exact same string. This is
  21  *    to curb naming creativity and achieve consistency.
  22  *
  23  * Datamanual Revisions:
  24  *
  25  * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017
  26  *
  27  */
  28
  29 &dra7_pmx_core {
  30         mmc1_pins_default: mmc1_pins_default {
  31                 pinctrl-single,pins = <
  32                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  33                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  34                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  35                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  36                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  37                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  38                 >;
  39         };
  40
  41         mmc1_pins_hs: mmc1_pins_hs {
  42                 pinctrl-single,pins = <
  43                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
  44                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
  45                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
  46                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
  47                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
  48                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
  49                 >;
  50         };
  51
  52         mmc1_pins_sdr50: mmc1_pins_sdr50 {
  53                 pinctrl-single,pins = <
  54                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_clk.clk */
  55                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_cmd.cmd */
  56                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_dat0.dat0 */
  57                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_dat1.dat1 */
  58                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_dat2.dat2 */
  59                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_dat3.dat3 */
  60                 >;
  61         };
  62
  63         mmc1_pins_ddr50: mmc1_pins_ddr50 {
  64                 pinctrl-single,pins = <
  65                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_clk.clk */
  66                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_cmd.cmd */
  67                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat0.dat0 */
  68                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat1.dat1 */
  69                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat2.dat2 */
  70                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat3.dat3 */
  71                 >;
  72         };
  73
  74         mmc2_pins_default: mmc2_pins_default {
  75                 pinctrl-single,pins = <
  76                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
  77                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
  78                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
  79                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
  80                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
  81                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
  82                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
  83                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
  84                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
  85                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
  86                 >;
  87         };
  88
  89         mmc2_pins_hs200: mmc2_pins_hs200 {
  90                 pinctrl-single,pins = <
  91                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
  92                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
  93                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
  94                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
  95                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
  96                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
  97                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
  98                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
  99                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 100                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 101                 >;
 102         };
 103
 104         mmc3_pins_default: mmc3_pins_default {
 105                 pinctrl-single,pins = <
 106                         DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
 107                         DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
 108                         DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
 109                         DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
 110                         DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
 111                         DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
 112                 >;
 113         };
 114
 115         mmc4_pins_hs: mmc4_pins_hs {
 116                 pinctrl-single,pins = <
 117                         DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
 118                         DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
 119                         DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
 120                         DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
 121                         DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
 122                         DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
 123                 >;
 124         };
 125 };
 126
 127 &dra7_iodelay_core {
 128
 129         /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
 130         mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf {
 131                 pinctrl-pin-array = <
 132                         0x618 A_DELAY_PS(489) G_DELAY_PS(0)     /* CFG_MMC1_CLK_IN */
 133                         0x624 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_IN */
 134                         0x630 A_DELAY_PS(374) G_DELAY_PS(0)     /* CFG_MMC1_DAT0_IN */
 135                         0x63c A_DELAY_PS(31) G_DELAY_PS(0)      /* CFG_MMC1_DAT1_IN */
 136                         0x648 A_DELAY_PS(56) G_DELAY_PS(0)      /* CFG_MMC1_DAT2_IN */
 137                         0x654 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_IN */
 138                         0x620 A_DELAY_PS(1355) G_DELAY_PS(0)    /* CFG_MMC1_CLK_OUT */
 139                         0x628 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OEN */
 140                         0x62c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OUT */
 141                         0x634 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OEN */
 142                         0x638 A_DELAY_PS(0) G_DELAY_PS(4)       /* CFG_MMC1_DAT0_OUT */
 143                         0x640 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OEN */
 144                         0x644 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OUT */
 145                         0x64c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OEN */
 146                         0x650 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OUT */
 147                         0x658 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OEN */
 148                         0x65c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OUT */
 149                 >;
 150         };
 151
 152         /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
 153         mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
 154                 pinctrl-pin-array = <
 155                         0x620 A_DELAY_PS(892) G_DELAY_PS(0)     /* CFG_MMC1_CLK_OUT */
 156                         0x628 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OEN */
 157                         0x62c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OUT */
 158                         0x634 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OEN */
 159                         0x638 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OUT */
 160                         0x640 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OEN */
 161                         0x644 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OUT */
 162                         0x64c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OEN */
 163                         0x650 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OUT */
 164                         0x658 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OEN */
 165                         0x65c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OUT */
 166                 >;
 167         };
 168
 169         /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
 170         mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf {
 171                 pinctrl-pin-array = <
 172                         0x190 A_DELAY_PS(384) G_DELAY_PS(0)       /* CFG_GPMC_A19_OEN */
 173                         0x194 A_DELAY_PS(0) G_DELAY_PS(174)       /* CFG_GPMC_A19_OUT */
 174                         0x1a8 A_DELAY_PS(410) G_DELAY_PS(0)       /* CFG_GPMC_A20_OEN */
 175                         0x1ac A_DELAY_PS(85) G_DELAY_PS(0)        /* CFG_GPMC_A20_OUT */
 176                         0x1b4 A_DELAY_PS(468) G_DELAY_PS(0)       /* CFG_GPMC_A21_OEN */
 177                         0x1b8 A_DELAY_PS(139) G_DELAY_PS(0)       /* CFG_GPMC_A21_OUT */
 178                         0x1c0 A_DELAY_PS(676) G_DELAY_PS(0)       /* CFG_GPMC_A22_OEN */
 179                         0x1c4 A_DELAY_PS(69) G_DELAY_PS(0)        /* CFG_GPMC_A22_OUT */
 180                         0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154)    /* CFG_GPMC_A23_OUT */
 181                         0x1d8 A_DELAY_PS(640) G_DELAY_PS(0)       /* CFG_GPMC_A24_OEN */
 182                         0x1dc A_DELAY_PS(0) G_DELAY_PS(0)         /* CFG_GPMC_A24_OUT */
 183                         0x1e4 A_DELAY_PS(356) G_DELAY_PS(0)       /* CFG_GPMC_A25_OEN */
 184                         0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)         /* CFG_GPMC_A25_OUT */
 185                         0x1f0 A_DELAY_PS(579) G_DELAY_PS(0)       /* CFG_GPMC_A26_OEN */
 186                         0x1f4 A_DELAY_PS(0) G_DELAY_PS(0)         /* CFG_GPMC_A26_OUT */
 187                         0x1fc A_DELAY_PS(435) G_DELAY_PS(0)       /* CFG_GPMC_A27_OEN */
 188                         0x200 A_DELAY_PS(36) G_DELAY_PS(0)        /* CFG_GPMC_A27_OUT */
 189                         0x364 A_DELAY_PS(759) G_DELAY_PS(0)       /* CFG_GPMC_CS1_OEN */
 190                         0x368 A_DELAY_PS(72) G_DELAY_PS(0)        /* CFG_GPMC_CS1_OUT */
 191               >;
 192         };
 193
 194         /* Corresponds to MMC3_MANUAL1 in datamanual */
 195         mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf {
 196                 pinctrl-pin-array = <
 197                         0x678 A_DELAY_PS(0) G_DELAY_PS(386)     /* CFG_MMC3_CLK_IN */
 198                         0x680 A_DELAY_PS(605) G_DELAY_PS(0)     /* CFG_MMC3_CLK_OUT */
 199                         0x684 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_IN */
 200                         0x688 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_OEN */
 201                         0x68c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_OUT */
 202                         0x690 A_DELAY_PS(171) G_DELAY_PS(0)     /* CFG_MMC3_DAT0_IN */
 203                         0x694 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT0_OEN */
 204                         0x698 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT0_OUT */
 205                         0x69c A_DELAY_PS(221) G_DELAY_PS(0)     /* CFG_MMC3_DAT1_IN */
 206                         0x6a0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT1_OEN */
 207                         0x6a4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT1_OUT */
 208                         0x6a8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_IN */
 209                         0x6ac A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_OEN */
 210                         0x6b0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_OUT */
 211                         0x6b4 A_DELAY_PS(474) G_DELAY_PS(0)     /* CFG_MMC3_DAT3_IN */
 212                         0x6b8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT3_OEN */
 213                         0x6bc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT3_OUT */
 214                 >;
 215         };
 216
 217         /* Corresponds to MMC3_MANUAL2 in datamanual */
 218         mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf {
 219                 pinctrl-pin-array = <
 220                         0x678 A_DELAY_PS(852) G_DELAY_PS(0)     /* CFG_MMC3_CLK_IN */
 221                         0x680 A_DELAY_PS(94) G_DELAY_PS(0)      /* CFG_MMC3_CLK_OUT */
 222                         0x684 A_DELAY_PS(122) G_DELAY_PS(0)     /* CFG_MMC3_CMD_IN */
 223                         0x688 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_OEN */
 224                         0x68c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_OUT */
 225                         0x690 A_DELAY_PS(91) G_DELAY_PS(0)      /* CFG_MMC3_DAT0_IN */
 226                         0x694 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT0_OEN */
 227                         0x698 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT0_OUT */
 228                         0x69c A_DELAY_PS(57) G_DELAY_PS(0)      /* CFG_MMC3_DAT1_IN */
 229                         0x6a0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT1_OEN */
 230                         0x6a4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT1_OUT */
 231                         0x6a8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_IN */
 232                         0x6ac A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_OEN */
 233                         0x6b0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_OUT */
 234                         0x6b4 A_DELAY_PS(375) G_DELAY_PS(0)     /* CFG_MMC3_DAT3_IN */
 235                         0x6b8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT3_OEN */
 236                         0x6bc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT3_OUT */
 237                 >;
 238         };
 239
 240         /* Corresponds to MMC4_MANUAL1 in datamanual */
 241         mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf {
 242                 pinctrl-pin-array = <
 243                         0x840 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_CTSN_IN */
 244                         0x848 A_DELAY_PS(1147) G_DELAY_PS(0)    /* CFG_UART1_CTSN_OUT */
 245                         0x84c A_DELAY_PS(1834) G_DELAY_PS(0)    /* CFG_UART1_RTSN_IN */
 246                         0x850 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OEN */
 247                         0x854 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OUT */
 248                         0x870 A_DELAY_PS(2165) G_DELAY_PS(0)    /* CFG_UART2_CTSN_IN */
 249                         0x874 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OEN */
 250                         0x878 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OUT */
 251                         0x87c A_DELAY_PS(1929) G_DELAY_PS(64)   /* CFG_UART2_RTSN_IN */
 252                         0x880 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OEN */
 253                         0x884 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OUT */
 254                         0x888 A_DELAY_PS(1935) G_DELAY_PS(128)  /* CFG_UART2_RXD_IN */
 255                         0x88c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OEN */
 256                         0x890 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OUT */
 257                         0x894 A_DELAY_PS(2172) G_DELAY_PS(44)   /* CFG_UART2_TXD_IN */
 258                         0x898 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OEN */
 259                         0x89c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OUT */
 260                 >;
 261         };
 262
 263         /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
 264         mmc4_iodelay_default_conf: mmc4_iodelay_default_conf {
 265                 pinctrl-pin-array = <
 266                         0x840 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_CTSN_IN */
 267                         0x848 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_CTSN_OUT */
 268                         0x84c A_DELAY_PS(307) G_DELAY_PS(0)     /* CFG_UART1_RTSN_IN */
 269                         0x850 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OEN */
 270                         0x854 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OUT */
 271                         0x870 A_DELAY_PS(785) G_DELAY_PS(0)     /* CFG_UART2_CTSN_IN */
 272                         0x874 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OEN */
 273                         0x878 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OUT */
 274                         0x87c A_DELAY_PS(613) G_DELAY_PS(0)     /* CFG_UART2_RTSN_IN */
 275                         0x880 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OEN */
 276                         0x884 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OUT */
 277                         0x888 A_DELAY_PS(683) G_DELAY_PS(0)     /* CFG_UART2_RXD_IN */
 278                         0x88c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OEN */
 279                         0x890 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OUT */
 280                         0x894 A_DELAY_PS(835) G_DELAY_PS(0)     /* CFG_UART2_TXD_IN */
 281                         0x898 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OEN */
 282                         0x89c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OUT */
 283                 >;
 284         };
 285 };