arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi

   1 /*
   2  * MMC IOdelay values for TI's DRA74x, DRA75x and AM572x SoCs.
   3  *
   4  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /*
  17  * Rules for modifying this file:
  18  * a) Update of this file should typically correspond to a datamanual revision.
  19  *    Datamanual revision that was used should be updated in comment below.
  20  *    If there is no update to datamanual, do not update the values. If you
  21  *    need to use values different from that recommended by the datamanual
  22  *    for your design, then you should consider adding values to the device-
  23  *    -tree file for your board directly.
  24  * b) We keep the mode names as close to the datamanual as possible. So
  25  *    if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
  26  *    we follow that in code too.
  27  * c) If the values change between multiple revisions of silicon, we add
  28  *    a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
  29  *    'rev20' for PG 2.0 and so on.
  30  * d) The node name and node label should be the exact same string. This is
  31  *    to curb naming creativity and achieve consistency.
  32  *
  33  * Datamanual Revisions:
  34  *
  35  * AM572x Silicon Revision 2.0: SPRS953F, Revised May 2019
  36  * AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016
  37  *
  38  */
  39
  40 &dra7_pmx_core {
  41         mmc1_pins_default: mmc1_pins_default {
  42                 pinctrl-single,pins = <
  43                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  44                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  45                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  46                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  47                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  48                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  49                 >;
  50         };
  51
  52         mmc1_pins_sdr12: mmc1_pins_sdr12 {
  53                 pinctrl-single,pins = <
  54                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  55                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  56                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  57                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  58                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  59                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  60                 >;
  61         };
  62
  63         mmc1_pins_hs: mmc1_pins_hs {
  64                 pinctrl-single,pins = <
  65                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
  66                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
  67                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
  68                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
  69                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
  70                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
  71                 >;
  72         };
  73
  74         mmc1_pins_sdr25: mmc1_pins_sdr25 {
  75                 pinctrl-single,pins = <
  76                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)    /* mmc1_clk.clk */
  77                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)    /* mmc1_cmd.cmd */
  78                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)    /* mmc1_dat0.dat0 */
  79                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)    /* mmc1_dat1.dat1 */
  80                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)    /* mmc1_dat2.dat2 */
  81                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0)    /* mmc1_dat3.dat3 */
  82                 >;
  83         };
  84
  85         mmc1_pins_sdr50: mmc1_pins_sdr50 {
  86                 pinctrl-single,pins = <
  87                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_clk.clk */
  88                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_cmd.cmd */
  89                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_dat0.dat0 */
  90                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_dat1.dat1 */
  91                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_dat2.dat2 */
  92                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0)    /* mmc1_dat3.dat3 */
  93                 >;
  94         };
  95
  96         mmc1_pins_ddr50: mmc1_pins_ddr50 {
  97                 pinctrl-single,pins = <
  98                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_clk.clk */
  99                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_cmd.cmd */
 100                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat0.dat0 */
 101                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat1.dat1 */
 102                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat2.dat2 */
 103                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat3.dat3 */
 104                 >;
 105         };
 106
 107         mmc1_pins_sdr104: mmc1_pins_sdr104 {
 108                 pinctrl-single,pins = <
 109                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_clk.clk */
 110                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_cmd.cmd */
 111                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat0.dat0 */
 112                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat1.dat1 */
 113                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat2.dat2 */
 114                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat3.dat3 */
 115                 >;
 116         };
 117
 118         mmc2_pins_default: mmc2_pins_default {
 119                 pinctrl-single,pins = <
 120                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 121                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 122                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 123                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 124                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 125                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 126                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 127                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 128                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 129                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 130                 >;
 131         };
 132
 133         mmc2_pins_hs: mmc2_pins_hs {
 134                 pinctrl-single,pins = <
 135                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 136                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 137                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 138                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 139                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 140                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 141                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 142                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 143                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 144                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 145                 >;
 146         };
 147
 148         mmc2_pins_ddr_3_3v_rev11: mmc2_pins_ddr_3_3v_rev11 {
 149                 pinctrl-single,pins = <
 150                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 151                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 152                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 153                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 154                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 155                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 156                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 157                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 158                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 159                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 160                 >;
 161         };
 162
 163         mmc2_pins_ddr_1_8v_rev11: mmc2_pins_ddr_1_8v_rev11 {
 164                 pinctrl-single,pins = <
 165                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 166                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 167                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 168                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 169                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 170                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 171                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 172                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 173                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 174                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 175                 >;
 176         };
 177
 178         mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {
 179                 pinctrl-single,pins = <
 180                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 181                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 182                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 183                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 184                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 185                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 186                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 187                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 188                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 189                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 190                 >;
 191         };
 192
 193         mmc2_pins_hs200: mmc2_pins_hs200 {
 194                 pinctrl-single,pins = <
 195                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 196                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 197                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 198                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 199                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 200                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 201                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 202                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 203                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 204                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 205                 >;
 206         };
 207
 208         mmc4_pins_default: mmc4_pins_default {
 209                 pinctrl-single,pins = <
 210                         DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
 211                         DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
 212                         DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
 213                         DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
 214                         DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
 215                         DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
 216                 >;
 217         };
 218
 219         mmc4_pins_hs: mmc4_pins_hs {
 220                 pinctrl-single,pins = <
 221                         DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
 222                         DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
 223                         DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
 224                         DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
 225                         DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
 226                         DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
 227                 >;
 228         };
 229
 230         mmc3_pins_default: mmc3_pins_default {
 231                 pinctrl-single,pins = <
 232                         DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
 233                         DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
 234                         DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
 235                         DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
 236                         DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
 237                         DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
 238                 >;
 239         };
 240
 241         mmc3_pins_hs: mmc3_pins_hs {
 242                 pinctrl-single,pins = <
 243                         DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
 244                         DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
 245                         DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
 246                         DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
 247                         DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
 248                         DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
 249                 >;
 250         };
 251
 252         mmc3_pins_sdr12: mmc3_pins_sdr12 {
 253                 pinctrl-single,pins = <
 254                         DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
 255                         DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
 256                         DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
 257                         DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
 258                         DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
 259                         DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
 260                 >;
 261         };
 262
 263         mmc3_pins_sdr25: mmc3_pins_sdr25 {
 264                 pinctrl-single,pins = <
 265                         DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
 266                         DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
 267                         DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
 268                         DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
 269                         DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
 270                         DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
 271                 >;
 272         };
 273
 274         mmc3_pins_sdr50: mmc3_pins_sdr50 {
 275                 pinctrl-single,pins = <
 276                         DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
 277                         DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
 278                         DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
 279                         DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
 280                         DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
 281                         DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
 282                 >;
 283         };
 284
 285         mmc4_pins_sdr12: mmc4_pins_sdr12 {
 286                 pinctrl-single,pins = <
 287                         DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
 288                         DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
 289                         DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
 290                         DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
 291                         DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
 292                         DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
 293                 >;
 294         };
 295
 296         mmc4_pins_sdr25: mmc4_pins_sdr25 {
 297                 pinctrl-single,pins = <
 298                         DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
 299                         DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
 300                         DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
 301                         DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
 302                         DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
 303                         DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
 304                 >;
 305         };
 306 };
 307
 308 &dra7_iodelay_core {
 309
 310         /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
 311         mmc1_iodelay_ddr_rev11_conf: mmc1_iodelay_ddr_rev11_conf {
 312                 pinctrl-pin-array = <
 313                         0x618 A_DELAY_PS(572) G_DELAY_PS(540)   /* CFG_MMC1_CLK_IN */
 314                         0x620 A_DELAY_PS(1525) G_DELAY_PS(0)    /* CFG_MMC1_CLK_OUT */
 315                         0x624 A_DELAY_PS(0) G_DELAY_PS(600)     /* CFG_MMC1_CMD_IN */
 316                         0x628 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OEN */
 317                         0x62c A_DELAY_PS(55) G_DELAY_PS(0)      /* CFG_MMC1_CMD_OUT */
 318                         0x630 A_DELAY_PS(403) G_DELAY_PS(120)   /* CFG_MMC1_DAT0_IN */
 319                         0x634 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OEN */
 320                         0x638 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OUT */
 321                         0x63c A_DELAY_PS(23) G_DELAY_PS(60)     /* CFG_MMC1_DAT1_IN */
 322                         0x640 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OEN */
 323                         0x644 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OUT */
 324                         0x648 A_DELAY_PS(25) G_DELAY_PS(60)     /* CFG_MMC1_DAT2_IN */
 325                         0x64c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OEN */
 326                         0x650 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OUT */
 327                         0x654 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_IN */
 328                         0x658 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OEN */
 329                         0x65c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OUT */
 330                 >;
 331         };
 332
 333         /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
 334         mmc1_iodelay_ddr_rev20_conf: mmc1_iodelay_ddr50_rev20_conf {
 335                 pinctrl-pin-array = <
 336                         0x618 A_DELAY_PS(1076) G_DELAY_PS(330)  /* CFG_MMC1_CLK_IN */
 337                         0x620 A_DELAY_PS(1271) G_DELAY_PS(0)    /* CFG_MMC1_CLK_OUT */
 338                         0x624 A_DELAY_PS(722) G_DELAY_PS(0)     /* CFG_MMC1_CMD_IN */
 339                         0x628 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OEN */
 340                         0x62C A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OUT */
 341                         0x630 A_DELAY_PS(751) G_DELAY_PS(0)     /* CFG_MMC1_DAT0_IN */
 342                         0x634 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OEN */
 343                         0x638 A_DELAY_PS(20) G_DELAY_PS(0)      /* CFG_MMC1_DAT0_OUT */
 344                         0x63C A_DELAY_PS(256) G_DELAY_PS(0)     /* CFG_MMC1_DAT1_IN */
 345                         0x640 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OEN */
 346                         0x644 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OUT */
 347                         0x648 A_DELAY_PS(263) G_DELAY_PS(0)     /* CFG_MMC1_DAT2_IN */
 348                         0x64C A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OEN */
 349                         0x650 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OUT */
 350                         0x654 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_IN */
 351                         0x658 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OEN */
 352                         0x65C A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OUT */
 353                 >;
 354         };
 355
 356         /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
 357         mmc1_iodelay_sdr104_rev11_conf: mmc1_iodelay_sdr104_rev11_conf {
 358                 pinctrl-pin-array = <
 359                         0x620 A_DELAY_PS(1063) G_DELAY_PS(17)   /* CFG_MMC1_CLK_OUT */
 360                         0x628 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OEN */
 361                         0x62c A_DELAY_PS(23) G_DELAY_PS(0)      /* CFG_MMC1_CMD_OUT */
 362                         0x634 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OEN */
 363                         0x638 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OUT */
 364                         0x640 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OEN */
 365                         0x644 A_DELAY_PS(2) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OUT */
 366                         0x64c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OEN */
 367                         0x650 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OUT */
 368                         0x658 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OEN */
 369                         0x65c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OUT */
 370                 >;
 371         };
 372
 373         /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
 374         mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
 375                 pinctrl-pin-array = <
 376                         0x620 A_DELAY_PS(600) G_DELAY_PS(400)   /* CFG_MMC1_CLK_OUT */
 377                         0x628 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OEN */
 378                         0x62c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OUT */
 379                         0x634 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OEN */
 380                         0x638 A_DELAY_PS(30) G_DELAY_PS(0)      /* CFG_MMC1_DAT0_OUT */
 381                         0x640 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OEN */
 382                         0x644 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OUT */
 383                         0x64c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OEN */
 384                         0x650 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OUT */
 385                         0x658 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OEN */
 386                         0x65c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OUT */
 387                 >;
 388         };
 389
 390         /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
 391         mmc2_iodelay_hs200_rev11_conf: mmc2_iodelay_hs200_rev11_conf {
 392                 pinctrl-pin-array = <
 393                         0x190 A_DELAY_PS(621) G_DELAY_PS(600)   /* CFG_GPMC_A19_OEN */
 394                         0x194 A_DELAY_PS(300) G_DELAY_PS(0)     /* CFG_GPMC_A19_OUT */
 395                         0x1a8 A_DELAY_PS(739) G_DELAY_PS(600)   /* CFG_GPMC_A20_OEN */
 396                         0x1ac A_DELAY_PS(240) G_DELAY_PS(0)     /* CFG_GPMC_A20_OUT */
 397                         0x1b4 A_DELAY_PS(812) G_DELAY_PS(600)   /* CFG_GPMC_A21_OEN */
 398                         0x1b8 A_DELAY_PS(240) G_DELAY_PS(0)     /* CFG_GPMC_A21_OUT */
 399                         0x1c0 A_DELAY_PS(954) G_DELAY_PS(600)   /* CFG_GPMC_A22_OEN */
 400                         0x1c4 A_DELAY_PS(60)  G_DELAY_PS(0)     /* CFG_GPMC_A22_OUT */
 401                         0x1d0 A_DELAY_PS(1340) G_DELAY_PS(420)  /* CFG_GPMC_A23_OUT */
 402                         0x1d8 A_DELAY_PS(935) G_DELAY_PS(600)   /* CFG_GPMC_A24_OEN */
 403                         0x1dc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A24_OUT */
 404                         0x1e4 A_DELAY_PS(525) G_DELAY_PS(600)   /* CFG_GPMC_A25_OEN */
 405                         0x1e8 A_DELAY_PS(120) G_DELAY_PS(0)     /* CFG_GPMC_A25_OUT */
 406                         0x1f0 A_DELAY_PS(767) G_DELAY_PS(600)   /* CFG_GPMC_A26_OEN */
 407                         0x1f4 A_DELAY_PS(225) G_DELAY_PS(0)     /* CFG_GPMC_A26_OUT */
 408                         0x1fc A_DELAY_PS(565) G_DELAY_PS(600)   /* CFG_GPMC_A27_OEN */
 409                         0x200 A_DELAY_PS(60) G_DELAY_PS(0)      /* CFG_GPMC_A27_OUT */
 410                         0x364 A_DELAY_PS(969) G_DELAY_PS(600)   /* CFG_GPMC_CS1_OEN */
 411                         0x368 A_DELAY_PS(180) G_DELAY_PS(0)     /* CFG_GPMC_CS1_OUT */
 412               >;
 413         };
 414
 415         /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
 416         mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
 417                 pinctrl-pin-array = <
 418                         0x190 A_DELAY_PS(274) G_DELAY_PS(0)       /* CFG_GPMC_A19_OEN */
 419                         0x194 A_DELAY_PS(162) G_DELAY_PS(0)       /* CFG_GPMC_A19_OUT */
 420                         0x1a8 A_DELAY_PS(401) G_DELAY_PS(0)       /* CFG_GPMC_A20_OEN */
 421                         0x1ac A_DELAY_PS(73) G_DELAY_PS(0)        /* CFG_GPMC_A20_OUT */
 422                         0x1b4 A_DELAY_PS(465) G_DELAY_PS(0)       /* CFG_GPMC_A21_OEN */
 423                         0x1b8 A_DELAY_PS(115) G_DELAY_PS(0)       /* CFG_GPMC_A21_OUT */
 424                         0x1c0 A_DELAY_PS(633) G_DELAY_PS(0)       /* CFG_GPMC_A22_OEN */
 425                         0x1c4 A_DELAY_PS(47) G_DELAY_PS(0)        /* CFG_GPMC_A22_OUT */
 426                         0x1d0 A_DELAY_PS(935) G_DELAY_PS(280)     /* CFG_GPMC_A23_OUT */
 427                         0x1d8 A_DELAY_PS(621) G_DELAY_PS(0)       /* CFG_GPMC_A24_OEN */
 428                         0x1dc A_DELAY_PS(0) G_DELAY_PS(0)         /* CFG_GPMC_A24_OUT */
 429                         0x1e4 A_DELAY_PS(183) G_DELAY_PS(0)       /* CFG_GPMC_A25_OEN */
 430                         0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)         /* CFG_GPMC_A25_OUT */
 431                         0x1f0 A_DELAY_PS(467) G_DELAY_PS(0)       /* CFG_GPMC_A26_OEN */
 432                         0x1f4 A_DELAY_PS(0) G_DELAY_PS(0)         /* CFG_GPMC_A26_OUT */
 433                         0x1fc A_DELAY_PS(262) G_DELAY_PS(0)       /* CFG_GPMC_A27_OEN */
 434                         0x200 A_DELAY_PS(46) G_DELAY_PS(0)        /* CFG_GPMC_A27_OUT */
 435                         0x364 A_DELAY_PS(684) G_DELAY_PS(0)       /* CFG_GPMC_CS1_OEN */
 436                         0x368 A_DELAY_PS(76) G_DELAY_PS(0)        /* CFG_GPMC_CS1_OUT */
 437               >;
 438         };
 439
 440         /* Correspnds to MMC2_DDR_3V3_MANUAL1 in datamanual */
 441         mmc2_iodelay_ddr_3_3v_rev11_conf: mmc2_iodelay_ddr_3_3v_rev11_conf {
 442                 pinctrl-pin-array = <
 443                         0x18c A_DELAY_PS(0) G_DELAY_PS(120)     /* CFG_GPMC_A19_IN */
 444                         0x190 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A19_OEN */
 445                         0x194 A_DELAY_PS(174) G_DELAY_PS(0)     /* CFG_GPMC_A19_OUT */
 446                         0x1a4 A_DELAY_PS(265) G_DELAY_PS(360)   /* CFG_GPMC_A20_IN */
 447                         0x1a8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A20_OEN */
 448                         0x1ac A_DELAY_PS(168) G_DELAY_PS(0)     /* CFG_GPMC_A20_OUT */
 449                         0x1b0 A_DELAY_PS(0) G_DELAY_PS(120)     /* CFG_GPMC_A21_IN */
 450                         0x1b4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A21_OEN */
 451                         0x1b8 A_DELAY_PS(136) G_DELAY_PS(0)     /* CFG_GPMC_A21_OUT */
 452                         0x1bc A_DELAY_PS(0) G_DELAY_PS(120)     /* CFG_GPMC_A22_IN */
 453                         0x1c0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A22_OEN */
 454                         0x1c4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A22_OUT */
 455                         0x1c8 A_DELAY_PS(287) G_DELAY_PS(420)   /* CFG_GPMC_A23_IN */
 456                         0x1d0 A_DELAY_PS(879) G_DELAY_PS(0)     /* CFG_GPMC_A23_OUT */
 457                         0x1d4 A_DELAY_PS(144) G_DELAY_PS(240)   /* CFG_GPMC_A24_IN */
 458                         0x1d8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A24_OEN */
 459                         0x1dc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A24_OUT */
 460                         0x1e0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A25_IN */
 461                         0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A25_OEN */
 462                         0x1e8 A_DELAY_PS(34) G_DELAY_PS(0)      /* CFG_GPMC_A25_OUT */
 463                         0x1ec A_DELAY_PS(0) G_DELAY_PS(120)     /* CFG_GPMC_A26_IN */
 464                         0x1f0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A26_OEN */
 465                         0x1f4 A_DELAY_PS(120) G_DELAY_PS(0)     /* CFG_GPMC_A26_OUT */
 466                         0x1f8 A_DELAY_PS(120) G_DELAY_PS(180)   /* CFG_GPMC_A27_IN */
 467                         0x1fc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A27_OEN */
 468                         0x200 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A27_OUT */
 469                         0x360 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_CS1_IN */
 470                         0x364 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_CS1_OEN */
 471                         0x368 A_DELAY_PS(11) G_DELAY_PS(0)      /* CFG_GPMC_CS1_OUT */
 472                 >;
 473         };
 474
 475         /* Corresponds to MMC2_DDR_1V8_MANUAL1 in datamanual */
 476         mmc2_iodelay_ddr_1_8v_rev11_conf: mmc2_iodelay_ddr_1_8v_rev11_conf {
 477                 pinctrl-pin-array = <
 478                         0x18c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A19_IN */
 479                         0x190 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A19_OEN */
 480                         0x194 A_DELAY_PS(174) G_DELAY_PS(0)     /* CFG_GPMC_A19_OUT */
 481                         0x1a4 A_DELAY_PS(274) G_DELAY_PS(240)   /* CFG_GPMC_A20_IN */
 482                         0x1a8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A20_OEN */
 483                         0x1ac A_DELAY_PS(168) G_DELAY_PS(0)     /* CFG_GPMC_A20_OUT */
 484                         0x1b0 A_DELAY_PS(0) G_DELAY_PS(60)      /* CFG_GPMC_A21_IN */
 485                         0x1b4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A21_OEN */
 486                         0x1b8 A_DELAY_PS(136) G_DELAY_PS(0)     /* CFG_GPMC_A21_OUT */
 487                         0x1bc A_DELAY_PS(0) G_DELAY_PS(60)      /* CFG_GPMC_A22_IN */
 488                         0x1c0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A22_OEN */
 489                         0x1c4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A22_OUT */
 490                         0x1c8 A_DELAY_PS(514) G_DELAY_PS(360)   /* CFG_GPMC_A23_IN */
 491                         0x1d0 A_DELAY_PS(879) G_DELAY_PS(0)     /* CFG_GPMC_A23_OUT */
 492                         0x1d4 A_DELAY_PS(187) G_DELAY_PS(120)   /* CFG_GPMC_A24_IN */
 493                         0x1d8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A24_OEN */
 494                         0x1dc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A24_OUT */
 495                         0x1e0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A25_IN */
 496                         0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A25_OEN */
 497                         0x1e8 A_DELAY_PS(34) G_DELAY_PS(0)      /* CFG_GPMC_A25_OUT */
 498                         0x1ec A_DELAY_PS(0) G_DELAY_PS(60)      /* CFG_GPMC_A26_IN */
 499                         0x1f0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A26_OEN */
 500                         0x1f4 A_DELAY_PS(120) G_DELAY_PS(0)     /* CFG_GPMC_A26_OUT */
 501                         0x1f8 A_DELAY_PS(121) G_DELAY_PS(60)    /* CFG_GPMC_A27_IN */
 502                         0x1fc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A27_OEN */
 503                         0x200 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A27_OUT */
 504                         0x360 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_CS1_IN */
 505                         0x364 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_CS1_OEN */
 506                         0x368 A_DELAY_PS(11) G_DELAY_PS(0)      /* CFG_GPMC_CS1_OUT */
 507                 >;
 508         };
 509
 510         /* Corresponds to MMC3_MANUAL1 in datamanual */
 511         mmc3_iodelay_manual1_rev20_conf: mmc3_iodelay_manual1_conf {
 512                 pinctrl-pin-array = <
 513                         0x678 A_DELAY_PS(0) G_DELAY_PS(386)     /* CFG_MMC3_CLK_IN */
 514                         0x680 A_DELAY_PS(605) G_DELAY_PS(0)     /* CFG_MMC3_CLK_OUT */
 515                         0x684 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_IN */
 516                         0x688 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_OEN */
 517                         0x68c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_OUT */
 518                         0x690 A_DELAY_PS(171) G_DELAY_PS(0)     /* CFG_MMC3_DAT0_IN */
 519                         0x694 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT0_OEN */
 520                         0x698 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT0_OUT */
 521                         0x69c A_DELAY_PS(221) G_DELAY_PS(0)     /* CFG_MMC3_DAT1_IN */
 522                         0x6a0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT1_OEN */
 523                         0x6a4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT1_OUT */
 524                         0x6a8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_IN */
 525                         0x6ac A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_OEN */
 526                         0x6b0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_OUT */
 527                         0x6b4 A_DELAY_PS(474) G_DELAY_PS(0)     /* CFG_MMC3_DAT3_IN */
 528                         0x6b8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT3_OEN */
 529                         0x6bc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT3_OUT */
 530                 >;
 531         };
 532
 533         /* Corresponds to MMC3_MANUAL1 in datamanual */
 534         mmc3_iodelay_manual1_rev11_conf: mmc3_iodelay_manual1_conf {
 535                 pinctrl-pin-array = <
 536                         0x678 A_DELAY_PS(406) G_DELAY_PS(0)     /* CFG_MMC3_CLK_IN */
 537                         0x680 A_DELAY_PS(659) G_DELAY_PS(0)     /* CFG_MMC3_CLK_OUT */
 538                         0x684 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_IN */
 539                         0x688 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_OEN */
 540                         0x68c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_CMD_OUT */
 541                         0x690 A_DELAY_PS(130) G_DELAY_PS(0)     /* CFG_MMC3_DAT0_IN */
 542                         0x694 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT0_OEN */
 543                         0x698 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT0_OUT */
 544                         0x69c A_DELAY_PS(169) G_DELAY_PS(0)     /* CFG_MMC3_DAT1_IN */
 545                         0x6a0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT1_OEN */
 546                         0x6a4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT1_OUT */
 547                         0x6a8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_IN */
 548                         0x6ac A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_OEN */
 549                         0x6b0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT2_OUT */
 550                         0x6b4 A_DELAY_PS(457) G_DELAY_PS(0)     /* CFG_MMC3_DAT3_IN */
 551                         0x6b8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT3_OEN */
 552                         0x6bc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC3_DAT3_OUT */
 553                 >;
 554         };
 555
 556         /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
 557         mmc4_iodelay_ds_rev11_conf: mmc4_iodelay_ds_rev11_conf {
 558                 pinctrl-pin-array = <
 559                         0x840 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_CTSN_IN */
 560                         0x848 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_CTSN_OUT */
 561                         0x84c A_DELAY_PS(96) G_DELAY_PS(0)      /* CFG_UART1_RTSN_IN */
 562                         0x850 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OEN */
 563                         0x854 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OUT */
 564                         0x870 A_DELAY_PS(582) G_DELAY_PS(0)     /* CFG_UART2_CTSN_IN */
 565                         0x874 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OEN */
 566                         0x878 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OUT */
 567                         0x87c A_DELAY_PS(391) G_DELAY_PS(0)     /* CFG_UART2_RTSN_IN */
 568                         0x880 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OEN */
 569                         0x884 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OUT */
 570                         0x888 A_DELAY_PS(561) G_DELAY_PS(0)     /* CFG_UART2_RXD_IN */
 571                         0x88c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OEN */
 572                         0x890 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OUT */
 573                         0x894 A_DELAY_PS(588) G_DELAY_PS(0)     /* CFG_UART2_TXD_IN */
 574                         0x898 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OEN */
 575                         0x89c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OUT */
 576                 >;
 577         };
 578
 579         /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
 580         mmc4_iodelay_ds_rev20_conf: mmc4_iodelay_ds_rev20_conf {
 581                 pinctrl-pin-array = <
 582                         0x840 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_CTSN_IN */
 583                         0x848 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_CTSN_OUT */
 584                         0x84c A_DELAY_PS(307) G_DELAY_PS(0)     /* CFG_UART1_RTSN_IN */
 585                         0x850 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OEN */
 586                         0x854 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OUT */
 587                         0x870 A_DELAY_PS(785) G_DELAY_PS(0)     /* CFG_UART2_CTSN_IN */
 588                         0x874 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OEN */
 589                         0x878 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OUT */
 590                         0x87c A_DELAY_PS(613) G_DELAY_PS(0)     /* CFG_UART2_RTSN_IN */
 591                         0x880 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OEN */
 592                         0x884 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OUT */
 593                         0x888 A_DELAY_PS(683) G_DELAY_PS(0)     /* CFG_UART2_RXD_IN */
 594                         0x88c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OEN */
 595                         0x890 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OUT */
 596                         0x894 A_DELAY_PS(835) G_DELAY_PS(0)     /* CFG_UART2_TXD_IN */
 597                         0x898 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OEN */
 598                         0x89c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OUT */
 599                 >;
 600         };
 601
 602         /* Corresponds to MMC4_MANUAL1 in datamanual */
 603         mmc4_iodelay_sdr12_hs_sdr25_rev11_conf: mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
 604                 pinctrl-pin-array = <
 605                         0x840 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_CTSN_IN */
 606                         0x848 A_DELAY_PS(2651) G_DELAY_PS(0)    /* CFG_UART1_CTSN_OUT */
 607                         0x84c A_DELAY_PS(1572) G_DELAY_PS(0)    /* CFG_UART1_RTSN_IN */
 608                         0x850 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OEN */
 609                         0x854 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OUT */
 610                         0x870 A_DELAY_PS(1913) G_DELAY_PS(0)    /* CFG_UART2_CTSN_IN */
 611                         0x874 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OEN */
 612                         0x878 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OUT */
 613                         0x87c A_DELAY_PS(1721) G_DELAY_PS(0)    /* CFG_UART2_RTSN_IN */
 614                         0x880 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OEN */
 615                         0x884 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OUT */
 616                         0x888 A_DELAY_PS(1891) G_DELAY_PS(0)    /* CFG_UART2_RXD_IN */
 617                         0x88c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OEN */
 618                         0x890 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OUT */
 619                         0x894 A_DELAY_PS(1919) G_DELAY_PS(0)    /* CFG_UART2_TXD_IN */
 620                         0x898 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OEN */
 621                         0x89c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OUT */
 622                 >;
 623         };
 624
 625         /* Corresponds to MMC4_MANUAL1 in datamanual */
 626         mmc4_iodelay_sdr12_hs_sdr25_rev20_conf: mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
 627                 pinctrl-pin-array = <
 628                         0x840 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_CTSN_IN */
 629                         0x848 A_DELAY_PS(1147) G_DELAY_PS(0)    /* CFG_UART1_CTSN_OUT */
 630                         0x84c A_DELAY_PS(1834) G_DELAY_PS(0)    /* CFG_UART1_RTSN_IN */
 631                         0x850 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OEN */
 632                         0x854 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART1_RTSN_OUT */
 633                         0x870 A_DELAY_PS(2165) G_DELAY_PS(0)    /* CFG_UART2_CTSN_IN */
 634                         0x874 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OEN */
 635                         0x878 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_CTSN_OUT */
 636                         0x87c A_DELAY_PS(1929) G_DELAY_PS(64)   /* CFG_UART2_RTSN_IN */
 637                         0x880 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OEN */
 638                         0x884 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RTSN_OUT */
 639                         0x888 A_DELAY_PS(1935) G_DELAY_PS(128)  /* CFG_UART2_RXD_IN */
 640                         0x88c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OEN */
 641                         0x890 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_RXD_OUT */
 642                         0x894 A_DELAY_PS(2172) G_DELAY_PS(44)   /* CFG_UART2_TXD_IN */
 643                         0x898 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OEN */
 644                         0x89c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_UART2_TXD_OUT */
 645                 >;
 646         };
 647 };