arch/arm/boot/dts/dra72x-mmc-iodelay.dtsi

   1 /*
   2  * MMC IOdelay values for TI's DRA72x, DRA71x and AM571x SoCs.
   3  *
   4  * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /*
  17  * Rules for modifying this file:
  18  * a) Update of this file should typically correspond to a datamanual revision.
  19  *    Datamanual revision that was used should be updated in comment below.
  20  *    If there is no update to datamanual, do not update the values. If you
  21  *    need to use values different from that recommended by the datamanual
  22  *    for your design, then you should consider adding values to the device-
  23  *    -tree file for your board directly.
  24  * b) We keep the mode names as close to the datamanual as possible. So
  25  *    if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
  26  *    we follow that in code too.
  27  * c) If the values change between multiple revisions of silicon, we add
  28  *    a revision tag to both the new and old entry. Use 'rev10' for PG 1.0,
  29  *    'rev20' for PG 2.0 and so on.
  30  * d) The node name and node label should be the exact same string. This is
  31  *    to curb naming creativity and achieve consistency.
  32  * e) If in future, DRA71x and DRA72x values differ, then add 'dra71_' and
  33  *    'dra72_' tag to entries. Both the new and old entries should gain a tag.
  34  *
  35  * Datamanual Revisions:
  36  *
  37  * AM571x Silicon Revision 2.0: SPRS957D, Revised January 2017
  38  * AM571x Silicon Revision 1.0: SPRS919M, Revised November 2017
  39  * DRA71x : SPRS960B, Revised February 2017
  40  */
  41
  42 &dra7_pmx_core {
  43         mmc1_pins_default: mmc1_pins_default {
  44                 pinctrl-single,pins = <
  45                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  46                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  47                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  48                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  49                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  50                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  51                 >;
  52         };
  53
  54         mmc1_pins_sdr12: mmc1_pins_sdr12 {
  55                 pinctrl-single,pins = <
  56                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  57                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  58                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  59                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  60                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  61                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  62                 >;
  63         };
  64
  65         mmc1_pins_hs: mmc1_pins_hs {
  66                 pinctrl-single,pins = <
  67                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  68                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  69                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  70                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  71                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  72                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  73                 >;
  74         };
  75
  76         mmc1_pins_sdr25: mmc1_pins_sdr25 {
  77                 pinctrl-single,pins = <
  78                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
  79                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
  80                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
  81                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
  82                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
  83                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
  84                 >;
  85         };
  86
  87         mmc1_pins_sdr50: mmc1_pins_sdr50 {
  88                 pinctrl-single,pins = <
  89                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)    /* mmc1_clk.clk */
  90                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)    /* mmc1_cmd.cmd */
  91                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)    /* mmc1_dat0.dat0 */
  92                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)    /* mmc1_dat1.dat1 */
  93                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)    /* mmc1_dat2.dat2 */
  94                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE15 | MUX_MODE0)    /* mmc1_dat3.dat3 */
  95                 >;
  96         };
  97
  98         mmc1_pins_ddr50_rev10: mmc1_pins_ddr50_rev10 {
  99                 pinctrl-single,pins = <
 100                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)    /* mmc1_clk.mmc1_clk */
 101                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)    /* mmc1_cmd.mmc1_cmd */
 102                         DRA7XX_CORE_IOPAD(0x375C, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)    /* mmc1_dat0.mmc1_dat0 */
 103                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)    /* mmc1_dat1.mmc1_dat1 */
 104                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)    /* mmc1_dat2.mmc1_dat2 */
 105                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE14 | MUX_MODE0)    /* mmc1_dat3.mmc1_dat3 */
 106                 >;
 107         };
 108
 109         mmc1_pins_ddr50_rev20: mmc1_pins_ddr50_rev20 {
 110                 pinctrl-single,pins = <
 111                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_clk.clk */
 112                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_cmd.cmd */
 113                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat0.dat0 */
 114                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat1.dat1 */
 115                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat2.dat2 */
 116                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat3.dat3 */
 117                 >;
 118         };
 119
 120         mmc1_pins_sdr104: mmc1_pins_sdr104 {
 121                 pinctrl-single,pins = <
 122                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_clk.clk */
 123                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_cmd.cmd */
 124                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat0.dat0 */
 125                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat1.dat1 */
 126                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat2.dat2 */
 127                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)   /* mmc1_dat3.dat3 */
 128                 >;
 129         };
 130
 131         mmc2_pins_default: mmc2_pins_default {
 132                 pinctrl-single,pins = <
 133                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 134                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 135                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 136                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 137                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 138                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 139                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 140                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 141                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 142                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 143                 >;
 144         };
 145
 146         mmc2_pins_hs: mmc2_pins_hs {
 147                 pinctrl-single,pins = <
 148                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 149                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 150                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 151                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 152                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 153                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 154                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 155                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 156                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 157                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 158                 >;
 159         };
 160
 161         mmc2_pins_ddr_rev10: mmc2_pins_ddr_rev10 {
 162                 pinctrl-single,pins = <
 163                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 164                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 165                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 166                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 167                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 168                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 169                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 170                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 171                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 172                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 173                 >;
 174         };
 175
 176         mmc2_pins_ddr_rev20: mmc2_pins_ddr_rev20 {
 177                 pinctrl-single,pins = <
 178                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 179                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 180                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 181                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 182                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 183                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 184                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 185                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 186                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 187                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 188                 >;
 189         };
 190
 191         mmc2_pins_hs200: mmc2_pins_hs200 {
 192                 pinctrl-single,pins = <
 193                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 194                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 195                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 196                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 197                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 198                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 199                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 200                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 201                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 202                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 203                 >;
 204         };
 205
 206         mmc4_pins_default: mmc4_pins_default {
 207                 pinctrl-single,pins = <
 208                         DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
 209                         DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
 210                         DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
 211                         DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
 212                         DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
 213                         DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
 214                 >;
 215         };
 216 };
 217
 218 &dra7_iodelay_core {
 219
 220         /* Corresponds to MMC1_MANUAL1 in datamanual */
 221         mmc1_iodelay_ddr50_conf: mmc1_iodelay_ddr50_conf {
 222                 pinctrl-pin-array = <
 223                         0x618 A_DELAY_PS(588) G_DELAY_PS(0)     /* CFG_MMC1_CLK_IN */
 224                         0x624 A_DELAY_PS(1000) G_DELAY_PS(0)    /* CFG_MMC1_CMD_IN */
 225                         0x630 A_DELAY_PS(1375) G_DELAY_PS(0)    /* CFG_MMC1_DAT0_IN */
 226                         0x63C A_DELAY_PS(1000) G_DELAY_PS(0)    /* CFG_MMC1_DAT1_IN */
 227                         0x648 A_DELAY_PS(1000) G_DELAY_PS(0)    /* CFG_MMC1_DAT2_IN */
 228                         0x654 A_DELAY_PS(1000) G_DELAY_PS(0)    /* CFG_MMC1_DAT3_IN */
 229                         0x620 A_DELAY_PS(1230) G_DELAY_PS(0)    /* CFG_MMC1_CLK_OUT */
 230                         0x62C A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OUT */
 231                         0x638 A_DELAY_PS(56) G_DELAY_PS(0)      /* CFG_MMC1_DAT0_OUT */
 232                         0x644 A_DELAY_PS(76) G_DELAY_PS(0)      /* CFG_MMC1_DAT1_OUT */
 233                         0x650 A_DELAY_PS(91) G_DELAY_PS(0)      /* CFG_MMC1_DAT2_OUT */
 234                         0x65C A_DELAY_PS(99) G_DELAY_PS(0)      /* CFG_MMC1_DAT3_OUT */
 235                         0x628 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OEN */
 236                         0x634 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OEN */
 237                         0x640 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OEN */
 238                         0x64C A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT2_OEN */
 239                         0x658 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT3_OEN */
 240                 >;
 241         };
 242
 243         /* Corresponds to MMC1_MANUAL2 in datamanual */
 244         mmc1_iodelay_sdr104_rev10_conf: mmc1_iodelay_sdr104_rev10_conf {
 245                 pinctrl-pin-array = <
 246                         0x620 A_DELAY_PS(560) G_DELAY_PS(365)   /* CFG_MMC1_CLK_OUT */
 247                         0x62c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OUT */
 248                         0x638 A_DELAY_PS(29) G_DELAY_PS(0)      /* CFG_MMC1_DAT0_OUT */
 249                         0x644 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT1_OUT */
 250                         0x650 A_DELAY_PS(47) G_DELAY_PS(0)      /* CFG_MMC1_DAT2_OUT */
 251                         0x65c A_DELAY_PS(30) G_DELAY_PS(0)      /* CFG_MMC1_DAT3_OUT */
 252                         0x628 A_DELAY_PS(125) G_DELAY_PS(0)     /* CFG_MMC1_CMD_OEN */
 253                         0x634 A_DELAY_PS(43) G_DELAY_PS(0)      /* CFG_MMC1_DAT0_OEN */
 254                         0x640 A_DELAY_PS(433) G_DELAY_PS(0)     /* CFG_MMC1_DAT1_OEN */
 255                         0x64c A_DELAY_PS(287) G_DELAY_PS(0)     /* CFG_MMC1_DAT2_OEN */
 256                         0x658 A_DELAY_PS(351) G_DELAY_PS(0)     /* CFG_MMC1_DAT3_OEN */
 257                 >;
 258         };
 259
 260         /* Corresponds to MMC1_MANUAL2 in datamanual */
 261         mmc1_iodelay_sdr104_rev20_conf: mmc1_iodelay_sdr104_rev20_conf {
 262                 pinctrl-pin-array = <
 263                         0x620 A_DELAY_PS(520) G_DELAY_PS(320)   /* CFG_MMC1_CLK_OUT */
 264                         0x62c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_CMD_OUT */
 265                         0x638 A_DELAY_PS(40) G_DELAY_PS(0)      /* CFG_MMC1_DAT0_OUT */
 266                         0x644 A_DELAY_PS(83) G_DELAY_PS(0)      /* CFG_MMC1_DAT1_OUT */
 267                         0x650 A_DELAY_PS(98) G_DELAY_PS(0)      /* CFG_MMC1_DAT2_OUT */
 268                         0x65c A_DELAY_PS(106) G_DELAY_PS(0)     /* CFG_MMC1_DAT3_OUT */
 269                         0x628 A_DELAY_PS(51) G_DELAY_PS(0)      /* CFG_MMC1_CMD_OEN */
 270                         0x634 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_MMC1_DAT0_OEN */
 271                         0x640 A_DELAY_PS(363) G_DELAY_PS(0)     /* CFG_MMC1_DAT1_OEN */
 272                         0x64c A_DELAY_PS(199) G_DELAY_PS(0)     /* CFG_MMC1_DAT2_OEN */
 273                         0x658 A_DELAY_PS(273) G_DELAY_PS(0)     /* CFG_MMC1_DAT3_OEN */
 274                 >;
 275         };
 276
 277         /* Corresponds to MMC2_MANUAL1 in datamanual */
 278         mmc2_iodelay_ddr_conf: mmc2_iodelay_ddr_conf {
 279                 pinctrl-pin-array = <
 280                         0x18c A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A19_IN */
 281                         0x1a4 A_DELAY_PS(119) G_DELAY_PS(0)     /* CFG_GPMC_A20_IN */
 282                         0x1b0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A21_IN */
 283                         0x1bc A_DELAY_PS(18) G_DELAY_PS(0)      /* CFG_GPMC_A22_IN */
 284                         0x1c8 A_DELAY_PS(894) G_DELAY_PS(0)     /* CFG_GPMC_A23_IN */
 285                         0x1d4 A_DELAY_PS(30) G_DELAY_PS(0)      /* CFG_GPMC_A24_IN */
 286                         0x1e0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A25_IN */
 287                         0x1ec A_DELAY_PS(23) G_DELAY_PS(0)      /* CFG_GPMC_A26_IN */
 288                         0x1f8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A27_IN */
 289                         0x360 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_CS1_IN */
 290                         0x194 A_DELAY_PS(152) G_DELAY_PS(0)     /* CFG_GPMC_A19_OUT */
 291                         0x1ac A_DELAY_PS(206) G_DELAY_PS(0)     /* CFG_GPMC_A20_OUT */
 292                         0x1b8 A_DELAY_PS(78) G_DELAY_PS(0)      /* CFG_GPMC_A21_OUT */
 293                         0x1c4 A_DELAY_PS(2) G_DELAY_PS(0)       /* CFG_GPMC_A22_OUT */
 294                         0x1d0 A_DELAY_PS(266) G_DELAY_PS(0)     /* CFG_GPMC_A23_OUT */
 295                         0x1dc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A24_OUT */
 296                         0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A25_OUT */
 297                         0x1f4 A_DELAY_PS(43) G_DELAY_PS(0)      /* CFG_GPMC_A26_OUT */
 298                         0x200 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A27_OUT */
 299                         0x368 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_CS1_OUT */
 300                         0x190 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A19_OEN */
 301                         0x1a8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A20_OEN */
 302                         0x1b4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A21_OEN */
 303                         0x1c0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A22_OEN */
 304                         0x1d8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A24_OEN */
 305                         0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A25_OEN */
 306                         0x1f0 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A26_OEN */
 307                         0x1fc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A27_OEN */
 308                         0x364 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_CS1_OEN */
 309                 >;
 310         };
 311
 312         /* Corresponds to MMC2_MANUAL3 in datamanual */
 313         mmc2_iodelay_hs200_rev10_conf: mmc2_iodelay_hs200_rev10_conf {
 314                 pinctrl-pin-array = <
 315                         0x194 A_DELAY_PS(150) G_DELAY_PS(95)    /* CFG_GPMC_A19_OUT */
 316                         0x1ac A_DELAY_PS(250) G_DELAY_PS(0)     /* CFG_GPMC_A20_OUT */
 317                         0x1b8 A_DELAY_PS(125) G_DELAY_PS(0)     /* CFG_GPMC_A21_OUT */
 318                         0x1c4 A_DELAY_PS(100) G_DELAY_PS(0)     /* CFG_GPMC_A22_OUT */
 319                         0x1d0 A_DELAY_PS(870) G_DELAY_PS(415)   /* CFG_GPMC_A23_OUT */
 320                         0x1dc A_DELAY_PS(30) G_DELAY_PS(0)      /* CFG_GPMC_A24_OUT */
 321                         0x1e8 A_DELAY_PS(200) G_DELAY_PS(0)     /* CFG_GPMC_A25_OUT */
 322                         0x1f4 A_DELAY_PS(200) G_DELAY_PS(0)     /* CFG_GPMC_A26_OUT */
 323                         0x200 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A27_OUT */
 324                         0x368 A_DELAY_PS(240) G_DELAY_PS(0)     /* CFG_GPMC_CS1_OUT */
 325                         0x190 A_DELAY_PS(695) G_DELAY_PS(0)     /* CFG_GPMC_A19_OEN */
 326                         0x1a8 A_DELAY_PS(924) G_DELAY_PS(0)     /* CFG_GPMC_A20_OEN */
 327                         0x1b4 A_DELAY_PS(719) G_DELAY_PS(0)     /* CFG_GPMC_A21_OEN */
 328                         0x1c0 A_DELAY_PS(824) G_DELAY_PS(0)     /* CFG_GPMC_A22_OEN */
 329                         0x1d8 A_DELAY_PS(877) G_DELAY_PS(0)     /* CFG_GPMC_A24_OEN */
 330                         0x1e4 A_DELAY_PS(446) G_DELAY_PS(0)     /* CFG_GPMC_A25_OEN */
 331                         0x1f0 A_DELAY_PS(847) G_DELAY_PS(0)     /* CFG_GPMC_A26_OEN */
 332                         0x1fc A_DELAY_PS(586) G_DELAY_PS(0)     /* CFG_GPMC_A27_OEN */
 333                         0x364 A_DELAY_PS(1039) G_DELAY_PS(0)    /* CFG_GPMC_CS1_OEN */
 334                 >;
 335         };
 336
 337         /* Corresponds to MMC2_MANUAL3 in datamanual */
 338         mmc2_iodelay_hs200_rev20_conf: mmc2_iodelay_hs200_rev20_conf {
 339                 pinctrl-pin-array = <
 340                         0x194 A_DELAY_PS(285) G_DELAY_PS(0)     /* CFG_GPMC_A19_OUT */
 341                         0x1ac A_DELAY_PS(189) G_DELAY_PS(0)     /* CFG_GPMC_A20_OUT */
 342                         0x1b8 A_DELAY_PS(0) G_DELAY_PS(120)     /* CFG_GPMC_A21_OUT */
 343                         0x1c4 A_DELAY_PS(0) G_DELAY_PS(70)      /* CFG_GPMC_A22_OUT */
 344                         0x1d0 A_DELAY_PS(730) G_DELAY_PS(360)   /* CFG_GPMC_A23_OUT */
 345                         0x1dc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A24_OUT */
 346                         0x1e8 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A25_OUT */
 347                         0x1f4 A_DELAY_PS(70) G_DELAY_PS(0)      /* CFG_GPMC_A26_OUT */
 348                         0x200 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A27_OUT */
 349                         0x368 A_DELAY_PS(0) G_DELAY_PS(120)     /* CFG_GPMC_CS1_OUT */
 350                         0x190 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A19_OEN */
 351                         0x1a8 A_DELAY_PS(231) G_DELAY_PS(0)     /* CFG_GPMC_A20_OEN */
 352                         0x1b4 A_DELAY_PS(39) G_DELAY_PS(0)      /* CFG_GPMC_A21_OEN */
 353                         0x1c0 A_DELAY_PS(91) G_DELAY_PS(0)      /* CFG_GPMC_A22_OEN */
 354                         0x1d8 A_DELAY_PS(176) G_DELAY_PS(0)     /* CFG_GPMC_A24_OEN */
 355                         0x1e4 A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A25_OEN */
 356                         0x1f0 A_DELAY_PS(101) G_DELAY_PS(0)     /* CFG_GPMC_A26_OEN */
 357                         0x1fc A_DELAY_PS(0) G_DELAY_PS(0)       /* CFG_GPMC_A27_OEN */
 358                         0x364 A_DELAY_PS(360) G_DELAY_PS(0)     /* CFG_GPMC_CS1_OEN */
 359                 >;
 360         };
 361 };