arch/arm/boot/dts/dra72-evm-common.dtsi

   1 /*
   2  * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra72x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/clk/ti-dra7-atl.h>
  13
  14 / {
  15         compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
  16
  17         aliases {
  18                 display0 = &hdmi0;
  19         };
  20
  21         chosen {
  22                 stdout-path = &uart1;
  23         };
  24
  25         evm_12v0: fixedregulator-evm12v0 {
  26                 /* main supply */
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "evm_12v0";
  29                 regulator-min-microvolt = <12000000>;
  30                 regulator-max-microvolt = <12000000>;
  31                 regulator-always-on;
  32                 regulator-boot-on;
  33         };
  34
  35         evm_5v0: fixedregulator-evm5v0 {
  36                 /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
  37                 /* Output 1 of LM5140QRWGTQ1 on dra71-evm */
  38                 compatible = "regulator-fixed";
  39                 regulator-name = "evm_5v0";
  40                 regulator-min-microvolt = <5000000>;
  41                 regulator-max-microvolt = <5000000>;
  42                 vin-supply = <&evm_12v0>;
  43                 regulator-always-on;
  44                 regulator-boot-on;
  45         };
  46
  47         evm_3v6: fixedregulator-evm_3v6 {
  48                 compatible = "regulator-fixed";
  49                 regulator-name = "evm_3v6";
  50                 regulator-min-microvolt = <3600000>;
  51                 regulator-max-microvolt = <3600000>;
  52                 vin-supply = <&evm_5v0>;
  53                 regulator-always-on;
  54                 regulator-boot-on;
  55         };
  56
  57         vsys_3v3: fixedregulator-vsys3v3 {
  58                 /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
  59                 /* Output 2 of LM5140QRWGTQ1 on dra71-evm */
  60                 compatible = "regulator-fixed";
  61                 regulator-name = "vsys_3v3";
  62                 regulator-min-microvolt = <3300000>;
  63                 regulator-max-microvolt = <3300000>;
  64                 vin-supply = <&evm_12v0>;
  65                 regulator-always-on;
  66                 regulator-boot-on;
  67         };
  68
  69         evm_3v3_sw: fixedregulator-evm_3v3 {
  70                 /* TPS22965DSG */
  71                 compatible = "regulator-fixed";
  72                 regulator-name = "evm_3v3";
  73                 regulator-min-microvolt = <3300000>;
  74                 regulator-max-microvolt = <3300000>;
  75                 vin-supply = <&vsys_3v3>;
  76                 regulator-always-on;
  77                 regulator-boot-on;
  78         };
  79
  80         aic_dvdd: fixedregulator-aic_dvdd {
  81                 /* TPS77018DBVT */
  82                 compatible = "regulator-fixed";
  83                 regulator-name = "aic_dvdd";
  84                 vin-supply = <&evm_3v3_sw>;
  85                 regulator-min-microvolt = <1800000>;
  86                 regulator-max-microvolt = <1800000>;
  87         };
  88
  89         evm_3v3_sd: fixedregulator-sd {
  90                 compatible = "regulator-fixed";
  91                 regulator-name = "evm_3v3_sd";
  92                 regulator-min-microvolt = <3300000>;
  93                 regulator-max-microvolt = <3300000>;
  94                 vin-supply = <&evm_3v3_sw>;
  95                 enable-active-high;
  96                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  97         };
  98
  99         extcon_usb1: extcon_usb1 {
 100                 compatible = "linux,extcon-usb-gpio";
 101                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
 102         };
 103
 104         extcon_usb2: extcon_usb2 {
 105                 compatible = "linux,extcon-usb-gpio";
 106                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
 107         };
 108
 109         hdmi0: connector {
 110                 compatible = "hdmi-connector";
 111                 label = "hdmi";
 112
 113                 type = "a";
 114
 115                 port {
 116                         hdmi_connector_in: endpoint {
 117                                 remote-endpoint = <&tpd12s015_out>;
 118                         };
 119                 };
 120         };
 121
 122         tpd12s015: encoder {
 123                 compatible = "ti,tpd12s015";
 124
 125                 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
 126                         <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
 127                         <&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
 128
 129                 ports {
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132
 133                         port@0 {
 134                                 reg = <0>;
 135
 136                                 tpd12s015_in: endpoint {
 137                                         remote-endpoint = <&hdmi_out>;
 138                                 };
 139                         };
 140
 141                         port@1 {
 142                                 reg = <1>;
 143
 144                                 tpd12s015_out: endpoint {
 145                                         remote-endpoint = <&hdmi_connector_in>;
 146                                 };
 147                         };
 148                 };
 149         };
 150
 151         sound0: sound0 {
 152                 compatible = "simple-audio-card";
 153                 simple-audio-card,name = "DRA7xx-EVM";
 154                 simple-audio-card,widgets =
 155                         "Headphone", "Headphone Jack",
 156                         "Line", "Line Out",
 157                         "Microphone", "Mic Jack",
 158                         "Line", "Line In";
 159                 simple-audio-card,routing =
 160                         "Headphone Jack",       "HPLOUT",
 161                         "Headphone Jack",       "HPROUT",
 162                         "Line Out",             "LLOUT",
 163                         "Line Out",             "RLOUT",
 164                         "MIC3L",                "Mic Jack",
 165                         "MIC3R",                "Mic Jack",
 166                         "Mic Jack",             "Mic Bias",
 167                         "LINE1L",               "Line In",
 168                         "LINE1R",               "Line In";
 169                 simple-audio-card,format = "dsp_b";
 170                 simple-audio-card,bitclock-master = <&sound0_master>;
 171                 simple-audio-card,frame-master = <&sound0_master>;
 172                 simple-audio-card,bitclock-inversion;
 173
 174                 sound0_master: simple-audio-card,cpu {
 175                         sound-dai = <&mcasp3>;
 176                         system-clock-frequency = <5644800>;
 177                 };
 178
 179                 simple-audio-card,codec {
 180                         sound-dai = <&tlv320aic3106>;
 181                         clocks = <&atl_clkin2_ck>;
 182                 };
 183         };
 184
 185         vmmcwl_fixed: fixedregulator-mmcwl {
 186                 compatible = "regulator-fixed";
 187                 regulator-name = "vmmcwl_fixed";
 188                 regulator-min-microvolt = <1800000>;
 189                 regulator-max-microvolt = <1800000>;
 190                 gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
 191                 enable-active-high;
 192         };
 193 };
 194
 195 &dra7_pmx_core {
 196         dcan1_pins_default: dcan1_pins_default {
 197                 pinctrl-single,pins = <
 198                         DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 199                         DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1)  /* wakeup0.dcan1_rx */
 200                 >;
 201         };
 202
 203         dcan1_pins_sleep: dcan1_pins_sleep {
 204                 pinctrl-single,pins = <
 205                         DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
 206                         DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
 207                 >;
 208         };
 209 };
 210
 211 &i2c1 {
 212         status = "okay";
 213         clock-frequency = <400000>;
 214
 215         pcf_lcd: gpio@20 {
 216                 compatible = "nxp,pcf8575";
 217                 reg = <0x20>;
 218                 gpio-controller;
 219                 #gpio-cells = <2>;
 220                 interrupt-controller;
 221                 #interrupt-cells = <2>;
 222         };
 223
 224         pcf_gpio_21: gpio@21 {
 225                 compatible = "ti,pcf8575", "nxp,pcf8575";
 226                 reg = <0x21>;
 227                 lines-initial-states = <0x1408>;
 228                 gpio-controller;
 229                 #gpio-cells = <2>;
 230                 interrupt-controller;
 231                 #interrupt-cells = <2>;
 232         };
 233
 234         tlv320aic3106: tlv320aic3106@19 {
 235                 #sound-dai-cells = <0>;
 236                 compatible = "ti,tlv320aic3106";
 237                 reg = <0x19>;
 238                 adc-settle-ms = <40>;
 239                 ai3x-micbias-vg = <1>;          /* 2.0V */
 240                 status = "okay";
 241
 242                 /* Regulators */
 243                 AVDD-supply = <&evm_3v3_sw>;
 244                 IOVDD-supply = <&evm_3v3_sw>;
 245                 DRVDD-supply = <&evm_3v3_sw>;
 246                 DVDD-supply = <&aic_dvdd>;
 247         };
 248 };
 249
 250 &i2c5 {
 251         status = "okay";
 252         clock-frequency = <400000>;
 253
 254         pcf_hdmi: pcf8575@26 {
 255                 compatible = "ti,pcf8575", "nxp,pcf8575";
 256                 reg = <0x26>;
 257                 gpio-controller;
 258                 #gpio-cells = <2>;
 259                 /*
 260                  * initial state is used here to keep the mdio interface
 261                  * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
 262                  * VIN2_S0 driven high otherwise Ethernet stops working
 263                  * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
 264                  */
 265                 lines-initial-states = <0x0f2b>;
 266
 267                 p1 {
 268                         /* vin6_sel_s0: high: VIN6, low: audio */
 269                         gpio-hog;
 270                         gpios = <1 GPIO_ACTIVE_HIGH>;
 271                         output-low;
 272                         line-name = "vin6_sel_s0";
 273                 };
 274         };
 275 };
 276
 277 &uart1 {
 278         status = "okay";
 279         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 280                               <&dra7_pmx_core 0x3e0>;
 281 };
 282
 283 &elm {
 284         status = "okay";
 285 };
 286
 287 &gpmc {
 288         /*
 289          * For the existing IOdelay configuration via U-Boot we don't
 290          * support NAND on dra72-evm. Keep it disabled. Enabling it
 291          * requires a different configuration by U-Boot.
 292          */
 293         status = "disabled";
 294         ranges = <0 0 0x08000000 0x01000000>;   /* minimum GPMC partition = 16MB */
 295         nand@0,0 {
 296                 /* To use NAND, DIP switch SW5 must be set like so:
 297                  * SW5.1 (NAND_SELn) = ON (LOW)
 298                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 299                  */
 300                 compatible = "ti,omap2-nand";
 301                 reg = <0 0 4>;          /* device IO registers */
 302                 interrupt-parent = <&gpmc>;
 303                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 304                              <1 IRQ_TYPE_NONE>; /* termcount */
 305                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
 306                 ti,nand-xfer-type = "prefetch-dma";
 307                 ti,nand-ecc-opt = "bch8";
 308                 ti,elm-id = <&elm>;
 309                 nand-bus-width = <16>;
 310                 gpmc,device-width = <2>;
 311                 gpmc,sync-clk-ps = <0>;
 312                 gpmc,cs-on-ns = <0>;
 313                 gpmc,cs-rd-off-ns = <80>;
 314                 gpmc,cs-wr-off-ns = <80>;
 315                 gpmc,adv-on-ns = <0>;
 316                 gpmc,adv-rd-off-ns = <60>;
 317                 gpmc,adv-wr-off-ns = <60>;
 318                 gpmc,we-on-ns = <10>;
 319                 gpmc,we-off-ns = <50>;
 320                 gpmc,oe-on-ns = <4>;
 321                 gpmc,oe-off-ns = <40>;
 322                 gpmc,access-ns = <40>;
 323                 gpmc,wr-access-ns = <80>;
 324                 gpmc,rd-cycle-ns = <80>;
 325                 gpmc,wr-cycle-ns = <80>;
 326                 gpmc,bus-turnaround-ns = <0>;
 327                 gpmc,cycle2cycle-delay-ns = <0>;
 328                 gpmc,clk-activation-ns = <0>;
 329                 gpmc,wr-data-mux-bus-ns = <0>;
 330                 /* MTD partition table */
 331                 /* All SPL-* partitions are sized to minimal length
 332                  * which can be independently programmable. For
 333                  * NAND flash this is equal to size of erase-block */
 334                 #address-cells = <1>;
 335                 #size-cells = <1>;
 336                 partition@0 {
 337                         label = "NAND.SPL";
 338                         reg = <0x00000000 0x000020000>;
 339                 };
 340                 partition@1 {
 341                         label = "NAND.SPL.backup1";
 342                         reg = <0x00020000 0x00020000>;
 343                 };
 344                 partition@2 {
 345                         label = "NAND.SPL.backup2";
 346                         reg = <0x00040000 0x00020000>;
 347                 };
 348                 partition@3 {
 349                         label = "NAND.SPL.backup3";
 350                         reg = <0x00060000 0x00020000>;
 351                 };
 352                 partition@4 {
 353                         label = "NAND.u-boot-spl-os";
 354                         reg = <0x00080000 0x00040000>;
 355                 };
 356                 partition@5 {
 357                         label = "NAND.u-boot";
 358                         reg = <0x000c0000 0x00100000>;
 359                 };
 360                 partition@6 {
 361                         label = "NAND.u-boot-env";
 362                         reg = <0x001c0000 0x00020000>;
 363                 };
 364                 partition@7 {
 365                         label = "NAND.u-boot-env.backup1";
 366                         reg = <0x001e0000 0x00020000>;
 367                 };
 368                 partition@8 {
 369                         label = "NAND.kernel";
 370                         reg = <0x00200000 0x00800000>;
 371                 };
 372                 partition@9 {
 373                         label = "NAND.file-system";
 374                         reg = <0x00a00000 0x0f600000>;
 375                 };
 376         };
 377 };
 378
 379 &omap_dwc3_1 {
 380         extcon = <&extcon_usb1>;
 381 };
 382
 383 &omap_dwc3_2 {
 384         extcon = <&extcon_usb2>;
 385 };
 386
 387 &usb1 {
 388         dr_mode = "otg";
 389         extcon = <&extcon_usb1>;
 390 };
 391
 392 &usb2 {
 393         dr_mode = "host";
 394 };
 395
 396 &mmc1 {
 397         status = "okay";
 398         pinctrl-names = "default";
 399         pinctrl-0 = <&mmc1_pins_default>;
 400         vmmc-supply = <&evm_3v3_sd>;
 401         bus-width = <4>;
 402         /*
 403          * SDCD signal is not being used here - using the fact that GPIO mode
 404          * is a viable alternative
 405          */
 406         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 407         max-frequency = <192000000>;
 408 };
 409
 410 &mmc2 {
 411         /* SW5-3 in ON position */
 412         status = "okay";
 413         pinctrl-names = "default";
 414         pinctrl-0 = <&mmc2_pins_default>;
 415         bus-width = <8>;
 416         non-removable;
 417         max-frequency = <192000000>;
 418 };
 419
 420 &mmc4 {
 421         status = "okay";
 422         vmmc-supply = <&evm_3v6>;
 423         vqmmc-supply = <&vmmcwl_fixed>;
 424         bus-width = <4>;
 425         cap-power-off-card;
 426         keep-power-in-suspend;
 427         non-removable;
 428         pinctrl-names = "default", "hs", "sdr12", "sdr25";
 429         pinctrl-0 = <&mmc4_pins_default>;
 430         pinctrl-1 = <&mmc4_pins_default>;
 431         pinctrl-2 = <&mmc4_pins_default>;
 432         pinctrl-3 = <&mmc4_pins_default>;
 433         #address-cells = <1>;
 434         #size-cells = <0>;
 435         wifi@2 {
 436                 compatible = "ti,wl1835";
 437                 reg = <2>;
 438                 interrupt-parent = <&gpio5>;
 439                 interrupts = <7 IRQ_TYPE_EDGE_RISING>;
 440         };
 441 };
 442
 443 &mac {
 444         status = "okay";
 445 };
 446
 447 &dcan1 {
 448         status = "ok";
 449         pinctrl-names = "default", "sleep", "active";
 450         pinctrl-0 = <&dcan1_pins_sleep>;
 451         pinctrl-1 = <&dcan1_pins_sleep>;
 452         pinctrl-2 = <&dcan1_pins_default>;
 453 };
 454
 455 &qspi {
 456         status = "okay";
 457
 458         spi-max-frequency = <76800000>;
 459         m25p80@0 {
 460                 compatible = "s25fl256s1";
 461                 spi-max-frequency = <76800000>;
 462                 reg = <0>;
 463                 spi-tx-bus-width = <1>;
 464                 spi-rx-bus-width = <4>;
 465                 #address-cells = <1>;
 466                 #size-cells = <1>;
 467
 468                 /* MTD partition table.
 469                  * The ROM checks the first four physical blocks
 470                  * for a valid file to boot and the flash here is
 471                  * 64KiB block size.
 472                  */
 473                 partition@0 {
 474                         label = "QSPI.SPL";
 475                         reg = <0x00000000 0x000010000>;
 476                 };
 477                 partition@1 {
 478                         label = "QSPI.SPL.backup1";
 479                         reg = <0x00010000 0x00010000>;
 480                 };
 481                 partition@2 {
 482                         label = "QSPI.SPL.backup2";
 483                         reg = <0x00020000 0x00010000>;
 484                 };
 485                 partition@3 {
 486                         label = "QSPI.SPL.backup3";
 487                         reg = <0x00030000 0x00010000>;
 488                 };
 489                 partition@4 {
 490                         label = "QSPI.u-boot";
 491                         reg = <0x00040000 0x00100000>;
 492                 };
 493                 partition@5 {
 494                         label = "QSPI.u-boot-spl-os";
 495                         reg = <0x00140000 0x00080000>;
 496                 };
 497                 partition@6 {
 498                         label = "QSPI.u-boot-env";
 499                         reg = <0x001c0000 0x00010000>;
 500                 };
 501                 partition@7 {
 502                         label = "QSPI.u-boot-env.backup1";
 503                         reg = <0x001d0000 0x0010000>;
 504                 };
 505                 partition@8 {
 506                         label = "QSPI.kernel";
 507                         reg = <0x001e0000 0x0800000>;
 508                 };
 509                 partition@9 {
 510                         label = "QSPI.file-system";
 511                         reg = <0x009e0000 0x01620000>;
 512                 };
 513         };
 514 };
 515
 516 &dss {
 517         status = "ok";
 518 };
 519
 520 &hdmi {
 521         status = "ok";
 522
 523         port {
 524                 hdmi_out: endpoint {
 525                         remote-endpoint = <&tpd12s015_in>;
 526                 };
 527         };
 528 };
 529
 530 &atl {
 531         assigned-clocks = <&abe_dpll_sys_clk_mux>,
 532                           <&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
 533                           <&dpll_abe_ck>,
 534                           <&dpll_abe_m2x2_ck>,
 535                           <&atl_clkin2_ck>;
 536         assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
 537         assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
 538
 539         status = "okay";
 540
 541         atl2 {
 542                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 543                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 544         };
 545 };
 546
 547 &mcasp3 {
 548         #sound-dai-cells = <0>;
 549
 550         assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
 551         assigned-clock-parents = <&atl_clkin2_ck>;
 552
 553         status = "okay";
 554
 555         op-mode = <0>;          /* MCASP_IIS_MODE */
 556         tdm-slots = <2>;
 557         /* 4 serializer */
 558         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 559                 1 2 0 0
 560         >;
 561         tx-num-evt = <32>;
 562         rx-num-evt = <32>;
 563 };
 564
 565 &mailbox5 {
 566         status = "okay";
 567         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 568                 status = "okay";
 569         };
 570         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 571                 status = "okay";
 572         };
 573 };
 574
 575 &mailbox6 {
 576         status = "okay";
 577         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 578                 status = "okay";
 579         };
 580 };
 581
 582 &pcie1_rc {
 583         status = "okay";
 584 };