arch/arm/boot/dts/dra72-evm-common.dtsi

   1 /*
   2  * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra72x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/clk/ti-dra7-atl.h>
  13
  14 / {
  15         compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
  16
  17         aliases {
  18                 display0 = &hdmi0;
  19         };
  20
  21         chosen {
  22                 stdout-path = &uart1;
  23         };
  24
  25         evm_12v0: fixedregulator-evm12v0 {
  26                 /* main supply */
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "evm_12v0";
  29                 regulator-min-microvolt = <12000000>;
  30                 regulator-max-microvolt = <12000000>;
  31                 regulator-always-on;
  32                 regulator-boot-on;
  33         };
  34
  35         evm_5v0: fixedregulator-evm5v0 {
  36                 /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */
  37                 /* Output 1 of LM5140QRWGTQ1 on dra71-evm */
  38                 compatible = "regulator-fixed";
  39                 regulator-name = "evm_5v0";
  40                 regulator-min-microvolt = <5000000>;
  41                 regulator-max-microvolt = <5000000>;
  42                 vin-supply = <&evm_12v0>;
  43                 regulator-always-on;
  44                 regulator-boot-on;
  45         };
  46
  47         vsys_3v3: fixedregulator-vsys3v3 {
  48                 /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */
  49                 /* Output 2 of LM5140QRWGTQ1 on dra71-evm */
  50                 compatible = "regulator-fixed";
  51                 regulator-name = "vsys_3v3";
  52                 regulator-min-microvolt = <3300000>;
  53                 regulator-max-microvolt = <3300000>;
  54                 vin-supply = <&evm_12v0>;
  55                 regulator-always-on;
  56                 regulator-boot-on;
  57         };
  58
  59         evm_3v3_sw: fixedregulator-evm_3v3 {
  60                 /* TPS22965DSG */
  61                 compatible = "regulator-fixed";
  62                 regulator-name = "evm_3v3";
  63                 regulator-min-microvolt = <3300000>;
  64                 regulator-max-microvolt = <3300000>;
  65                 vin-supply = <&vsys_3v3>;
  66                 regulator-always-on;
  67                 regulator-boot-on;
  68         };
  69
  70         aic_dvdd: fixedregulator-aic_dvdd {
  71                 /* TPS77018DBVT */
  72                 compatible = "regulator-fixed";
  73                 regulator-name = "aic_dvdd";
  74                 vin-supply = <&evm_3v3_sw>;
  75                 regulator-min-microvolt = <1800000>;
  76                 regulator-max-microvolt = <1800000>;
  77         };
  78
  79         evm_3v3_sd: fixedregulator-sd {
  80                 compatible = "regulator-fixed";
  81                 regulator-name = "evm_3v3_sd";
  82                 regulator-min-microvolt = <3300000>;
  83                 regulator-max-microvolt = <3300000>;
  84                 vin-supply = <&evm_3v3_sw>;
  85                 enable-active-high;
  86                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  87         };
  88
  89         extcon_usb1: extcon_usb1 {
  90                 compatible = "linux,extcon-usb-gpio";
  91                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  92         };
  93
  94         extcon_usb2: extcon_usb2 {
  95                 compatible = "linux,extcon-usb-gpio";
  96                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  97         };
  98
  99         hdmi0: connector {
 100                 compatible = "hdmi-connector";
 101                 label = "hdmi";
 102
 103                 type = "a";
 104
 105                 port {
 106                         hdmi_connector_in: endpoint {
 107                                 remote-endpoint = <&tpd12s015_out>;
 108                         };
 109                 };
 110         };
 111
 112         tpd12s015: encoder {
 113                 compatible = "ti,tpd12s015";
 114
 115                 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */
 116                         <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
 117                         <&gpio7 12 GPIO_ACTIVE_HIGH>;   /* gpio7_12/sp1_cs2, HPD */
 118
 119                 ports {
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122
 123                         port@0 {
 124                                 reg = <0>;
 125
 126                                 tpd12s015_in: endpoint {
 127                                         remote-endpoint = <&hdmi_out>;
 128                                 };
 129                         };
 130
 131                         port@1 {
 132                                 reg = <1>;
 133
 134                                 tpd12s015_out: endpoint {
 135                                         remote-endpoint = <&hdmi_connector_in>;
 136                                 };
 137                         };
 138                 };
 139         };
 140
 141         sound0: sound0 {
 142                 compatible = "simple-audio-card";
 143                 simple-audio-card,name = "DRA7xx-EVM";
 144                 simple-audio-card,widgets =
 145                         "Headphone", "Headphone Jack",
 146                         "Line", "Line Out",
 147                         "Microphone", "Mic Jack",
 148                         "Line", "Line In";
 149                 simple-audio-card,routing =
 150                         "Headphone Jack",       "HPLOUT",
 151                         "Headphone Jack",       "HPROUT",
 152                         "Line Out",             "LLOUT",
 153                         "Line Out",             "RLOUT",
 154                         "MIC3L",                "Mic Jack",
 155                         "MIC3R",                "Mic Jack",
 156                         "Mic Jack",             "Mic Bias",
 157                         "LINE1L",               "Line In",
 158                         "LINE1R",               "Line In";
 159                 simple-audio-card,format = "dsp_b";
 160                 simple-audio-card,bitclock-master = <&sound0_master>;
 161                 simple-audio-card,frame-master = <&sound0_master>;
 162                 simple-audio-card,bitclock-inversion;
 163
 164                 sound0_master: simple-audio-card,cpu {
 165                         sound-dai = <&mcasp3>;
 166                         system-clock-frequency = <5644800>;
 167                 };
 168
 169                 simple-audio-card,codec {
 170                         sound-dai = <&tlv320aic3106>;
 171                         clocks = <&atl_clkin2_ck>;
 172                 };
 173         };
 174 };
 175
 176 &dra7_pmx_core {
 177         mmc1_pins_default: mmc1_pins_default {
 178                 pinctrl-single,pins = <
 179                         DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)       /* mmc1sdcd.gpio219 */
 180                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
 181                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
 182                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
 183                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
 184                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
 185                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
 186                 >;
 187         };
 188
 189         mmc2_pins_default: mmc2_pins_default {
 190                 pinctrl-single,pins = <
 191                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 192                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 193                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 194                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 195                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 196                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 197                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 198                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 199                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 200                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 201                 >;
 202         };
 203
 204         dcan1_pins_default: dcan1_pins_default {
 205                 pinctrl-single,pins = <
 206                         DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 207                         DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1)  /* wakeup0.dcan1_rx */
 208                 >;
 209         };
 210
 211         dcan1_pins_sleep: dcan1_pins_sleep {
 212                 pinctrl-single,pins = <
 213                         DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
 214                         DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
 215                 >;
 216         };
 217 };
 218
 219 &i2c1 {
 220         status = "okay";
 221         clock-frequency = <400000>;
 222
 223         pcf_lcd: gpio@20 {
 224                 compatible = "nxp,pcf8575";
 225                 reg = <0x20>;
 226                 gpio-controller;
 227                 #gpio-cells = <2>;
 228                 interrupt-controller;
 229                 #interrupt-cells = <2>;
 230         };
 231
 232         pcf_gpio_21: gpio@21 {
 233                 compatible = "ti,pcf8575", "nxp,pcf8575";
 234                 reg = <0x21>;
 235                 lines-initial-states = <0x1408>;
 236                 gpio-controller;
 237                 #gpio-cells = <2>;
 238                 interrupt-controller;
 239                 #interrupt-cells = <2>;
 240         };
 241
 242         tlv320aic3106: tlv320aic3106@19 {
 243                 #sound-dai-cells = <0>;
 244                 compatible = "ti,tlv320aic3106";
 245                 reg = <0x19>;
 246                 adc-settle-ms = <40>;
 247                 ai3x-micbias-vg = <1>;          /* 2.0V */
 248                 status = "okay";
 249
 250                 /* Regulators */
 251                 AVDD-supply = <&evm_3v3_sw>;
 252                 IOVDD-supply = <&evm_3v3_sw>;
 253                 DRVDD-supply = <&evm_3v3_sw>;
 254                 DVDD-supply = <&aic_dvdd>;
 255         };
 256 };
 257
 258 &i2c5 {
 259         status = "okay";
 260         clock-frequency = <400000>;
 261
 262         pcf_hdmi: pcf8575@26 {
 263                 compatible = "ti,pcf8575", "nxp,pcf8575";
 264                 reg = <0x26>;
 265                 gpio-controller;
 266                 #gpio-cells = <2>;
 267                 /*
 268                  * initial state is used here to keep the mdio interface
 269                  * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and
 270                  * VIN2_S0 driven high otherwise Ethernet stops working
 271                  * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6
 272                  */
 273                 lines-initial-states = <0x0f2b>;
 274
 275                 p1 {
 276                         /* vin6_sel_s0: high: VIN6, low: audio */
 277                         gpio-hog;
 278                         gpios = <1 GPIO_ACTIVE_HIGH>;
 279                         output-low;
 280                         line-name = "vin6_sel_s0";
 281                 };
 282         };
 283 };
 284
 285 &uart1 {
 286         status = "okay";
 287         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 288                               <&dra7_pmx_core 0x3e0>;
 289 };
 290
 291 &elm {
 292         status = "okay";
 293 };
 294
 295 &gpmc {
 296         /*
 297          * For the existing IOdelay configuration via U-Boot we don't
 298          * support NAND on dra72-evm. Keep it disabled. Enabling it
 299          * requires a different configuration by U-Boot.
 300          */
 301         status = "disabled";
 302         ranges = <0 0 0x08000000 0x01000000>;   /* minimum GPMC partition = 16MB */
 303         nand@0,0 {
 304                 /* To use NAND, DIP switch SW5 must be set like so:
 305                  * SW5.1 (NAND_SELn) = ON (LOW)
 306                  * SW5.9 (GPMC_WPN) = OFF (HIGH)
 307                  */
 308                 compatible = "ti,omap2-nand";
 309                 reg = <0 0 4>;          /* device IO registers */
 310                 interrupt-parent = <&gpmc>;
 311                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 312                              <1 IRQ_TYPE_NONE>; /* termcount */
 313                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
 314                 ti,nand-ecc-opt = "bch8";
 315                 ti,elm-id = <&elm>;
 316                 nand-bus-width = <16>;
 317                 gpmc,device-width = <2>;
 318                 gpmc,sync-clk-ps = <0>;
 319                 gpmc,cs-on-ns = <0>;
 320                 gpmc,cs-rd-off-ns = <80>;
 321                 gpmc,cs-wr-off-ns = <80>;
 322                 gpmc,adv-on-ns = <0>;
 323                 gpmc,adv-rd-off-ns = <60>;
 324                 gpmc,adv-wr-off-ns = <60>;
 325                 gpmc,we-on-ns = <10>;
 326                 gpmc,we-off-ns = <50>;
 327                 gpmc,oe-on-ns = <4>;
 328                 gpmc,oe-off-ns = <40>;
 329                 gpmc,access-ns = <40>;
 330                 gpmc,wr-access-ns = <80>;
 331                 gpmc,rd-cycle-ns = <80>;
 332                 gpmc,wr-cycle-ns = <80>;
 333                 gpmc,bus-turnaround-ns = <0>;
 334                 gpmc,cycle2cycle-delay-ns = <0>;
 335                 gpmc,clk-activation-ns = <0>;
 336                 gpmc,wr-data-mux-bus-ns = <0>;
 337                 /* MTD partition table */
 338                 /* All SPL-* partitions are sized to minimal length
 339                  * which can be independently programmable. For
 340                  * NAND flash this is equal to size of erase-block */
 341                 #address-cells = <1>;
 342                 #size-cells = <1>;
 343                 partition@0 {
 344                         label = "NAND.SPL";
 345                         reg = <0x00000000 0x000020000>;
 346                 };
 347                 partition@1 {
 348                         label = "NAND.SPL.backup1";
 349                         reg = <0x00020000 0x00020000>;
 350                 };
 351                 partition@2 {
 352                         label = "NAND.SPL.backup2";
 353                         reg = <0x00040000 0x00020000>;
 354                 };
 355                 partition@3 {
 356                         label = "NAND.SPL.backup3";
 357                         reg = <0x00060000 0x00020000>;
 358                 };
 359                 partition@4 {
 360                         label = "NAND.u-boot-spl-os";
 361                         reg = <0x00080000 0x00040000>;
 362                 };
 363                 partition@5 {
 364                         label = "NAND.u-boot";
 365                         reg = <0x000c0000 0x00100000>;
 366                 };
 367                 partition@6 {
 368                         label = "NAND.u-boot-env";
 369                         reg = <0x001c0000 0x00020000>;
 370                 };
 371                 partition@7 {
 372                         label = "NAND.u-boot-env.backup1";
 373                         reg = <0x001e0000 0x00020000>;
 374                 };
 375                 partition@8 {
 376                         label = "NAND.kernel";
 377                         reg = <0x00200000 0x00800000>;
 378                 };
 379                 partition@9 {
 380                         label = "NAND.file-system";
 381                         reg = <0x00a00000 0x0f600000>;
 382                 };
 383         };
 384 };
 385
 386 &omap_dwc3_1 {
 387         extcon = <&extcon_usb1>;
 388 };
 389
 390 &omap_dwc3_2 {
 391         extcon = <&extcon_usb2>;
 392 };
 393
 394 &usb1 {
 395         dr_mode = "peripheral";
 396 };
 397
 398 &usb2 {
 399         dr_mode = "host";
 400 };
 401
 402 &mmc1 {
 403         status = "okay";
 404         pinctrl-names = "default";
 405         pinctrl-0 = <&mmc1_pins_default>;
 406         vmmc-supply = <&evm_3v3_sd>;
 407         bus-width = <4>;
 408         /*
 409          * SDCD signal is not being used here - using the fact that GPIO mode
 410          * is a viable alternative
 411          */
 412         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 413         max-frequency = <192000000>;
 414 };
 415
 416 &mmc2 {
 417         /* SW5-3 in ON position */
 418         status = "okay";
 419         pinctrl-names = "default";
 420         pinctrl-0 = <&mmc2_pins_default>;
 421
 422         vmmc-supply = <&evm_3v3_sw>;
 423         bus-width = <8>;
 424         ti,non-removable;
 425         max-frequency = <192000000>;
 426 };
 427
 428 &mac {
 429         status = "okay";
 430 };
 431
 432 &dcan1 {
 433         status = "ok";
 434         pinctrl-names = "default", "sleep", "active";
 435         pinctrl-0 = <&dcan1_pins_sleep>;
 436         pinctrl-1 = <&dcan1_pins_sleep>;
 437         pinctrl-2 = <&dcan1_pins_default>;
 438 };
 439
 440 &qspi {
 441         status = "okay";
 442
 443         spi-max-frequency = <76800000>;
 444         m25p80@0 {
 445                 compatible = "s25fl256s1";
 446                 spi-max-frequency = <76800000>;
 447                 reg = <0>;
 448                 spi-tx-bus-width = <1>;
 449                 spi-rx-bus-width = <4>;
 450                 #address-cells = <1>;
 451                 #size-cells = <1>;
 452
 453                 /* MTD partition table.
 454                  * The ROM checks the first four physical blocks
 455                  * for a valid file to boot and the flash here is
 456                  * 64KiB block size.
 457                  */
 458                 partition@0 {
 459                         label = "QSPI.SPL";
 460                         reg = <0x00000000 0x000010000>;
 461                 };
 462                 partition@1 {
 463                         label = "QSPI.SPL.backup1";
 464                         reg = <0x00010000 0x00010000>;
 465                 };
 466                 partition@2 {
 467                         label = "QSPI.SPL.backup2";
 468                         reg = <0x00020000 0x00010000>;
 469                 };
 470                 partition@3 {
 471                         label = "QSPI.SPL.backup3";
 472                         reg = <0x00030000 0x00010000>;
 473                 };
 474                 partition@4 {
 475                         label = "QSPI.u-boot";
 476                         reg = <0x00040000 0x00100000>;
 477                 };
 478                 partition@5 {
 479                         label = "QSPI.u-boot-spl-os";
 480                         reg = <0x00140000 0x00080000>;
 481                 };
 482                 partition@6 {
 483                         label = "QSPI.u-boot-env";
 484                         reg = <0x001c0000 0x00010000>;
 485                 };
 486                 partition@7 {
 487                         label = "QSPI.u-boot-env.backup1";
 488                         reg = <0x001d0000 0x0010000>;
 489                 };
 490                 partition@8 {
 491                         label = "QSPI.kernel";
 492                         reg = <0x001e0000 0x0800000>;
 493                 };
 494                 partition@9 {
 495                         label = "QSPI.file-system";
 496                         reg = <0x009e0000 0x01620000>;
 497                 };
 498         };
 499 };
 500
 501 &dss {
 502         status = "ok";
 503 };
 504
 505 &hdmi {
 506         status = "ok";
 507
 508         port {
 509                 hdmi_out: endpoint {
 510                         remote-endpoint = <&tpd12s015_in>;
 511                 };
 512         };
 513 };
 514
 515 &atl {
 516         assigned-clocks = <&abe_dpll_sys_clk_mux>,
 517                           <&atl_gfclk_mux>,
 518                           <&dpll_abe_ck>,
 519                           <&dpll_abe_m2x2_ck>,
 520                           <&atl_clkin2_ck>;
 521         assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
 522         assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
 523
 524         status = "okay";
 525
 526         atl2 {
 527                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 528                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 529         };
 530 };
 531
 532 &mcasp3 {
 533         #sound-dai-cells = <0>;
 534
 535         assigned-clocks = <&mcasp3_ahclkx_mux>;
 536         assigned-clock-parents = <&atl_clkin2_ck>;
 537
 538         status = "okay";
 539
 540         op-mode = <0>;          /* MCASP_IIS_MODE */
 541         tdm-slots = <2>;
 542         /* 4 serializer */
 543         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 544                 1 2 0 0
 545         >;
 546         tx-num-evt = <32>;
 547         rx-num-evt = <32>;
 548 };
 549
 550 &mailbox5 {
 551         status = "okay";
 552         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 553                 status = "okay";
 554         };
 555         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 556                 status = "okay";
 557         };
 558 };
 559
 560 &mailbox6 {
 561         status = "okay";
 562         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 563                 status = "okay";
 564         };
 565 };