arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/bus/ti-sysc.h>
  11 #include <dt-bindings/clock/dra7.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/pinctrl/dra.h>
  14 #include <dt-bindings/clock/dra7.h>
  15
  16 #define MAX_SOURCES 400
  17
  18 / {
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         compatible = "ti,dra7xx";
  23         interrupt-parent = <&crossbar_mpu>;
  24         chosen { };
  25
  26         aliases {
  27                 i2c0 = &i2c1;
  28                 i2c1 = &i2c2;
  29                 i2c2 = &i2c3;
  30                 i2c3 = &i2c4;
  31                 i2c4 = &i2c5;
  32                 serial0 = &uart1;
  33                 serial1 = &uart2;
  34                 serial2 = &uart3;
  35                 serial3 = &uart4;
  36                 serial4 = &uart5;
  37                 serial5 = &uart6;
  38                 serial6 = &uart7;
  39                 serial7 = &uart8;
  40                 serial8 = &uart9;
  41                 serial9 = &uart10;
  42                 ethernet0 = &cpsw_emac0;
  43                 ethernet1 = &cpsw_emac1;
  44                 d_can0 = &dcan1;
  45                 d_can1 = &dcan2;
  46                 spi0 = &qspi;
  47         };
  48
  49         timer {
  50                 compatible = "arm,armv7-timer";
  51                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  52                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  53                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  54                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  55                 interrupt-parent = <&gic>;
  56         };
  57
  58         gic: interrupt-controller@48211000 {
  59                 compatible = "arm,cortex-a15-gic";
  60                 interrupt-controller;
  61                 #interrupt-cells = <3>;
  62                 reg = <0x0 0x48211000 0x0 0x1000>,
  63                       <0x0 0x48212000 0x0 0x2000>,
  64                       <0x0 0x48214000 0x0 0x2000>,
  65                       <0x0 0x48216000 0x0 0x2000>;
  66                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  67                 interrupt-parent = <&gic>;
  68         };
  69
  70         wakeupgen: interrupt-controller@48281000 {
  71                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  72                 interrupt-controller;
  73                 #interrupt-cells = <3>;
  74                 reg = <0x0 0x48281000 0x0 0x1000>;
  75                 interrupt-parent = <&gic>;
  76         };
  77
  78         cpus {
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 cpu0: cpu@0 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a15";
  85                         reg = <0>;
  86
  87                         operating-points-v2 = <&cpu0_opp_table>;
  88
  89                         clocks = <&dpll_mpu_ck>;
  90                         clock-names = "cpu";
  91
  92                         clock-latency = <300000>; /* From omap-cpufreq driver */
  93
  94                         /* cooling options */
  95                         #cooling-cells = <2>; /* min followed by max */
  96
  97                         vbb-supply = <&abb_mpu>;
  98                 };
  99         };
 100
 101         cpu0_opp_table: opp-table {
 102                 compatible = "operating-points-v2-ti-cpu";
 103                 syscon = <&scm_wkup>;
 104
 105                 opp_nom-1000000000 {
 106                         opp-hz = /bits/ 64 <1000000000>;
 107                         opp-microvolt = <1060000 850000 1150000>,
 108                                         <1060000 850000 1150000>;
 109                         opp-supported-hw = <0xFF 0x01>;
 110                         opp-suspend;
 111                 };
 112
 113                 opp_od-1176000000 {
 114                         opp-hz = /bits/ 64 <1176000000>;
 115                         opp-microvolt = <1160000 885000 1160000>,
 116                                         <1160000 885000 1160000>;
 117
 118                         opp-supported-hw = <0xFF 0x02>;
 119                 };
 120
 121                 opp_high@1500000000 {
 122                         opp-hz = /bits/ 64 <1500000000>;
 123                         opp-microvolt = <1210000 950000 1250000>,
 124                                         <1210000 950000 1250000>;
 125                         opp-supported-hw = <0xFF 0x04>;
 126                 };
 127         };
 128
 129         /*
 130          * The soc node represents the soc top level view. It is used for IPs
 131          * that are not memory mapped in the MPU view or for the MPU itself.
 132          */
 133         soc {
 134                 compatible = "ti,omap-infra";
 135                 mpu {
 136                         compatible = "ti,omap5-mpu";
 137                         ti,hwmods = "mpu";
 138                 };
 139         };
 140
 141         /*
 142          * XXX: Use a flat representation of the SOC interconnect.
 143          * The real OMAP interconnect network is quite complex.
 144          * Since it will not bring real advantage to represent that in DT for
 145          * the moment, just use a fake OCP bus entry to represent the whole bus
 146          * hierarchy.
 147          */
 148         ocp {
 149                 compatible = "ti,dra7-l3-noc", "simple-bus";
 150                 #address-cells = <1>;
 151                 #size-cells = <1>;
 152                 ranges = <0x0 0x0 0x0 0xc0000000>;
 153                 ti,hwmods = "l3_main_1", "l3_main_2";
 154                 reg = <0x0 0x44000000 0x0 0x1000000>,
 155                       <0x0 0x45000000 0x0 0x1000>;
 156                 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 157                                       <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 158
 159                 l4_cfg: interconnect@4a000000 {
 160                 };
 161                 l4_wkup: interconnect@4ae00000 {
 162                 };
 163                 l4_per1: interconnect@48000000 {
 164                 };
 165                 l4_per2: interconnect@48400000 {
 166                 };
 167                 l4_per3: interconnect@48800000 {
 168                 };
 169
 170                 axi@0 {
 171                         compatible = "simple-bus";
 172                         #size-cells = <1>;
 173                         #address-cells = <1>;
 174                         ranges = <0x51000000 0x51000000 0x3000
 175                                   0x0        0x20000000 0x10000000>;
 176                         /**
 177                          * To enable PCI endpoint mode, disable the pcie1_rc
 178                          * node and enable pcie1_ep mode.
 179                          */
 180                         pcie1_rc: pcie@51000000 {
 181                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 182                                 reg-names = "rc_dbics", "ti_conf", "config";
 183                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 184                                 #address-cells = <3>;
 185                                 #size-cells = <2>;
 186                                 device_type = "pci";
 187                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 188                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 189                                 bus-range = <0x00 0xff>;
 190                                 #interrupt-cells = <1>;
 191                                 num-lanes = <1>;
 192                                 linux,pci-domain = <0>;
 193                                 ti,hwmods = "pcie1";
 194                                 phys = <&pcie1_phy>;
 195                                 phy-names = "pcie-phy0";
 196                                 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 197                                 interrupt-map-mask = <0 0 0 7>;
 198                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 199                                                 <0 0 0 2 &pcie1_intc 2>,
 200                                                 <0 0 0 3 &pcie1_intc 3>,
 201                                                 <0 0 0 4 &pcie1_intc 4>;
 202                                 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
 203                                 status = "disabled";
 204                                 pcie1_intc: interrupt-controller {
 205                                         interrupt-controller;
 206                                         #address-cells = <0>;
 207                                         #interrupt-cells = <1>;
 208                                 };
 209                         };
 210
 211                         pcie1_ep: pcie_ep@51000000 {
 212                                 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
 213                                 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
 214                                 interrupts = <0 232 0x4>;
 215                                 num-lanes = <1>;
 216                                 num-ib-windows = <4>;
 217                                 num-ob-windows = <16>;
 218                                 ti,hwmods = "pcie1";
 219                                 phys = <&pcie1_phy>;
 220                                 phy-names = "pcie-phy0";
 221                                 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
 222                                 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
 223                                 status = "disabled";
 224                         };
 225                 };
 226
 227                 axi@1 {
 228                         compatible = "simple-bus";
 229                         #size-cells = <1>;
 230                         #address-cells = <1>;
 231                         ranges = <0x51800000 0x51800000 0x3000
 232                                   0x0        0x30000000 0x10000000>;
 233                         status = "disabled";
 234                         pcie2_rc: pcie@51800000 {
 235                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 236                                 reg-names = "rc_dbics", "ti_conf", "config";
 237                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 238                                 #address-cells = <3>;
 239                                 #size-cells = <2>;
 240                                 device_type = "pci";
 241                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 242                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 243                                 bus-range = <0x00 0xff>;
 244                                 #interrupt-cells = <1>;
 245                                 num-lanes = <1>;
 246                                 linux,pci-domain = <1>;
 247                                 ti,hwmods = "pcie2";
 248                                 phys = <&pcie2_phy>;
 249                                 phy-names = "pcie-phy0";
 250                                 interrupt-map-mask = <0 0 0 7>;
 251                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 252                                                 <0 0 0 2 &pcie2_intc 2>,
 253                                                 <0 0 0 3 &pcie2_intc 3>,
 254                                                 <0 0 0 4 &pcie2_intc 4>;
 255                                 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
 256                                 pcie2_intc: interrupt-controller {
 257                                         interrupt-controller;
 258                                         #address-cells = <0>;
 259                                         #interrupt-cells = <1>;
 260                                 };
 261                         };
 262                 };
 263
 264                 ocmcram1: ocmcram@40300000 {
 265                         compatible = "mmio-sram";
 266                         reg = <0x40300000 0x80000>;
 267                         ranges = <0x0 0x40300000 0x80000>;
 268                         #address-cells = <1>;
 269                         #size-cells = <1>;
 270                         /*
 271                          * This is a placeholder for an optional reserved
 272                          * region for use by secure software. The size
 273                          * of this region is not known until runtime so it
 274                          * is set as zero to either be updated to reserve
 275                          * space or left unchanged to leave all SRAM for use.
 276                          * On HS parts that that require the reserved region
 277                          * either the bootloader can update the size to
 278                          * the required amount or the node can be overridden
 279                          * from the board dts file for the secure platform.
 280                          */
 281                         sram-hs@0 {
 282                                 compatible = "ti,secure-ram";
 283                                 reg = <0x0 0x0>;
 284                         };
 285                 };
 286
 287                 /*
 288                  * NOTE: ocmcram2 and ocmcram3 are not available on all
 289                  * DRA7xx and AM57xx variants. Confirm availability in
 290                  * the data manual for the exact part number in use
 291                  * before enabling these nodes in the board dts file.
 292                  */
 293                 ocmcram2: ocmcram@40400000 {
 294                         status = "disabled";
 295                         compatible = "mmio-sram";
 296                         reg = <0x40400000 0x100000>;
 297                         ranges = <0x0 0x40400000 0x100000>;
 298                         #address-cells = <1>;
 299                         #size-cells = <1>;
 300                 };
 301
 302                 ocmcram3: ocmcram@40500000 {
 303                         status = "disabled";
 304                         compatible = "mmio-sram";
 305                         reg = <0x40500000 0x100000>;
 306                         ranges = <0x0 0x40500000 0x100000>;
 307                         #address-cells = <1>;
 308                         #size-cells = <1>;
 309                 };
 310
 311                 bandgap: bandgap@4a0021e0 {
 312                         reg = <0x4a0021e0 0xc
 313                                 0x4a00232c 0xc
 314                                 0x4a002380 0x2c
 315                                 0x4a0023C0 0x3c
 316                                 0x4a002564 0x8
 317                                 0x4a002574 0x50>;
 318                                 compatible = "ti,dra752-bandgap";
 319                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 320                                 #thermal-sensor-cells = <1>;
 321                 };
 322
 323                 dsp1_system: dsp_system@40d00000 {
 324                         compatible = "syscon";
 325                         reg = <0x40d00000 0x100>;
 326                 };
 327
 328                 dra7_iodelay_core: padconf@4844a000 {
 329                         compatible = "ti,dra7-iodelay";
 330                         reg = <0x4844a000 0x0d1c>;
 331                         #address-cells = <1>;
 332                         #size-cells = <0>;
 333                         #pinctrl-cells = <2>;
 334                 };
 335
 336                 edma: edma@43300000 {
 337                         compatible = "ti,edma3-tpcc";
 338                         ti,hwmods = "tpcc";
 339                         reg = <0x43300000 0x100000>;
 340                         reg-names = "edma3_cc";
 341                         interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 342                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 343                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 344                         interrupt-names = "edma3_ccint", "edma3_mperr",
 345                                           "edma3_ccerrint";
 346                         dma-requests = <64>;
 347                         #dma-cells = <2>;
 348
 349                         ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
 350
 351                         /*
 352                          * memcpy is disabled, can be enabled with:
 353                          * ti,edma-memcpy-channels = <20 21>;
 354                          * for example. Note that these channels need to be
 355                          * masked in the xbar as well.
 356                          */
 357                 };
 358
 359                 edma_tptc0: tptc@43400000 {
 360                         compatible = "ti,edma3-tptc";
 361                         ti,hwmods = "tptc0";
 362                         reg =   <0x43400000 0x100000>;
 363                         interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
 364                         interrupt-names = "edma3_tcerrint";
 365                 };
 366
 367                 edma_tptc1: tptc@43500000 {
 368                         compatible = "ti,edma3-tptc";
 369                         ti,hwmods = "tptc1";
 370                         reg =   <0x43500000 0x100000>;
 371                         interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 372                         interrupt-names = "edma3_tcerrint";
 373                 };
 374
 375                 dmm@4e000000 {
 376                         compatible = "ti,omap5-dmm";
 377                         reg = <0x4e000000 0x800>;
 378                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 379                         ti,hwmods = "dmm";
 380                 };
 381
 382                 mmu0_dsp1: mmu@40d01000 {
 383                         compatible = "ti,dra7-dsp-iommu";
 384                         reg = <0x40d01000 0x100>;
 385                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 386                         ti,hwmods = "mmu0_dsp1";
 387                         #iommu-cells = <0>;
 388                         ti,syscon-mmuconfig = <&dsp1_system 0x0>;
 389                         status = "disabled";
 390                 };
 391
 392                 mmu1_dsp1: mmu@40d02000 {
 393                         compatible = "ti,dra7-dsp-iommu";
 394                         reg = <0x40d02000 0x100>;
 395                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 396                         ti,hwmods = "mmu1_dsp1";
 397                         #iommu-cells = <0>;
 398                         ti,syscon-mmuconfig = <&dsp1_system 0x1>;
 399                         status = "disabled";
 400                 };
 401
 402                 mmu_ipu1: mmu@58882000 {
 403                         compatible = "ti,dra7-iommu";
 404                         reg = <0x58882000 0x100>;
 405                         interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
 406                         ti,hwmods = "mmu_ipu1";
 407                         #iommu-cells = <0>;
 408                         ti,iommu-bus-err-back;
 409                         status = "disabled";
 410                 };
 411
 412                 mmu_ipu2: mmu@55082000 {
 413                         compatible = "ti,dra7-iommu";
 414                         reg = <0x55082000 0x100>;
 415                         interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
 416                         ti,hwmods = "mmu_ipu2";
 417                         #iommu-cells = <0>;
 418                         ti,iommu-bus-err-back;
 419                         status = "disabled";
 420                 };
 421
 422                 abb_mpu: regulator-abb-mpu {
 423                         compatible = "ti,abb-v3";
 424                         regulator-name = "abb_mpu";
 425                         #address-cells = <0>;
 426                         #size-cells = <0>;
 427                         clocks = <&sys_clkin1>;
 428                         ti,settling-time = <50>;
 429                         ti,clock-cycles = <16>;
 430
 431                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
 432                               <0x4ae06014 0x4>, <0x4a003b20 0xc>,
 433                               <0x4ae0c158 0x4>;
 434                         reg-names = "setup-address", "control-address",
 435                                     "int-address", "efuse-address",
 436                                     "ldo-address";
 437                         ti,tranxdone-status-mask = <0x80>;
 438                         /* LDOVBBMPU_FBB_MUX_CTRL */
 439                         ti,ldovbb-override-mask = <0x400>;
 440                         /* LDOVBBMPU_FBB_VSET_OUT */
 441                         ti,ldovbb-vset-mask = <0x1F>;
 442
 443                         /*
 444                          * NOTE: only FBB mode used but actual vset will
 445                          * determine final biasing
 446                          */
 447                         ti,abb_info = <
 448                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 449                         1060000         0       0x0     0 0x02000000 0x01F00000
 450                         1160000         0       0x4     0 0x02000000 0x01F00000
 451                         1210000         0       0x8     0 0x02000000 0x01F00000
 452                         >;
 453                 };
 454
 455                 abb_ivahd: regulator-abb-ivahd {
 456                         compatible = "ti,abb-v3";
 457                         regulator-name = "abb_ivahd";
 458                         #address-cells = <0>;
 459                         #size-cells = <0>;
 460                         clocks = <&sys_clkin1>;
 461                         ti,settling-time = <50>;
 462                         ti,clock-cycles = <16>;
 463
 464                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
 465                               <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
 466                               <0x4a002470 0x4>;
 467                         reg-names = "setup-address", "control-address",
 468                                     "int-address", "efuse-address",
 469                                     "ldo-address";
 470                         ti,tranxdone-status-mask = <0x40000000>;
 471                         /* LDOVBBIVA_FBB_MUX_CTRL */
 472                         ti,ldovbb-override-mask = <0x400>;
 473                         /* LDOVBBIVA_FBB_VSET_OUT */
 474                         ti,ldovbb-vset-mask = <0x1F>;
 475
 476                         /*
 477                          * NOTE: only FBB mode used but actual vset will
 478                          * determine final biasing
 479                          */
 480                         ti,abb_info = <
 481                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 482                         1055000         0       0x0     0 0x02000000 0x01F00000
 483                         1150000         0       0x4     0 0x02000000 0x01F00000
 484                         1250000         0       0x8     0 0x02000000 0x01F00000
 485                         >;
 486                 };
 487
 488                 abb_dspeve: regulator-abb-dspeve {
 489                         compatible = "ti,abb-v3";
 490                         regulator-name = "abb_dspeve";
 491                         #address-cells = <0>;
 492                         #size-cells = <0>;
 493                         clocks = <&sys_clkin1>;
 494                         ti,settling-time = <50>;
 495                         ti,clock-cycles = <16>;
 496
 497                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
 498                               <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
 499                               <0x4a00246c 0x4>;
 500                         reg-names = "setup-address", "control-address",
 501                                     "int-address", "efuse-address",
 502                                     "ldo-address";
 503                         ti,tranxdone-status-mask = <0x20000000>;
 504                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
 505                         ti,ldovbb-override-mask = <0x400>;
 506                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
 507                         ti,ldovbb-vset-mask = <0x1F>;
 508
 509                         /*
 510                          * NOTE: only FBB mode used but actual vset will
 511                          * determine final biasing
 512                          */
 513                         ti,abb_info = <
 514                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 515                         1055000         0       0x0     0 0x02000000 0x01F00000
 516                         1150000         0       0x4     0 0x02000000 0x01F00000
 517                         1250000         0       0x8     0 0x02000000 0x01F00000
 518                         >;
 519                 };
 520
 521                 abb_gpu: regulator-abb-gpu {
 522                         compatible = "ti,abb-v3";
 523                         regulator-name = "abb_gpu";
 524                         #address-cells = <0>;
 525                         #size-cells = <0>;
 526                         clocks = <&sys_clkin1>;
 527                         ti,settling-time = <50>;
 528                         ti,clock-cycles = <16>;
 529
 530                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
 531                               <0x4ae06010 0x4>, <0x4a003b08 0xc>,
 532                               <0x4ae0c154 0x4>;
 533                         reg-names = "setup-address", "control-address",
 534                                     "int-address", "efuse-address",
 535                                     "ldo-address";
 536                         ti,tranxdone-status-mask = <0x10000000>;
 537                         /* LDOVBBGPU_FBB_MUX_CTRL */
 538                         ti,ldovbb-override-mask = <0x400>;
 539                         /* LDOVBBGPU_FBB_VSET_OUT */
 540                         ti,ldovbb-vset-mask = <0x1F>;
 541
 542                         /*
 543                          * NOTE: only FBB mode used but actual vset will
 544                          * determine final biasing
 545                          */
 546                         ti,abb_info = <
 547                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
 548                         1090000         0       0x0     0 0x02000000 0x01F00000
 549                         1210000         0       0x4     0 0x02000000 0x01F00000
 550                         1280000         0       0x8     0 0x02000000 0x01F00000
 551                         >;
 552                 };
 553
 554                 qspi: spi@4b300000 {
 555                         compatible = "ti,dra7xxx-qspi";
 556                         reg = <0x4b300000 0x100>,
 557                               <0x5c000000 0x4000000>;
 558                         reg-names = "qspi_base", "qspi_mmap";
 559                         syscon-chipselects = <&scm_conf 0x558>;
 560                         #address-cells = <1>;
 561                         #size-cells = <0>;
 562                         ti,hwmods = "qspi";
 563                         clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
 564                         clock-names = "fck";
 565                         num-cs = <4>;
 566                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
 567                         status = "disabled";
 568                 };
 569
 570                 /* OCP2SCP3 */
 571                 sata: sata@4a141100 {
 572                         compatible = "snps,dwc-ahci";
 573                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 574                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 575                         phys = <&sata_phy>;
 576                         phy-names = "sata-phy";
 577                         clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
 578                         ti,hwmods = "sata";
 579                         ports-implemented = <0x1>;
 580                 };
 581
 582                 /* OCP2SCP1 */
 583                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
 584                 gpmc: gpmc@50000000 {
 585                         compatible = "ti,am3352-gpmc";
 586                         ti,hwmods = "gpmc";
 587                         reg = <0x50000000 0x37c>;      /* device IO registers */
 588                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 589                         dmas = <&edma_xbar 4 0>;
 590                         dma-names = "rxtx";
 591                         gpmc,num-cs = <8>;
 592                         gpmc,num-waitpins = <2>;
 593                         #address-cells = <2>;
 594                         #size-cells = <1>;
 595                         interrupt-controller;
 596                         #interrupt-cells = <2>;
 597                         gpio-controller;
 598                         #gpio-cells = <2>;
 599                         status = "disabled";
 600                 };
 601
 602                 crossbar_mpu: crossbar@4a002a48 {
 603                         compatible = "ti,irq-crossbar";
 604                         reg = <0x4a002a48 0x130>;
 605                         interrupt-controller;
 606                         interrupt-parent = <&wakeupgen>;
 607                         #interrupt-cells = <3>;
 608                         ti,max-irqs = <160>;
 609                         ti,max-crossbar-sources = <MAX_SOURCES>;
 610                         ti,reg-size = <2>;
 611                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
 612                         ti,irqs-skip = <10 133 139 140>;
 613                         ti,irqs-safe-map = <0>;
 614                 };
 615
 616                 dss: dss@58000000 {
 617                         compatible = "ti,dra7-dss";
 618                         /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
 619                         /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
 620                         status = "disabled";
 621                         ti,hwmods = "dss_core";
 622                         /* CTRL_CORE_DSS_PLL_CONTROL */
 623                         syscon-pll-ctrl = <&scm_conf 0x538>;
 624                         #address-cells = <1>;
 625                         #size-cells = <1>;
 626                         ranges;
 627
 628                         dispc@58001000 {
 629                                 compatible = "ti,dra7-dispc";
 630                                 reg = <0x58001000 0x1000>;
 631                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 632                                 ti,hwmods = "dss_dispc";
 633                                 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
 634                                 clock-names = "fck";
 635                                 /* CTRL_CORE_SMA_SW_1 */
 636                                 syscon-pol = <&scm_conf 0x534>;
 637                         };
 638
 639                         hdmi: encoder@58060000 {
 640                                 compatible = "ti,dra7-hdmi";
 641                                 reg = <0x58040000 0x200>,
 642                                       <0x58040200 0x80>,
 643                                       <0x58040300 0x80>,
 644                                       <0x58060000 0x19000>;
 645                                 reg-names = "wp", "pll", "phy", "core";
 646                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 647                                 status = "disabled";
 648                                 ti,hwmods = "dss_hdmi";
 649                                 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
 650                                          <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
 651                                 clock-names = "fck", "sys_clk";
 652                                 dmas = <&sdma_xbar 76>;
 653                                 dma-names = "audio_tx";
 654                         };
 655                 };
 656
 657                 aes1: aes@4b500000 {
 658                         compatible = "ti,omap4-aes";
 659                         ti,hwmods = "aes1";
 660                         reg = <0x4b500000 0xa0>;
 661                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 662                         dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
 663                         dma-names = "tx", "rx";
 664                         clocks = <&l3_iclk_div>;
 665                         clock-names = "fck";
 666                 };
 667
 668                 aes2: aes@4b700000 {
 669                         compatible = "ti,omap4-aes";
 670                         ti,hwmods = "aes2";
 671                         reg = <0x4b700000 0xa0>;
 672                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 673                         dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
 674                         dma-names = "tx", "rx";
 675                         clocks = <&l3_iclk_div>;
 676                         clock-names = "fck";
 677                 };
 678
 679                 des: des@480a5000 {
 680                         compatible = "ti,omap4-des";
 681                         ti,hwmods = "des";
 682                         reg = <0x480a5000 0xa0>;
 683                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 684                         dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
 685                         dma-names = "tx", "rx";
 686                         clocks = <&l3_iclk_div>;
 687                         clock-names = "fck";
 688                 };
 689
 690                 sham: sham@53100000 {
 691                         compatible = "ti,omap5-sham";
 692                         ti,hwmods = "sham";
 693                         reg = <0x4b101000 0x300>;
 694                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 695                         dmas = <&edma_xbar 119 0>;
 696                         dma-names = "rx";
 697                         clocks = <&l3_iclk_div>;
 698                         clock-names = "fck";
 699                 };
 700
 701                 opp_supply_mpu: opp-supply@4a003b20 {
 702                         compatible = "ti,omap5-opp-supply";
 703                         reg = <0x4a003b20 0xc>;
 704                         ti,efuse-settings = <
 705                         /* uV   offset */
 706                         1060000 0x0
 707                         1160000 0x4
 708                         1210000 0x8
 709                         >;
 710                         ti,absolute-max-voltage-uv = <1500000>;
 711                 };
 712
 713         };
 714
 715         thermal_zones: thermal-zones {
 716                 #include "omap4-cpu-thermal.dtsi"
 717                 #include "omap5-gpu-thermal.dtsi"
 718                 #include "omap5-core-thermal.dtsi"
 719                 #include "dra7-dspeve-thermal.dtsi"
 720                 #include "dra7-iva-thermal.dtsi"
 721         };
 722
 723 };
 724
 725 &cpu_thermal {
 726         polling-delay = <500>; /* milliseconds */
 727         coefficients = <0 2000>;
 728 };
 729
 730 &gpu_thermal {
 731         coefficients = <0 2000>;
 732 };
 733
 734 &core_thermal {
 735         coefficients = <0 2000>;
 736 };
 737
 738 &dspeve_thermal {
 739         coefficients = <0 2000>;
 740 };
 741
 742 &iva_thermal {
 743         coefficients = <0 2000>;
 744 };
 745
 746 &cpu_crit {
 747         temperature = <120000>; /* milli Celsius */
 748 };
 749
 750 &core_crit {
 751         temperature = <120000>; /* milli Celsius */
 752 };
 753
 754 &gpu_crit {
 755         temperature = <120000>; /* milli Celsius */
 756 };
 757
 758 &dspeve_crit {
 759         temperature = <120000>; /* milli Celsius */
 760 };
 761
 762 &iva_crit {
 763         temperature = <120000>; /* milli Celsius */
 764 };
 765
 766 #include "dra7-l4.dtsi"
 767 #include "dra7xx-clocks.dtsi"