arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/arm-gic.h>
  11 #include <dt-bindings/pinctrl/dra.h>
  12
  13 #define MAX_SOURCES 400
  14
  15 / {
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         compatible = "ti,dra7xx";
  20         interrupt-parent = <&crossbar_mpu>;
  21
  22         aliases {
  23                 i2c0 = &i2c1;
  24                 i2c1 = &i2c2;
  25                 i2c2 = &i2c3;
  26                 i2c3 = &i2c4;
  27                 i2c4 = &i2c5;
  28                 serial0 = &uart1;
  29                 serial1 = &uart2;
  30                 serial2 = &uart3;
  31                 serial3 = &uart4;
  32                 serial4 = &uart5;
  33                 serial5 = &uart6;
  34                 serial6 = &uart7;
  35                 serial7 = &uart8;
  36                 serial8 = &uart9;
  37                 serial9 = &uart10;
  38                 ethernet0 = &cpsw_emac0;
  39                 ethernet1 = &cpsw_emac1;
  40                 d_can0 = &dcan1;
  41                 d_can1 = &dcan2;
  42                 spi0 = &qspi;
  43         };
  44
  45         timer {
  46                 compatible = "arm,armv7-timer";
  47                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  48                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  49                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  50                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  51                 interrupt-parent = <&gic>;
  52         };
  53
  54         gic: interrupt-controller@48211000 {
  55                 compatible = "arm,cortex-a15-gic";
  56                 interrupt-controller;
  57                 #interrupt-cells = <3>;
  58                 reg = <0x0 0x48211000 0x0 0x1000>,
  59                       <0x0 0x48212000 0x0 0x1000>,
  60                       <0x0 0x48214000 0x0 0x2000>,
  61                       <0x0 0x48216000 0x0 0x2000>;
  62                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  63                 interrupt-parent = <&gic>;
  64         };
  65
  66         wakeupgen: interrupt-controller@48281000 {
  67                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  68                 interrupt-controller;
  69                 #interrupt-cells = <3>;
  70                 reg = <0x0 0x48281000 0x0 0x1000>;
  71                 interrupt-parent = <&gic>;
  72         };
  73
  74         cpus {
  75                 #address-cells = <1>;
  76                 #size-cells = <0>;
  77
  78                 cpu0: cpu@0 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a15";
  81                         reg = <0>;
  82
  83                         operating-points = <
  84                                 /* kHz    uV */
  85                                 1000000 1060000
  86                                 1176000 1160000
  87                                 >;
  88
  89                         clocks = <&dpll_mpu_ck>;
  90                         clock-names = "cpu";
  91
  92                         clock-latency = <300000>; /* From omap-cpufreq driver */
  93
  94                         /* cooling options */
  95                         cooling-min-level = <0>;
  96                         cooling-max-level = <2>;
  97                         #cooling-cells = <2>; /* min followed by max */
  98                 };
  99         };
 100
 101         /*
 102          * The soc node represents the soc top level view. It is used for IPs
 103          * that are not memory mapped in the MPU view or for the MPU itself.
 104          */
 105         soc {
 106                 compatible = "ti,omap-infra";
 107                 mpu {
 108                         compatible = "ti,omap5-mpu";
 109                         ti,hwmods = "mpu";
 110                 };
 111         };
 112
 113         /*
 114          * XXX: Use a flat representation of the SOC interconnect.
 115          * The real OMAP interconnect network is quite complex.
 116          * Since it will not bring real advantage to represent that in DT for
 117          * the moment, just use a fake OCP bus entry to represent the whole bus
 118          * hierarchy.
 119          */
 120         ocp {
 121                 compatible = "ti,dra7-l3-noc", "simple-bus";
 122                 #address-cells = <1>;
 123                 #size-cells = <1>;
 124                 ranges = <0x0 0x0 0x0 0xc0000000>;
 125                 ti,hwmods = "l3_main_1", "l3_main_2";
 126                 reg = <0x0 0x44000000 0x0 0x1000000>,
 127                       <0x0 0x45000000 0x0 0x1000>;
 128                 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 129                                       <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 130
 131                 l4_cfg: l4@4a000000 {
 132                         compatible = "ti,dra7-l4-cfg", "simple-bus";
 133                         #address-cells = <1>;
 134                         #size-cells = <1>;
 135                         ranges = <0 0x4a000000 0x22c000>;
 136
 137                         scm: scm@2000 {
 138                                 compatible = "ti,dra7-scm-core", "simple-bus";
 139                                 reg = <0x2000 0x2000>;
 140                                 #address-cells = <1>;
 141                                 #size-cells = <1>;
 142                                 ranges = <0 0x2000 0x2000>;
 143
 144                                 scm_conf: scm_conf@0 {
 145                                         compatible = "syscon", "simple-bus";
 146                                         reg = <0x0 0x1400>;
 147                                         #address-cells = <1>;
 148                                         #size-cells = <1>;
 149                                         ranges = <0 0x0 0x1400>;
 150
 151                                         pbias_regulator: pbias_regulator@e00 {
 152                                                 compatible = "ti,pbias-dra7", "ti,pbias-omap";
 153                                                 reg = <0xe00 0x4>;
 154                                                 syscon = <&scm_conf>;
 155                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 156                                                         regulator-name = "pbias_mmc_omap5";
 157                                                         regulator-min-microvolt = <1800000>;
 158                                                         regulator-max-microvolt = <3000000>;
 159                                                 };
 160                                         };
 161
 162                                         scm_conf_clocks: clocks {
 163                                                 #address-cells = <1>;
 164                                                 #size-cells = <0>;
 165                                         };
 166                                 };
 167
 168                                 dra7_pmx_core: pinmux@1400 {
 169                                         compatible = "ti,dra7-padconf",
 170                                                      "pinctrl-single";
 171                                         reg = <0x1400 0x0468>;
 172                                         #address-cells = <1>;
 173                                         #size-cells = <0>;
 174                                         #pinctrl-cells = <1>;
 175                                         #interrupt-cells = <1>;
 176                                         interrupt-controller;
 177                                         pinctrl-single,register-width = <32>;
 178                                         pinctrl-single,function-mask = <0x3fffffff>;
 179                                 };
 180
 181                                 scm_conf1: scm_conf@1c04 {
 182                                         compatible = "syscon";
 183                                         reg = <0x1c04 0x0020>;
 184                                 };
 185
 186                                 scm_conf_pcie: scm_conf@1c24 {
 187                                         compatible = "syscon";
 188                                         reg = <0x1c24 0x0024>;
 189                                 };
 190
 191                                 sdma_xbar: dma-router@b78 {
 192                                         compatible = "ti,dra7-dma-crossbar";
 193                                         reg = <0xb78 0xfc>;
 194                                         #dma-cells = <1>;
 195                                         dma-requests = <205>;
 196                                         ti,dma-safe-map = <0>;
 197                                         dma-masters = <&sdma>;
 198                                 };
 199
 200                                 edma_xbar: dma-router@c78 {
 201                                         compatible = "ti,dra7-dma-crossbar";
 202                                         reg = <0xc78 0x7c>;
 203                                         #dma-cells = <2>;
 204                                         dma-requests = <204>;
 205                                         ti,dma-safe-map = <0>;
 206                                         dma-masters = <&edma>;
 207                                 };
 208                         };
 209
 210                         cm_core_aon: cm_core_aon@5000 {
 211                                 compatible = "ti,dra7-cm-core-aon";
 212                                 reg = <0x5000 0x2000>;
 213
 214                                 cm_core_aon_clocks: clocks {
 215                                         #address-cells = <1>;
 216                                         #size-cells = <0>;
 217                                 };
 218
 219                                 cm_core_aon_clockdomains: clockdomains {
 220                                 };
 221                         };
 222
 223                         cm_core: cm_core@8000 {
 224                                 compatible = "ti,dra7-cm-core";
 225                                 reg = <0x8000 0x3000>;
 226
 227                                 cm_core_clocks: clocks {
 228                                         #address-cells = <1>;
 229                                         #size-cells = <0>;
 230                                 };
 231
 232                                 cm_core_clockdomains: clockdomains {
 233                                 };
 234                         };
 235                 };
 236
 237                 l4_wkup: l4@4ae00000 {
 238                         compatible = "ti,dra7-l4-wkup", "simple-bus";
 239                         #address-cells = <1>;
 240                         #size-cells = <1>;
 241                         ranges = <0 0x4ae00000 0x3f000>;
 242
 243                         counter32k: counter@4000 {
 244                                 compatible = "ti,omap-counter32k";
 245                                 reg = <0x4000 0x40>;
 246                                 ti,hwmods = "counter_32k";
 247                         };
 248
 249                         prm: prm@6000 {
 250                                 compatible = "ti,dra7-prm";
 251                                 reg = <0x6000 0x3000>;
 252                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 253
 254                                 prm_clocks: clocks {
 255                                         #address-cells = <1>;
 256                                         #size-cells = <0>;
 257                                 };
 258
 259                                 prm_clockdomains: clockdomains {
 260                                 };
 261                         };
 262
 263                         scm_wkup: scm_conf@c000 {
 264                                 compatible = "syscon";
 265                                 reg = <0xc000 0x1000>;
 266                         };
 267                 };
 268
 269                 axi@0 {
 270                         compatible = "simple-bus";
 271                         #size-cells = <1>;
 272                         #address-cells = <1>;
 273                         ranges = <0x51000000 0x51000000 0x3000
 274                                   0x0        0x20000000 0x10000000>;
 275                         pcie1: pcie@51000000 {
 276                                 compatible = "ti,dra7-pcie";
 277                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 278                                 reg-names = "rc_dbics", "ti_conf", "config";
 279                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 280                                 #address-cells = <3>;
 281                                 #size-cells = <2>;
 282                                 device_type = "pci";
 283                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 284                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 285                                 #interrupt-cells = <1>;
 286                                 num-lanes = <1>;
 287                                 linux,pci-domain = <0>;
 288                                 ti,hwmods = "pcie1";
 289                                 phys = <&pcie1_phy>;
 290                                 phy-names = "pcie-phy0";
 291                                 interrupt-map-mask = <0 0 0 7>;
 292                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 293                                                 <0 0 0 2 &pcie1_intc 2>,
 294                                                 <0 0 0 3 &pcie1_intc 3>,
 295                                                 <0 0 0 4 &pcie1_intc 4>;
 296                                 pcie1_intc: interrupt-controller {
 297                                         interrupt-controller;
 298                                         #address-cells = <0>;
 299                                         #interrupt-cells = <1>;
 300                                 };
 301                         };
 302                 };
 303
 304                 axi@1 {
 305                         compatible = "simple-bus";
 306                         #size-cells = <1>;
 307                         #address-cells = <1>;
 308                         ranges = <0x51800000 0x51800000 0x3000
 309                                   0x0        0x30000000 0x10000000>;
 310                         status = "disabled";
 311                         pcie@51800000 {
 312                                 compatible = "ti,dra7-pcie";
 313                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 314                                 reg-names = "rc_dbics", "ti_conf", "config";
 315                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 316                                 #address-cells = <3>;
 317                                 #size-cells = <2>;
 318                                 device_type = "pci";
 319                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 320                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 321                                 #interrupt-cells = <1>;
 322                                 num-lanes = <1>;
 323                                 linux,pci-domain = <1>;
 324                                 ti,hwmods = "pcie2";
 325                                 phys = <&pcie2_phy>;
 326                                 phy-names = "pcie-phy0";
 327                                 interrupt-map-mask = <0 0 0 7>;
 328                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 329                                                 <0 0 0 2 &pcie2_intc 2>,
 330                                                 <0 0 0 3 &pcie2_intc 3>,
 331                                                 <0 0 0 4 &pcie2_intc 4>;
 332                                 pcie2_intc: interrupt-controller {
 333                                         interrupt-controller;
 334                                         #address-cells = <0>;
 335                                         #interrupt-cells = <1>;
 336                                 };
 337                         };
 338                 };
 339
 340                 ocmcram1: ocmcram@40300000 {
 341                         compatible = "mmio-sram";
 342                         reg = <0x40300000 0x80000>;
 343                         ranges = <0x0 0x40300000 0x80000>;
 344                         #address-cells = <1>;
 345                         #size-cells = <1>;
 346                         /*
 347                          * This is a placeholder for an optional reserved
 348                          * region for use by secure software. The size
 349                          * of this region is not known until runtime so it
 350                          * is set as zero to either be updated to reserve
 351                          * space or left unchanged to leave all SRAM for use.
 352                          * On HS parts that that require the reserved region
 353                          * either the bootloader can update the size to
 354                          * the required amount or the node can be overridden
 355                          * from the board dts file for the secure platform.
 356                          */
 357                         sram-hs@0 {
 358                                 compatible = "ti,secure-ram";
 359                                 reg = <0x0 0x0>;
 360                         };
 361                 };
 362
 363                 /*
 364                  * NOTE: ocmcram2 and ocmcram3 are not available on all
 365                  * DRA7xx and AM57xx variants. Confirm availability in
 366                  * the data manual for the exact part number in use
 367                  * before enabling these nodes in the board dts file.
 368                  */
 369                 ocmcram2: ocmcram@40400000 {
 370                         status = "disabled";
 371                         compatible = "mmio-sram";
 372                         reg = <0x40400000 0x100000>;
 373                         ranges = <0x0 0x40400000 0x100000>;
 374                         #address-cells = <1>;
 375                         #size-cells = <1>;
 376                 };
 377
 378                 ocmcram3: ocmcram@40500000 {
 379                         status = "disabled";
 380                         compatible = "mmio-sram";
 381                         reg = <0x40500000 0x100000>;
 382                         ranges = <0x0 0x40500000 0x100000>;
 383                         #address-cells = <1>;
 384                         #size-cells = <1>;
 385                 };
 386
 387                 bandgap: bandgap@4a0021e0 {
 388                         reg = <0x4a0021e0 0xc
 389                                 0x4a00232c 0xc
 390                                 0x4a002380 0x2c
 391                                 0x4a0023C0 0x3c
 392                                 0x4a002564 0x8
 393                                 0x4a002574 0x50>;
 394                                 compatible = "ti,dra752-bandgap";
 395                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 396                                 #thermal-sensor-cells = <1>;
 397                 };
 398
 399                 dsp1_system: dsp_system@40d00000 {
 400                         compatible = "syscon";
 401                         reg = <0x40d00000 0x100>;
 402                 };
 403
 404                 sdma: dma-controller@4a056000 {
 405                         compatible = "ti,omap4430-sdma";
 406                         reg = <0x4a056000 0x1000>;
 407                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 408                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 409                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 410                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 411                         #dma-cells = <1>;
 412                         dma-channels = <32>;
 413                         dma-requests = <127>;
 414                 };
 415
 416                 edma: edma@43300000 {
 417                         compatible = "ti,edma3-tpcc";
 418                         ti,hwmods = "tpcc";
 419                         reg = <0x43300000 0x100000>;
 420                         reg-names = "edma3_cc";
 421                         interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 422                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 423                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 424                         interrupt-names = "edma3_ccint", "edma3_mperr",
 425                                           "edma3_ccerrint";
 426                         dma-requests = <64>;
 427                         #dma-cells = <2>;
 428
 429                         ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
 430
 431                         /*
 432                          * memcpy is disabled, can be enabled with:
 433                          * ti,edma-memcpy-channels = <20 21>;
 434                          * for example. Note that these channels need to be
 435                          * masked in the xbar as well.
 436                          */
 437                 };
 438
 439                 edma_tptc0: tptc@43400000 {
 440                         compatible = "ti,edma3-tptc";
 441                         ti,hwmods = "tptc0";
 442                         reg =   <0x43400000 0x100000>;
 443                         interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
 444                         interrupt-names = "edma3_tcerrint";
 445                 };
 446
 447                 edma_tptc1: tptc@43500000 {
 448                         compatible = "ti,edma3-tptc";
 449                         ti,hwmods = "tptc1";
 450                         reg =   <0x43500000 0x100000>;
 451                         interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 452                         interrupt-names = "edma3_tcerrint";
 453                 };
 454
 455                 gpio1: gpio@4ae10000 {
 456                         compatible = "ti,omap4-gpio";
 457                         reg = <0x4ae10000 0x200>;
 458                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 459                         ti,hwmods = "gpio1";
 460                         gpio-controller;
 461                         #gpio-cells = <2>;
 462                         interrupt-controller;
 463                         #interrupt-cells = <2>;
 464                 };
 465
 466                 gpio2: gpio@48055000 {
 467                         compatible = "ti,omap4-gpio";
 468                         reg = <0x48055000 0x200>;
 469                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 470                         ti,hwmods = "gpio2";
 471                         gpio-controller;
 472                         #gpio-cells = <2>;
 473                         interrupt-controller;
 474                         #interrupt-cells = <2>;
 475                 };
 476
 477                 gpio3: gpio@48057000 {
 478                         compatible = "ti,omap4-gpio";
 479                         reg = <0x48057000 0x200>;
 480                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 481                         ti,hwmods = "gpio3";
 482                         gpio-controller;
 483                         #gpio-cells = <2>;
 484                         interrupt-controller;
 485                         #interrupt-cells = <2>;
 486                 };
 487
 488                 gpio4: gpio@48059000 {
 489                         compatible = "ti,omap4-gpio";
 490                         reg = <0x48059000 0x200>;
 491                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 492                         ti,hwmods = "gpio4";
 493                         gpio-controller;
 494                         #gpio-cells = <2>;
 495                         interrupt-controller;
 496                         #interrupt-cells = <2>;
 497                 };
 498
 499                 gpio5: gpio@4805b000 {
 500                         compatible = "ti,omap4-gpio";
 501                         reg = <0x4805b000 0x200>;
 502                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 503                         ti,hwmods = "gpio5";
 504                         gpio-controller;
 505                         #gpio-cells = <2>;
 506                         interrupt-controller;
 507                         #interrupt-cells = <2>;
 508                 };
 509
 510                 gpio6: gpio@4805d000 {
 511                         compatible = "ti,omap4-gpio";
 512                         reg = <0x4805d000 0x200>;
 513                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 514                         ti,hwmods = "gpio6";
 515                         gpio-controller;
 516                         #gpio-cells = <2>;
 517                         interrupt-controller;
 518                         #interrupt-cells = <2>;
 519                 };
 520
 521                 gpio7: gpio@48051000 {
 522                         compatible = "ti,omap4-gpio";
 523                         reg = <0x48051000 0x200>;
 524                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 525                         ti,hwmods = "gpio7";
 526                         gpio-controller;
 527                         #gpio-cells = <2>;
 528                         interrupt-controller;
 529                         #interrupt-cells = <2>;
 530                 };
 531
 532                 gpio8: gpio@48053000 {
 533                         compatible = "ti,omap4-gpio";
 534                         reg = <0x48053000 0x200>;
 535                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 536                         ti,hwmods = "gpio8";
 537                         gpio-controller;
 538                         #gpio-cells = <2>;
 539                         interrupt-controller;
 540                         #interrupt-cells = <2>;
 541                 };
 542
 543                 uart1: serial@4806a000 {
 544                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 545                         reg = <0x4806a000 0x100>;
 546                         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 547                         ti,hwmods = "uart1";
 548                         clock-frequency = <48000000>;
 549                         status = "disabled";
 550                         dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
 551                         dma-names = "tx", "rx";
 552                 };
 553
 554                 uart2: serial@4806c000 {
 555                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 556                         reg = <0x4806c000 0x100>;
 557                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 558                         ti,hwmods = "uart2";
 559                         clock-frequency = <48000000>;
 560                         status = "disabled";
 561                         dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
 562                         dma-names = "tx", "rx";
 563                 };
 564
 565                 uart3: serial@48020000 {
 566                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 567                         reg = <0x48020000 0x100>;
 568                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 569                         ti,hwmods = "uart3";
 570                         clock-frequency = <48000000>;
 571                         status = "disabled";
 572                         dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
 573                         dma-names = "tx", "rx";
 574                 };
 575
 576                 uart4: serial@4806e000 {
 577                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 578                         reg = <0x4806e000 0x100>;
 579                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 580                         ti,hwmods = "uart4";
 581                         clock-frequency = <48000000>;
 582                         status = "disabled";
 583                         dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
 584                         dma-names = "tx", "rx";
 585                 };
 586
 587                 uart5: serial@48066000 {
 588                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 589                         reg = <0x48066000 0x100>;
 590                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 591                         ti,hwmods = "uart5";
 592                         clock-frequency = <48000000>;
 593                         status = "disabled";
 594                         dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
 595                         dma-names = "tx", "rx";
 596                 };
 597
 598                 uart6: serial@48068000 {
 599                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 600                         reg = <0x48068000 0x100>;
 601                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 602                         ti,hwmods = "uart6";
 603                         clock-frequency = <48000000>;
 604                         status = "disabled";
 605                         dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
 606                         dma-names = "tx", "rx";
 607                 };
 608
 609                 uart7: serial@48420000 {
 610                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 611                         reg = <0x48420000 0x100>;
 612                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 613                         ti,hwmods = "uart7";
 614                         clock-frequency = <48000000>;
 615                         status = "disabled";
 616                 };
 617
 618                 uart8: serial@48422000 {
 619                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 620                         reg = <0x48422000 0x100>;
 621                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 622                         ti,hwmods = "uart8";
 623                         clock-frequency = <48000000>;
 624                         status = "disabled";
 625                 };
 626
 627                 uart9: serial@48424000 {
 628                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 629                         reg = <0x48424000 0x100>;
 630                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 631                         ti,hwmods = "uart9";
 632                         clock-frequency = <48000000>;
 633                         status = "disabled";
 634                 };
 635
 636                 uart10: serial@4ae2b000 {
 637                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 638                         reg = <0x4ae2b000 0x100>;
 639                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 640                         ti,hwmods = "uart10";
 641                         clock-frequency = <48000000>;
 642                         status = "disabled";
 643                 };
 644
 645                 mailbox1: mailbox@4a0f4000 {
 646                         compatible = "ti,omap4-mailbox";
 647                         reg = <0x4a0f4000 0x200>;
 648                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 649                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 650                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 651                         ti,hwmods = "mailbox1";
 652                         #mbox-cells = <1>;
 653                         ti,mbox-num-users = <3>;
 654                         ti,mbox-num-fifos = <8>;
 655                         status = "disabled";
 656                 };
 657
 658                 mailbox2: mailbox@4883a000 {
 659                         compatible = "ti,omap4-mailbox";
 660                         reg = <0x4883a000 0x200>;
 661                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 662                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 663                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 664                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 665                         ti,hwmods = "mailbox2";
 666                         #mbox-cells = <1>;
 667                         ti,mbox-num-users = <4>;
 668                         ti,mbox-num-fifos = <12>;
 669                         status = "disabled";
 670                 };
 671
 672                 mailbox3: mailbox@4883c000 {
 673                         compatible = "ti,omap4-mailbox";
 674                         reg = <0x4883c000 0x200>;
 675                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 676                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 677                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 678                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 679                         ti,hwmods = "mailbox3";
 680                         #mbox-cells = <1>;
 681                         ti,mbox-num-users = <4>;
 682                         ti,mbox-num-fifos = <12>;
 683                         status = "disabled";
 684                 };
 685
 686                 mailbox4: mailbox@4883e000 {
 687                         compatible = "ti,omap4-mailbox";
 688                         reg = <0x4883e000 0x200>;
 689                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 690                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 691                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 692                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 693                         ti,hwmods = "mailbox4";
 694                         #mbox-cells = <1>;
 695                         ti,mbox-num-users = <4>;
 696                         ti,mbox-num-fifos = <12>;
 697                         status = "disabled";
 698                 };
 699
 700                 mailbox5: mailbox@48840000 {
 701                         compatible = "ti,omap4-mailbox";
 702                         reg = <0x48840000 0x200>;
 703                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 704                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 705                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 706                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 707                         ti,hwmods = "mailbox5";
 708                         #mbox-cells = <1>;
 709                         ti,mbox-num-users = <4>;
 710                         ti,mbox-num-fifos = <12>;
 711                         status = "disabled";
 712                 };
 713
 714                 mailbox6: mailbox@48842000 {
 715                         compatible = "ti,omap4-mailbox";
 716                         reg = <0x48842000 0x200>;
 717                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 718                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 719                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 720                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 721                         ti,hwmods = "mailbox6";
 722                         #mbox-cells = <1>;
 723                         ti,mbox-num-users = <4>;
 724                         ti,mbox-num-fifos = <12>;
 725                         status = "disabled";
 726                 };
 727
 728                 mailbox7: mailbox@48844000 {
 729                         compatible = "ti,omap4-mailbox";
 730                         reg = <0x48844000 0x200>;
 731                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 732                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 733                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 734                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 735                         ti,hwmods = "mailbox7";
 736                         #mbox-cells = <1>;
 737                         ti,mbox-num-users = <4>;
 738                         ti,mbox-num-fifos = <12>;
 739                         status = "disabled";
 740                 };
 741
 742                 mailbox8: mailbox@48846000 {
 743                         compatible = "ti,omap4-mailbox";
 744                         reg = <0x48846000 0x200>;
 745                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 746                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 747                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 748                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 749                         ti,hwmods = "mailbox8";
 750                         #mbox-cells = <1>;
 751                         ti,mbox-num-users = <4>;
 752                         ti,mbox-num-fifos = <12>;
 753                         status = "disabled";
 754                 };
 755
 756                 mailbox9: mailbox@4885e000 {
 757                         compatible = "ti,omap4-mailbox";
 758                         reg = <0x4885e000 0x200>;
 759                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 760                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 761                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 762                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 763                         ti,hwmods = "mailbox9";
 764                         #mbox-cells = <1>;
 765                         ti,mbox-num-users = <4>;
 766                         ti,mbox-num-fifos = <12>;
 767                         status = "disabled";
 768                 };
 769
 770                 mailbox10: mailbox@48860000 {
 771                         compatible = "ti,omap4-mailbox";
 772                         reg = <0x48860000 0x200>;
 773                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 774                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 775                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 776                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 777                         ti,hwmods = "mailbox10";
 778                         #mbox-cells = <1>;
 779                         ti,mbox-num-users = <4>;
 780                         ti,mbox-num-fifos = <12>;
 781                         status = "disabled";
 782                 };
 783
 784                 mailbox11: mailbox@48862000 {
 785                         compatible = "ti,omap4-mailbox";
 786                         reg = <0x48862000 0x200>;
 787                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 788                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 789                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 790                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 791                         ti,hwmods = "mailbox11";
 792                         #mbox-cells = <1>;
 793                         ti,mbox-num-users = <4>;
 794                         ti,mbox-num-fifos = <12>;
 795                         status = "disabled";
 796                 };
 797
 798                 mailbox12: mailbox@48864000 {
 799                         compatible = "ti,omap4-mailbox";
 800                         reg = <0x48864000 0x200>;
 801                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 802                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 803                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 804                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 805                         ti,hwmods = "mailbox12";
 806                         #mbox-cells = <1>;
 807                         ti,mbox-num-users = <4>;
 808                         ti,mbox-num-fifos = <12>;
 809                         status = "disabled";
 810                 };
 811
 812                 mailbox13: mailbox@48802000 {
 813                         compatible = "ti,omap4-mailbox";
 814                         reg = <0x48802000 0x200>;
 815                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 816                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 817                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 818                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 819                         ti,hwmods = "mailbox13";
 820                         #mbox-cells = <1>;
 821                         ti,mbox-num-users = <4>;
 822                         ti,mbox-num-fifos = <12>;
 823                         status = "disabled";
 824                 };
 825
 826                 timer1: timer@4ae18000 {
 827                         compatible = "ti,omap5430-timer";
 828                         reg = <0x4ae18000 0x80>;
 829                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 830                         ti,hwmods = "timer1";
 831                         ti,timer-alwon;
 832                 };
 833
 834                 timer2: timer@48032000 {
 835                         compatible = "ti,omap5430-timer";
 836                         reg = <0x48032000 0x80>;
 837                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 838                         ti,hwmods = "timer2";
 839                 };
 840
 841                 timer3: timer@48034000 {
 842                         compatible = "ti,omap5430-timer";
 843                         reg = <0x48034000 0x80>;
 844                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 845                         ti,hwmods = "timer3";
 846                 };
 847
 848                 timer4: timer@48036000 {
 849                         compatible = "ti,omap5430-timer";
 850                         reg = <0x48036000 0x80>;
 851                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 852                         ti,hwmods = "timer4";
 853                 };
 854
 855                 timer5: timer@48820000 {
 856                         compatible = "ti,omap5430-timer";
 857                         reg = <0x48820000 0x80>;
 858                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 859                         ti,hwmods = "timer5";
 860                 };
 861
 862                 timer6: timer@48822000 {
 863                         compatible = "ti,omap5430-timer";
 864                         reg = <0x48822000 0x80>;
 865                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 866                         ti,hwmods = "timer6";
 867                 };
 868
 869                 timer7: timer@48824000 {
 870                         compatible = "ti,omap5430-timer";
 871                         reg = <0x48824000 0x80>;
 872                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 873                         ti,hwmods = "timer7";
 874                 };
 875
 876                 timer8: timer@48826000 {
 877                         compatible = "ti,omap5430-timer";
 878                         reg = <0x48826000 0x80>;
 879                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 880                         ti,hwmods = "timer8";
 881                 };
 882
 883                 timer9: timer@4803e000 {
 884                         compatible = "ti,omap5430-timer";
 885                         reg = <0x4803e000 0x80>;
 886                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 887                         ti,hwmods = "timer9";
 888                 };
 889
 890                 timer10: timer@48086000 {
 891                         compatible = "ti,omap5430-timer";
 892                         reg = <0x48086000 0x80>;
 893                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 894                         ti,hwmods = "timer10";
 895                 };
 896
 897                 timer11: timer@48088000 {
 898                         compatible = "ti,omap5430-timer";
 899                         reg = <0x48088000 0x80>;
 900                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 901                         ti,hwmods = "timer11";
 902                 };
 903
 904                 timer12: timer@4ae20000 {
 905                         compatible = "ti,omap5430-timer";
 906                         reg = <0x4ae20000 0x80>;
 907                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 908                         ti,hwmods = "timer12";
 909                         ti,timer-alwon;
 910                         ti,timer-secure;
 911                 };
 912
 913                 timer13: timer@48828000 {
 914                         compatible = "ti,omap5430-timer";
 915                         reg = <0x48828000 0x80>;
 916                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 917                         ti,hwmods = "timer13";
 918                 };
 919
 920                 timer14: timer@4882a000 {
 921                         compatible = "ti,omap5430-timer";
 922                         reg = <0x4882a000 0x80>;
 923                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 924                         ti,hwmods = "timer14";
 925                 };
 926
 927                 timer15: timer@4882c000 {
 928                         compatible = "ti,omap5430-timer";
 929                         reg = <0x4882c000 0x80>;
 930                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 931                         ti,hwmods = "timer15";
 932                 };
 933
 934                 timer16: timer@4882e000 {
 935                         compatible = "ti,omap5430-timer";
 936                         reg = <0x4882e000 0x80>;
 937                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 938                         ti,hwmods = "timer16";
 939                 };
 940
 941                 wdt2: wdt@4ae14000 {
 942                         compatible = "ti,omap3-wdt";
 943                         reg = <0x4ae14000 0x80>;
 944                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 945                         ti,hwmods = "wd_timer2";
 946                 };
 947
 948                 hwspinlock: spinlock@4a0f6000 {
 949                         compatible = "ti,omap4-hwspinlock";
 950                         reg = <0x4a0f6000 0x1000>;
 951                         ti,hwmods = "spinlock";
 952                         #hwlock-cells = <1>;
 953                 };
 954
 955                 dmm@4e000000 {
 956                         compatible = "ti,omap5-dmm";
 957                         reg = <0x4e000000 0x800>;
 958                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 959                         ti,hwmods = "dmm";
 960                 };
 961
 962                 i2c1: i2c@48070000 {
 963                         compatible = "ti,omap4-i2c";
 964                         reg = <0x48070000 0x100>;
 965                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 966                         #address-cells = <1>;
 967                         #size-cells = <0>;
 968                         ti,hwmods = "i2c1";
 969                         status = "disabled";
 970                 };
 971
 972                 i2c2: i2c@48072000 {
 973                         compatible = "ti,omap4-i2c";
 974                         reg = <0x48072000 0x100>;
 975                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 976                         #address-cells = <1>;
 977                         #size-cells = <0>;
 978                         ti,hwmods = "i2c2";
 979                         status = "disabled";
 980                 };
 981
 982                 i2c3: i2c@48060000 {
 983                         compatible = "ti,omap4-i2c";
 984                         reg = <0x48060000 0x100>;
 985                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 986                         #address-cells = <1>;
 987                         #size-cells = <0>;
 988                         ti,hwmods = "i2c3";
 989                         status = "disabled";
 990                 };
 991
 992                 i2c4: i2c@4807a000 {
 993                         compatible = "ti,omap4-i2c";
 994                         reg = <0x4807a000 0x100>;
 995                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 996                         #address-cells = <1>;
 997                         #size-cells = <0>;
 998                         ti,hwmods = "i2c4";
 999                         status = "disabled";
1000                 };
1001
1002                 i2c5: i2c@4807c000 {
1003                         compatible = "ti,omap4-i2c";
1004                         reg = <0x4807c000 0x100>;
1005                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1006                         #address-cells = <1>;
1007                         #size-cells = <0>;
1008                         ti,hwmods = "i2c5";
1009                         status = "disabled";
1010                 };
1011
1012                 mmc1: mmc@4809c000 {
1013                         compatible = "ti,omap4-hsmmc";
1014                         reg = <0x4809c000 0x400>;
1015                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1016                         ti,hwmods = "mmc1";
1017                         ti,dual-volt;
1018                         ti,needs-special-reset;
1019                         dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
1020                         dma-names = "tx", "rx";
1021                         status = "disabled";
1022                         pbias-supply = <&pbias_mmc_reg>;
1023                 };
1024
1025                 mmc2: mmc@480b4000 {
1026                         compatible = "ti,omap4-hsmmc";
1027                         reg = <0x480b4000 0x400>;
1028                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1029                         ti,hwmods = "mmc2";
1030                         ti,needs-special-reset;
1031                         dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
1032                         dma-names = "tx", "rx";
1033                         status = "disabled";
1034                 };
1035
1036                 mmc3: mmc@480ad000 {
1037                         compatible = "ti,omap4-hsmmc";
1038                         reg = <0x480ad000 0x400>;
1039                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1040                         ti,hwmods = "mmc3";
1041                         ti,needs-special-reset;
1042                         dmas = <&sdma_xbar 77>, <&sdma_xbar 78>;
1043                         dma-names = "tx", "rx";
1044                         status = "disabled";
1045                 };
1046
1047                 mmc4: mmc@480d1000 {
1048                         compatible = "ti,omap4-hsmmc";
1049                         reg = <0x480d1000 0x400>;
1050                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1051                         ti,hwmods = "mmc4";
1052                         ti,needs-special-reset;
1053                         dmas = <&sdma_xbar 57>, <&sdma_xbar 58>;
1054                         dma-names = "tx", "rx";
1055                         status = "disabled";
1056                 };
1057
1058                 mmu0_dsp1: mmu@40d01000 {
1059                         compatible = "ti,dra7-dsp-iommu";
1060                         reg = <0x40d01000 0x100>;
1061                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1062                         ti,hwmods = "mmu0_dsp1";
1063                         #iommu-cells = <0>;
1064                         ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1065                         status = "disabled";
1066                 };
1067
1068                 mmu1_dsp1: mmu@40d02000 {
1069                         compatible = "ti,dra7-dsp-iommu";
1070                         reg = <0x40d02000 0x100>;
1071                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1072                         ti,hwmods = "mmu1_dsp1";
1073                         #iommu-cells = <0>;
1074                         ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1075                         status = "disabled";
1076                 };
1077
1078                 mmu_ipu1: mmu@58882000 {
1079                         compatible = "ti,dra7-iommu";
1080                         reg = <0x58882000 0x100>;
1081                         interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1082                         ti,hwmods = "mmu_ipu1";
1083                         #iommu-cells = <0>;
1084                         ti,iommu-bus-err-back;
1085                         status = "disabled";
1086                 };
1087
1088                 mmu_ipu2: mmu@55082000 {
1089                         compatible = "ti,dra7-iommu";
1090                         reg = <0x55082000 0x100>;
1091                         interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1092                         ti,hwmods = "mmu_ipu2";
1093                         #iommu-cells = <0>;
1094                         ti,iommu-bus-err-back;
1095                         status = "disabled";
1096                 };
1097
1098                 abb_mpu: regulator-abb-mpu {
1099                         compatible = "ti,abb-v3";
1100                         regulator-name = "abb_mpu";
1101                         #address-cells = <0>;
1102                         #size-cells = <0>;
1103                         clocks = <&sys_clkin1>;
1104                         ti,settling-time = <50>;
1105                         ti,clock-cycles = <16>;
1106
1107                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1108                               <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1109                               <0x4ae0c158 0x4>;
1110                         reg-names = "setup-address", "control-address",
1111                                     "int-address", "efuse-address",
1112                                     "ldo-address";
1113                         ti,tranxdone-status-mask = <0x80>;
1114                         /* LDOVBBMPU_FBB_MUX_CTRL */
1115                         ti,ldovbb-override-mask = <0x400>;
1116                         /* LDOVBBMPU_FBB_VSET_OUT */
1117                         ti,ldovbb-vset-mask = <0x1F>;
1118
1119                         /*
1120                          * NOTE: only FBB mode used but actual vset will
1121                          * determine final biasing
1122                          */
1123                         ti,abb_info = <
1124                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1125                         1060000         0       0x0     0 0x02000000 0x01F00000
1126                         1160000         0       0x4     0 0x02000000 0x01F00000
1127                         1210000         0       0x8     0 0x02000000 0x01F00000
1128                         >;
1129                 };
1130
1131                 abb_ivahd: regulator-abb-ivahd {
1132                         compatible = "ti,abb-v3";
1133                         regulator-name = "abb_ivahd";
1134                         #address-cells = <0>;
1135                         #size-cells = <0>;
1136                         clocks = <&sys_clkin1>;
1137                         ti,settling-time = <50>;
1138                         ti,clock-cycles = <16>;
1139
1140                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1141                               <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1142                               <0x4a002470 0x4>;
1143                         reg-names = "setup-address", "control-address",
1144                                     "int-address", "efuse-address",
1145                                     "ldo-address";
1146                         ti,tranxdone-status-mask = <0x40000000>;
1147                         /* LDOVBBIVA_FBB_MUX_CTRL */
1148                         ti,ldovbb-override-mask = <0x400>;
1149                         /* LDOVBBIVA_FBB_VSET_OUT */
1150                         ti,ldovbb-vset-mask = <0x1F>;
1151
1152                         /*
1153                          * NOTE: only FBB mode used but actual vset will
1154                          * determine final biasing
1155                          */
1156                         ti,abb_info = <
1157                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1158                         1055000         0       0x0     0 0x02000000 0x01F00000
1159                         1150000         0       0x4     0 0x02000000 0x01F00000
1160                         1250000         0       0x8     0 0x02000000 0x01F00000
1161                         >;
1162                 };
1163
1164                 abb_dspeve: regulator-abb-dspeve {
1165                         compatible = "ti,abb-v3";
1166                         regulator-name = "abb_dspeve";
1167                         #address-cells = <0>;
1168                         #size-cells = <0>;
1169                         clocks = <&sys_clkin1>;
1170                         ti,settling-time = <50>;
1171                         ti,clock-cycles = <16>;
1172
1173                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1174                               <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1175                               <0x4a00246c 0x4>;
1176                         reg-names = "setup-address", "control-address",
1177                                     "int-address", "efuse-address",
1178                                     "ldo-address";
1179                         ti,tranxdone-status-mask = <0x20000000>;
1180                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1181                         ti,ldovbb-override-mask = <0x400>;
1182                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
1183                         ti,ldovbb-vset-mask = <0x1F>;
1184
1185                         /*
1186                          * NOTE: only FBB mode used but actual vset will
1187                          * determine final biasing
1188                          */
1189                         ti,abb_info = <
1190                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1191                         1055000         0       0x0     0 0x02000000 0x01F00000
1192                         1150000         0       0x4     0 0x02000000 0x01F00000
1193                         1250000         0       0x8     0 0x02000000 0x01F00000
1194                         >;
1195                 };
1196
1197                 abb_gpu: regulator-abb-gpu {
1198                         compatible = "ti,abb-v3";
1199                         regulator-name = "abb_gpu";
1200                         #address-cells = <0>;
1201                         #size-cells = <0>;
1202                         clocks = <&sys_clkin1>;
1203                         ti,settling-time = <50>;
1204                         ti,clock-cycles = <16>;
1205
1206                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1207                               <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1208                               <0x4ae0c154 0x4>;
1209                         reg-names = "setup-address", "control-address",
1210                                     "int-address", "efuse-address",
1211                                     "ldo-address";
1212                         ti,tranxdone-status-mask = <0x10000000>;
1213                         /* LDOVBBGPU_FBB_MUX_CTRL */
1214                         ti,ldovbb-override-mask = <0x400>;
1215                         /* LDOVBBGPU_FBB_VSET_OUT */
1216                         ti,ldovbb-vset-mask = <0x1F>;
1217
1218                         /*
1219                          * NOTE: only FBB mode used but actual vset will
1220                          * determine final biasing
1221                          */
1222                         ti,abb_info = <
1223                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1224                         1090000         0       0x0     0 0x02000000 0x01F00000
1225                         1210000         0       0x4     0 0x02000000 0x01F00000
1226                         1280000         0       0x8     0 0x02000000 0x01F00000
1227                         >;
1228                 };
1229
1230                 mcspi1: spi@48098000 {
1231                         compatible = "ti,omap4-mcspi";
1232                         reg = <0x48098000 0x200>;
1233                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1234                         #address-cells = <1>;
1235                         #size-cells = <0>;
1236                         ti,hwmods = "mcspi1";
1237                         ti,spi-num-cs = <4>;
1238                         dmas = <&sdma_xbar 35>,
1239                                <&sdma_xbar 36>,
1240                                <&sdma_xbar 37>,
1241                                <&sdma_xbar 38>,
1242                                <&sdma_xbar 39>,
1243                                <&sdma_xbar 40>,
1244                                <&sdma_xbar 41>,
1245                                <&sdma_xbar 42>;
1246                         dma-names = "tx0", "rx0", "tx1", "rx1",
1247                                     "tx2", "rx2", "tx3", "rx3";
1248                         status = "disabled";
1249                 };
1250
1251                 mcspi2: spi@4809a000 {
1252                         compatible = "ti,omap4-mcspi";
1253                         reg = <0x4809a000 0x200>;
1254                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1255                         #address-cells = <1>;
1256                         #size-cells = <0>;
1257                         ti,hwmods = "mcspi2";
1258                         ti,spi-num-cs = <2>;
1259                         dmas = <&sdma_xbar 43>,
1260                                <&sdma_xbar 44>,
1261                                <&sdma_xbar 45>,
1262                                <&sdma_xbar 46>;
1263                         dma-names = "tx0", "rx0", "tx1", "rx1";
1264                         status = "disabled";
1265                 };
1266
1267                 mcspi3: spi@480b8000 {
1268                         compatible = "ti,omap4-mcspi";
1269                         reg = <0x480b8000 0x200>;
1270                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1271                         #address-cells = <1>;
1272                         #size-cells = <0>;
1273                         ti,hwmods = "mcspi3";
1274                         ti,spi-num-cs = <2>;
1275                         dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1276                         dma-names = "tx0", "rx0";
1277                         status = "disabled";
1278                 };
1279
1280                 mcspi4: spi@480ba000 {
1281                         compatible = "ti,omap4-mcspi";
1282                         reg = <0x480ba000 0x200>;
1283                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1284                         #address-cells = <1>;
1285                         #size-cells = <0>;
1286                         ti,hwmods = "mcspi4";
1287                         ti,spi-num-cs = <1>;
1288                         dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1289                         dma-names = "tx0", "rx0";
1290                         status = "disabled";
1291                 };
1292
1293                 qspi: qspi@4b300000 {
1294                         compatible = "ti,dra7xxx-qspi";
1295                         reg = <0x4b300000 0x100>,
1296                               <0x5c000000 0x4000000>;
1297                         reg-names = "qspi_base", "qspi_mmap";
1298                         syscon-chipselects = <&scm_conf 0x558>;
1299                         #address-cells = <1>;
1300                         #size-cells = <0>;
1301                         ti,hwmods = "qspi";
1302                         clocks = <&qspi_gfclk_div>;
1303                         clock-names = "fck";
1304                         num-cs = <4>;
1305                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1306                         status = "disabled";
1307                 };
1308
1309                 /* OCP2SCP3 */
1310                 ocp2scp@4a090000 {
1311                         compatible = "ti,omap-ocp2scp";
1312                         #address-cells = <1>;
1313                         #size-cells = <1>;
1314                         ranges;
1315                         reg = <0x4a090000 0x20>;
1316                         ti,hwmods = "ocp2scp3";
1317                         sata_phy: phy@4A096000 {
1318                                 compatible = "ti,phy-pipe3-sata";
1319                                 reg = <0x4A096000 0x80>, /* phy_rx */
1320                                       <0x4A096400 0x64>, /* phy_tx */
1321                                       <0x4A096800 0x40>; /* pll_ctrl */
1322                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1323                                 syscon-phy-power = <&scm_conf 0x374>;
1324                                 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1325                                 clock-names = "sysclk", "refclk";
1326                                 syscon-pllreset = <&scm_conf 0x3fc>;
1327                                 #phy-cells = <0>;
1328                         };
1329
1330                         pcie1_phy: pciephy@4a094000 {
1331                                 compatible = "ti,phy-pipe3-pcie";
1332                                 reg = <0x4a094000 0x80>, /* phy_rx */
1333                                       <0x4a094400 0x64>; /* phy_tx */
1334                                 reg-names = "phy_rx", "phy_tx";
1335                                 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1336                                 syscon-pcs = <&scm_conf_pcie 0x10>;
1337                                 clocks = <&dpll_pcie_ref_ck>,
1338                                          <&dpll_pcie_ref_m2ldo_ck>,
1339                                          <&optfclk_pciephy1_32khz>,
1340                                          <&optfclk_pciephy1_clk>,
1341                                          <&optfclk_pciephy1_div_clk>,
1342                                          <&optfclk_pciephy_div>,
1343                                          <&sys_clkin1>;
1344                                 clock-names = "dpll_ref", "dpll_ref_m2",
1345                                               "wkupclk", "refclk",
1346                                               "div-clk", "phy-div", "sysclk";
1347                                 #phy-cells = <0>;
1348                         };
1349
1350                         pcie2_phy: pciephy@4a095000 {
1351                                 compatible = "ti,phy-pipe3-pcie";
1352                                 reg = <0x4a095000 0x80>, /* phy_rx */
1353                                       <0x4a095400 0x64>; /* phy_tx */
1354                                 reg-names = "phy_rx", "phy_tx";
1355                                 syscon-phy-power = <&scm_conf_pcie 0x20>;
1356                                 syscon-pcs = <&scm_conf_pcie 0x10>;
1357                                 clocks = <&dpll_pcie_ref_ck>,
1358                                          <&dpll_pcie_ref_m2ldo_ck>,
1359                                          <&optfclk_pciephy2_32khz>,
1360                                          <&optfclk_pciephy2_clk>,
1361                                          <&optfclk_pciephy2_div_clk>,
1362                                          <&optfclk_pciephy_div>,
1363                                          <&sys_clkin1>;
1364                                 clock-names = "dpll_ref", "dpll_ref_m2",
1365                                               "wkupclk", "refclk",
1366                                               "div-clk", "phy-div", "sysclk";
1367                                 #phy-cells = <0>;
1368                                 status = "disabled";
1369                         };
1370                 };
1371
1372                 sata: sata@4a141100 {
1373                         compatible = "snps,dwc-ahci";
1374                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1375                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1376                         phys = <&sata_phy>;
1377                         phy-names = "sata-phy";
1378                         clocks = <&sata_ref_clk>;
1379                         ti,hwmods = "sata";
1380                 };
1381
1382                 rtc: rtc@48838000 {
1383                         compatible = "ti,am3352-rtc";
1384                         reg = <0x48838000 0x100>;
1385                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1386                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1387                         ti,hwmods = "rtcss";
1388                         clocks = <&sys_32k_ck>;
1389                 };
1390
1391                 /* OCP2SCP1 */
1392                 ocp2scp@4a080000 {
1393                         compatible = "ti,omap-ocp2scp";
1394                         #address-cells = <1>;
1395                         #size-cells = <1>;
1396                         ranges;
1397                         reg = <0x4a080000 0x20>;
1398                         ti,hwmods = "ocp2scp1";
1399
1400                         usb2_phy1: phy@4a084000 {
1401                                 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1402                                 reg = <0x4a084000 0x400>;
1403                                 syscon-phy-power = <&scm_conf 0x300>;
1404                                 clocks = <&usb_phy1_always_on_clk32k>,
1405                                          <&usb_otg_ss1_refclk960m>;
1406                                 clock-names =   "wkupclk",
1407                                                 "refclk";
1408                                 #phy-cells = <0>;
1409                         };
1410
1411                         usb2_phy2: phy@4a085000 {
1412                                 compatible = "ti,dra7x-usb2-phy2",
1413                                              "ti,omap-usb2";
1414                                 reg = <0x4a085000 0x400>;
1415                                 syscon-phy-power = <&scm_conf 0xe74>;
1416                                 clocks = <&usb_phy2_always_on_clk32k>,
1417                                          <&usb_otg_ss2_refclk960m>;
1418                                 clock-names =   "wkupclk",
1419                                                 "refclk";
1420                                 #phy-cells = <0>;
1421                         };
1422
1423                         usb3_phy1: phy@4a084400 {
1424                                 compatible = "ti,omap-usb3";
1425                                 reg = <0x4a084400 0x80>,
1426                                       <0x4a084800 0x64>,
1427                                       <0x4a084c00 0x40>;
1428                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1429                                 syscon-phy-power = <&scm_conf 0x370>;
1430                                 clocks = <&usb_phy3_always_on_clk32k>,
1431                                          <&sys_clkin1>,
1432                                          <&usb_otg_ss1_refclk960m>;
1433                                 clock-names =   "wkupclk",
1434                                                 "sysclk",
1435                                                 "refclk";
1436                                 #phy-cells = <0>;
1437                         };
1438                 };
1439
1440                 omap_dwc3_1: omap_dwc3_1@48880000 {
1441                         compatible = "ti,dwc3";
1442                         ti,hwmods = "usb_otg_ss1";
1443                         reg = <0x48880000 0x10000>;
1444                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1445                         #address-cells = <1>;
1446                         #size-cells = <1>;
1447                         utmi-mode = <2>;
1448                         ranges;
1449                         usb1: usb@48890000 {
1450                                 compatible = "snps,dwc3";
1451                                 reg = <0x48890000 0x17000>;
1452                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1453                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1454                                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1455                                 interrupt-names = "peripheral",
1456                                                   "host",
1457                                                   "otg";
1458                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1459                                 phy-names = "usb2-phy", "usb3-phy";
1460                                 maximum-speed = "super-speed";
1461                                 dr_mode = "otg";
1462                                 snps,dis_u3_susphy_quirk;
1463                                 snps,dis_u2_susphy_quirk;
1464                         };
1465                 };
1466
1467                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1468                         compatible = "ti,dwc3";
1469                         ti,hwmods = "usb_otg_ss2";
1470                         reg = <0x488c0000 0x10000>;
1471                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1472                         #address-cells = <1>;
1473                         #size-cells = <1>;
1474                         utmi-mode = <2>;
1475                         ranges;
1476                         usb2: usb@488d0000 {
1477                                 compatible = "snps,dwc3";
1478                                 reg = <0x488d0000 0x17000>;
1479                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1480                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1481                                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1482                                 interrupt-names = "peripheral",
1483                                                   "host",
1484                                                   "otg";
1485                                 phys = <&usb2_phy2>;
1486                                 phy-names = "usb2-phy";
1487                                 maximum-speed = "high-speed";
1488                                 dr_mode = "otg";
1489                                 snps,dis_u3_susphy_quirk;
1490                                 snps,dis_u2_susphy_quirk;
1491                         };
1492                 };
1493
1494                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1495                 omap_dwc3_3: omap_dwc3_3@48900000 {
1496                         compatible = "ti,dwc3";
1497                         ti,hwmods = "usb_otg_ss3";
1498                         reg = <0x48900000 0x10000>;
1499                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1500                         #address-cells = <1>;
1501                         #size-cells = <1>;
1502                         utmi-mode = <2>;
1503                         ranges;
1504                         status = "disabled";
1505                         usb3: usb@48910000 {
1506                                 compatible = "snps,dwc3";
1507                                 reg = <0x48910000 0x17000>;
1508                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1509                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1510                                              <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1511                                 interrupt-names = "peripheral",
1512                                                   "host",
1513                                                   "otg";
1514                                 maximum-speed = "high-speed";
1515                                 dr_mode = "otg";
1516                                 snps,dis_u3_susphy_quirk;
1517                                 snps,dis_u2_susphy_quirk;
1518                         };
1519                 };
1520
1521                 elm: elm@48078000 {
1522                         compatible = "ti,am3352-elm";
1523                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1524                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1525                         ti,hwmods = "elm";
1526                         status = "disabled";
1527                 };
1528
1529                 gpmc: gpmc@50000000 {
1530                         compatible = "ti,am3352-gpmc";
1531                         ti,hwmods = "gpmc";
1532                         reg = <0x50000000 0x37c>;      /* device IO registers */
1533                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1534                         dmas = <&edma_xbar 4 0>;
1535                         dma-names = "rxtx";
1536                         gpmc,num-cs = <8>;
1537                         gpmc,num-waitpins = <2>;
1538                         #address-cells = <2>;
1539                         #size-cells = <1>;
1540                         interrupt-controller;
1541                         #interrupt-cells = <2>;
1542                         gpio-controller;
1543                         #gpio-cells = <2>;
1544                         status = "disabled";
1545                 };
1546
1547                 atl: atl@4843c000 {
1548                         compatible = "ti,dra7-atl";
1549                         reg = <0x4843c000 0x3ff>;
1550                         ti,hwmods = "atl";
1551                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1552                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1553                         clocks = <&atl_gfclk_mux>;
1554                         clock-names = "fck";
1555                         status = "disabled";
1556                 };
1557
1558                 mcasp1: mcasp@48460000 {
1559                         compatible = "ti,dra7-mcasp-audio";
1560                         ti,hwmods = "mcasp1";
1561                         reg = <0x48460000 0x2000>,
1562                               <0x45800000 0x1000>;
1563                         reg-names = "mpu","dat";
1564                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1565                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1566                         interrupt-names = "tx", "rx";
1567                         dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1568                         dma-names = "tx", "rx";
1569                         clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
1570                                  <&mcasp1_ahclkr_mux>;
1571                         clock-names = "fck", "ahclkx", "ahclkr";
1572                         status = "disabled";
1573                 };
1574
1575                 mcasp2: mcasp@48464000 {
1576                         compatible = "ti,dra7-mcasp-audio";
1577                         ti,hwmods = "mcasp2";
1578                         reg = <0x48464000 0x2000>,
1579                               <0x45c00000 0x1000>;
1580                         reg-names = "mpu","dat";
1581                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1582                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1583                         interrupt-names = "tx", "rx";
1584                         dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1585                         dma-names = "tx", "rx";
1586                         clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
1587                                  <&mcasp2_ahclkr_mux>;
1588                         clock-names = "fck", "ahclkx", "ahclkr";
1589                         status = "disabled";
1590                 };
1591
1592                 mcasp3: mcasp@48468000 {
1593                         compatible = "ti,dra7-mcasp-audio";
1594                         ti,hwmods = "mcasp3";
1595                         reg = <0x48468000 0x2000>,
1596                               <0x46000000 0x1000>;
1597                         reg-names = "mpu","dat";
1598                         interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1599                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1600                         interrupt-names = "tx", "rx";
1601                         dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1602                         dma-names = "tx", "rx";
1603                         clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
1604                         clock-names = "fck", "ahclkx";
1605                         status = "disabled";
1606                 };
1607
1608                 mcasp4: mcasp@4846c000 {
1609                         compatible = "ti,dra7-mcasp-audio";
1610                         ti,hwmods = "mcasp4";
1611                         reg = <0x4846c000 0x2000>,
1612                               <0x48436000 0x1000>;
1613                         reg-names = "mpu","dat";
1614                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1615                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1616                         interrupt-names = "tx", "rx";
1617                         dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1618                         dma-names = "tx", "rx";
1619                         clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
1620                         clock-names = "fck", "ahclkx";
1621                         status = "disabled";
1622                 };
1623
1624                 mcasp5: mcasp@48470000 {
1625                         compatible = "ti,dra7-mcasp-audio";
1626                         ti,hwmods = "mcasp5";
1627                         reg = <0x48470000 0x2000>,
1628                               <0x4843a000 0x1000>;
1629                         reg-names = "mpu","dat";
1630                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1631                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1632                         interrupt-names = "tx", "rx";
1633                         dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1634                         dma-names = "tx", "rx";
1635                         clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
1636                         clock-names = "fck", "ahclkx";
1637                         status = "disabled";
1638                 };
1639
1640                 mcasp6: mcasp@48474000 {
1641                         compatible = "ti,dra7-mcasp-audio";
1642                         ti,hwmods = "mcasp6";
1643                         reg = <0x48474000 0x2000>,
1644                               <0x4844c000 0x1000>;
1645                         reg-names = "mpu","dat";
1646                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1647                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1648                         interrupt-names = "tx", "rx";
1649                         dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1650                         dma-names = "tx", "rx";
1651                         clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
1652                         clock-names = "fck", "ahclkx";
1653                         status = "disabled";
1654                 };
1655
1656                 mcasp7: mcasp@48478000 {
1657                         compatible = "ti,dra7-mcasp-audio";
1658                         ti,hwmods = "mcasp7";
1659                         reg = <0x48478000 0x2000>,
1660                               <0x48450000 0x1000>;
1661                         reg-names = "mpu","dat";
1662                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1663                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1664                         interrupt-names = "tx", "rx";
1665                         dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1666                         dma-names = "tx", "rx";
1667                         clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
1668                         clock-names = "fck", "ahclkx";
1669                         status = "disabled";
1670                 };
1671
1672                 mcasp8: mcasp@4847c000 {
1673                         compatible = "ti,dra7-mcasp-audio";
1674                         ti,hwmods = "mcasp8";
1675                         reg = <0x4847c000 0x2000>,
1676                               <0x48454000 0x1000>;
1677                         reg-names = "mpu","dat";
1678                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1679                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1680                         interrupt-names = "tx", "rx";
1681                         dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1682                         dma-names = "tx", "rx";
1683                         clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
1684                         clock-names = "fck", "ahclkx";
1685                         status = "disabled";
1686                 };
1687
1688                 crossbar_mpu: crossbar@4a002a48 {
1689                         compatible = "ti,irq-crossbar";
1690                         reg = <0x4a002a48 0x130>;
1691                         interrupt-controller;
1692                         interrupt-parent = <&wakeupgen>;
1693                         #interrupt-cells = <3>;
1694                         ti,max-irqs = <160>;
1695                         ti,max-crossbar-sources = <MAX_SOURCES>;
1696                         ti,reg-size = <2>;
1697                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1698                         ti,irqs-skip = <10 133 139 140>;
1699                         ti,irqs-safe-map = <0>;
1700                 };
1701
1702                 mac: ethernet@48484000 {
1703                         compatible = "ti,dra7-cpsw","ti,cpsw";
1704                         ti,hwmods = "gmac";
1705                         clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
1706                         clock-names = "fck", "cpts";
1707                         cpdma_channels = <8>;
1708                         ale_entries = <1024>;
1709                         bd_ram_size = <0x2000>;
1710                         no_bd_ram = <0>;
1711                         mac_control = <0x20>;
1712                         slaves = <2>;
1713                         active_slave = <0>;
1714                         cpts_clock_mult = <0x784CFE14>;
1715                         cpts_clock_shift = <29>;
1716                         reg = <0x48484000 0x1000
1717                                0x48485200 0x2E00>;
1718                         #address-cells = <1>;
1719                         #size-cells = <1>;
1720
1721                         /*
1722                          * Do not allow gating of cpsw clock as workaround
1723                          * for errata i877. Keeping internal clock disabled
1724                          * causes the device switching characteristics
1725                          * to degrade over time and eventually fail to meet
1726                          * the data manual delay time/skew specs.
1727                          */
1728                         ti,no-idle;
1729
1730                         /*
1731                          * rx_thresh_pend
1732                          * rx_pend
1733                          * tx_pend
1734                          * misc_pend
1735                          */
1736                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1737                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1738                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1739                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1740                         ranges;
1741                         syscon = <&scm_conf>;
1742                         status = "disabled";
1743
1744                         davinci_mdio: mdio@48485000 {
1745                                 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1746                                 #address-cells = <1>;
1747                                 #size-cells = <0>;
1748                                 ti,hwmods = "davinci_mdio";
1749                                 bus_freq = <1000000>;
1750                                 reg = <0x48485000 0x100>;
1751                         };
1752
1753                         cpsw_emac0: slave@48480200 {
1754                                 /* Filled in by U-Boot */
1755                                 mac-address = [ 00 00 00 00 00 00 ];
1756                         };
1757
1758                         cpsw_emac1: slave@48480300 {
1759                                 /* Filled in by U-Boot */
1760                                 mac-address = [ 00 00 00 00 00 00 ];
1761                         };
1762
1763                         phy_sel: cpsw-phy-sel@4a002554 {
1764                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1765                                 reg= <0x4a002554 0x4>;
1766                                 reg-names = "gmii-sel";
1767                         };
1768                 };
1769
1770                 dcan1: can@481cc000 {
1771                         compatible = "ti,dra7-d_can";
1772                         ti,hwmods = "dcan1";
1773                         reg = <0x4ae3c000 0x2000>;
1774                         syscon-raminit = <&scm_conf 0x558 0>;
1775                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1776                         clocks = <&dcan1_sys_clk_mux>;
1777                         status = "disabled";
1778                 };
1779
1780                 dcan2: can@481d0000 {
1781                         compatible = "ti,dra7-d_can";
1782                         ti,hwmods = "dcan2";
1783                         reg = <0x48480000 0x2000>;
1784                         syscon-raminit = <&scm_conf 0x558 1>;
1785                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1786                         clocks = <&sys_clkin1>;
1787                         status = "disabled";
1788                 };
1789
1790                 dss: dss@58000000 {
1791                         compatible = "ti,dra7-dss";
1792                         /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1793                         /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1794                         status = "disabled";
1795                         ti,hwmods = "dss_core";
1796                         /* CTRL_CORE_DSS_PLL_CONTROL */
1797                         syscon-pll-ctrl = <&scm_conf 0x538>;
1798                         #address-cells = <1>;
1799                         #size-cells = <1>;
1800                         ranges;
1801
1802                         dispc@58001000 {
1803                                 compatible = "ti,dra7-dispc";
1804                                 reg = <0x58001000 0x1000>;
1805                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1806                                 ti,hwmods = "dss_dispc";
1807                                 clocks = <&dss_dss_clk>;
1808                                 clock-names = "fck";
1809                                 /* CTRL_CORE_SMA_SW_1 */
1810                                 syscon-pol = <&scm_conf 0x534>;
1811                         };
1812
1813                         hdmi: encoder@58060000 {
1814                                 compatible = "ti,dra7-hdmi";
1815                                 reg = <0x58040000 0x200>,
1816                                       <0x58040200 0x80>,
1817                                       <0x58040300 0x80>,
1818                                       <0x58060000 0x19000>;
1819                                 reg-names = "wp", "pll", "phy", "core";
1820                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1821                                 status = "disabled";
1822                                 ti,hwmods = "dss_hdmi";
1823                                 clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
1824                                 clock-names = "fck", "sys_clk";
1825                         };
1826                 };
1827
1828                 epwmss0: epwmss@4843e000 {
1829                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1830                         reg = <0x4843e000 0x30>;
1831                         ti,hwmods = "epwmss0";
1832                         #address-cells = <1>;
1833                         #size-cells = <1>;
1834                         status = "disabled";
1835                         ranges;
1836
1837                         ehrpwm0: pwm@4843e200 {
1838                                 compatible = "ti,dra746-ehrpwm",
1839                                              "ti,am3352-ehrpwm";
1840                                 #pwm-cells = <3>;
1841                                 reg = <0x4843e200 0x80>;
1842                                 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1843                                 clock-names = "tbclk", "fck";
1844                                 status = "disabled";
1845                         };
1846
1847                         ecap0: ecap@4843e100 {
1848                                 compatible = "ti,dra746-ecap",
1849                                              "ti,am3352-ecap";
1850                                 #pwm-cells = <3>;
1851                                 reg = <0x4843e100 0x80>;
1852                                 clocks = <&l4_root_clk_div>;
1853                                 clock-names = "fck";
1854                                 status = "disabled";
1855                         };
1856                 };
1857
1858                 epwmss1: epwmss@48440000 {
1859                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1860                         reg = <0x48440000 0x30>;
1861                         ti,hwmods = "epwmss1";
1862                         #address-cells = <1>;
1863                         #size-cells = <1>;
1864                         status = "disabled";
1865                         ranges;
1866
1867                         ehrpwm1: pwm@48440200 {
1868                                 compatible = "ti,dra746-ehrpwm",
1869                                              "ti,am3352-ehrpwm";
1870                                 #pwm-cells = <3>;
1871                                 reg = <0x48440200 0x80>;
1872                                 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
1873                                 clock-names = "tbclk", "fck";
1874                                 status = "disabled";
1875                         };
1876
1877                         ecap1: ecap@48440100 {
1878                                 compatible = "ti,dra746-ecap",
1879                                              "ti,am3352-ecap";
1880                                 #pwm-cells = <3>;
1881                                 reg = <0x48440100 0x80>;
1882                                 clocks = <&l4_root_clk_div>;
1883                                 clock-names = "fck";
1884                                 status = "disabled";
1885                         };
1886                 };
1887
1888                 epwmss2: epwmss@48442000 {
1889                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1890                         reg = <0x48442000 0x30>;
1891                         ti,hwmods = "epwmss2";
1892                         #address-cells = <1>;
1893                         #size-cells = <1>;
1894                         status = "disabled";
1895                         ranges;
1896
1897                         ehrpwm2: pwm@48442200 {
1898                                 compatible = "ti,dra746-ehrpwm",
1899                                              "ti,am3352-ehrpwm";
1900                                 #pwm-cells = <3>;
1901                                 reg = <0x48442200 0x80>;
1902                                 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
1903                                 clock-names = "tbclk", "fck";
1904                                 status = "disabled";
1905                         };
1906
1907                         ecap2: ecap@48442100 {
1908                                 compatible = "ti,dra746-ecap",
1909                                              "ti,am3352-ecap";
1910                                 #pwm-cells = <3>;
1911                                 reg = <0x48442100 0x80>;
1912                                 clocks = <&l4_root_clk_div>;
1913                                 clock-names = "fck";
1914                                 status = "disabled";
1915                         };
1916                 };
1917
1918                 aes1: aes@4b500000 {
1919                         compatible = "ti,omap4-aes";
1920                         ti,hwmods = "aes1";
1921                         reg = <0x4b500000 0xa0>;
1922                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1923                         dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
1924                         dma-names = "tx", "rx";
1925                         clocks = <&l3_iclk_div>;
1926                         clock-names = "fck";
1927                 };
1928
1929                 aes2: aes@4b700000 {
1930                         compatible = "ti,omap4-aes";
1931                         ti,hwmods = "aes2";
1932                         reg = <0x4b700000 0xa0>;
1933                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1934                         dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1935                         dma-names = "tx", "rx";
1936                         clocks = <&l3_iclk_div>;
1937                         clock-names = "fck";
1938                 };
1939
1940                 des: des@480a5000 {
1941                         compatible = "ti,omap4-des";
1942                         ti,hwmods = "des";
1943                         reg = <0x480a5000 0xa0>;
1944                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1945                         dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
1946                         dma-names = "tx", "rx";
1947                         clocks = <&l3_iclk_div>;
1948                         clock-names = "fck";
1949                 };
1950
1951                 sham: sham@53100000 {
1952                         compatible = "ti,omap5-sham";
1953                         ti,hwmods = "sham";
1954                         reg = <0x4b101000 0x300>;
1955                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1956                         dmas = <&edma_xbar 119 0>;
1957                         dma-names = "rx";
1958                         clocks = <&l3_iclk_div>;
1959                         clock-names = "fck";
1960                 };
1961
1962                 rng: rng@48090000 {
1963                         compatible = "ti,omap4-rng";
1964                         ti,hwmods = "rng";
1965                         reg = <0x48090000 0x2000>;
1966                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1967                         clocks = <&l3_iclk_div>;
1968                         clock-names = "fck";
1969                 };
1970         };
1971
1972         thermal_zones: thermal-zones {
1973                 #include "omap4-cpu-thermal.dtsi"
1974                 #include "omap5-gpu-thermal.dtsi"
1975                 #include "omap5-core-thermal.dtsi"
1976                 #include "dra7-dspeve-thermal.dtsi"
1977                 #include "dra7-iva-thermal.dtsi"
1978         };
1979
1980 };
1981
1982 &cpu_thermal {
1983         polling-delay = <500>; /* milliseconds */
1984 };
1985
1986 /include/ "dra7xx-clocks.dtsi"