arch/arm/boot/dts/dra7.dtsi

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/bus/ti-sysc.h>
  11 #include <dt-bindings/clock/dra7.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/pinctrl/dra.h>
  14 #include <dt-bindings/clock/dra7.h>
  15
  16 #define MAX_SOURCES 400
  17
  18 / {
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         compatible = "ti,dra7xx";
  23         interrupt-parent = <&crossbar_mpu>;
  24         chosen { };
  25
  26         aliases {
  27                 i2c0 = &i2c1;
  28                 i2c1 = &i2c2;
  29                 i2c2 = &i2c3;
  30                 i2c3 = &i2c4;
  31                 i2c4 = &i2c5;
  32                 serial0 = &uart1;
  33                 serial1 = &uart2;
  34                 serial2 = &uart3;
  35                 serial3 = &uart4;
  36                 serial4 = &uart5;
  37                 serial5 = &uart6;
  38                 serial6 = &uart7;
  39                 serial7 = &uart8;
  40                 serial8 = &uart9;
  41                 serial9 = &uart10;
  42                 ethernet0 = &cpsw_emac0;
  43                 ethernet1 = &cpsw_emac1;
  44                 d_can0 = &dcan1;
  45                 d_can1 = &dcan2;
  46                 spi0 = &qspi;
  47         };
  48
  49         timer {
  50                 compatible = "arm,armv7-timer";
  51                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  52                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  53                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
  54                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
  55                 interrupt-parent = <&gic>;
  56         };
  57
  58         gic: interrupt-controller@48211000 {
  59                 compatible = "arm,cortex-a15-gic";
  60                 interrupt-controller;
  61                 #interrupt-cells = <3>;
  62                 reg = <0x0 0x48211000 0x0 0x1000>,
  63                       <0x0 0x48212000 0x0 0x2000>,
  64                       <0x0 0x48214000 0x0 0x2000>,
  65                       <0x0 0x48216000 0x0 0x2000>;
  66                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  67                 interrupt-parent = <&gic>;
  68         };
  69
  70         wakeupgen: interrupt-controller@48281000 {
  71                 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
  72                 interrupt-controller;
  73                 #interrupt-cells = <3>;
  74                 reg = <0x0 0x48281000 0x0 0x1000>;
  75                 interrupt-parent = <&gic>;
  76         };
  77
  78         cpus {
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 cpu0: cpu@0 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a15";
  85                         reg = <0>;
  86
  87                         operating-points-v2 = <&cpu0_opp_table>;
  88
  89                         clocks = <&dpll_mpu_ck>;
  90                         clock-names = "cpu";
  91
  92                         clock-latency = <300000>; /* From omap-cpufreq driver */
  93
  94                         /* cooling options */
  95                         #cooling-cells = <2>; /* min followed by max */
  96
  97                         vbb-supply = <&abb_mpu>;
  98                 };
  99         };
 100
 101         cpu0_opp_table: opp-table {
 102                 compatible = "operating-points-v2-ti-cpu";
 103                 syscon = <&scm_wkup>;
 104
 105                 opp_nom-1000000000 {
 106                         opp-hz = /bits/ 64 <1000000000>;
 107                         opp-microvolt = <1060000 850000 1150000>,
 108                                         <1060000 850000 1150000>;
 109                         opp-supported-hw = <0xFF 0x01>;
 110                         opp-suspend;
 111                 };
 112
 113                 opp_od-1176000000 {
 114                         opp-hz = /bits/ 64 <1176000000>;
 115                         opp-microvolt = <1160000 885000 1160000>,
 116                                         <1160000 885000 1160000>;
 117
 118                         opp-supported-hw = <0xFF 0x02>;
 119                 };
 120
 121                 opp_high@1500000000 {
 122                         opp-hz = /bits/ 64 <1500000000>;
 123                         opp-microvolt = <1210000 950000 1250000>,
 124                                         <1210000 950000 1250000>;
 125                         opp-supported-hw = <0xFF 0x04>;
 126                 };
 127         };
 128
 129         /*
 130          * The soc node represents the soc top level view. It is used for IPs
 131          * that are not memory mapped in the MPU view or for the MPU itself.
 132          */
 133         soc {
 134                 compatible = "ti,omap-infra";
 135                 mpu {
 136                         compatible = "ti,omap5-mpu";
 137                         ti,hwmods = "mpu";
 138                 };
 139         };
 140
 141         /*
 142          * XXX: Use a flat representation of the SOC interconnect.
 143          * The real OMAP interconnect network is quite complex.
 144          * Since it will not bring real advantage to represent that in DT for
 145          * the moment, just use a fake OCP bus entry to represent the whole bus
 146          * hierarchy.
 147          */
 148         ocp {
 149                 compatible = "ti,dra7-l3-noc", "simple-bus";
 150                 #address-cells = <1>;
 151                 #size-cells = <1>;
 152                 ranges = <0x0 0x0 0x0 0xc0000000>;
 153                 ti,hwmods = "l3_main_1", "l3_main_2";
 154                 reg = <0x0 0x44000000 0x0 0x1000000>,
 155                       <0x0 0x45000000 0x0 0x1000>;
 156                 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 157                                       <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 158
 159                 l4_cfg: l4@4a000000 {
 160                         compatible = "ti,dra7-l4-cfg", "simple-bus";
 161                         #address-cells = <1>;
 162                         #size-cells = <1>;
 163                         ranges = <0 0x4a000000 0x22c000>;
 164
 165                         scm: scm@2000 {
 166                                 compatible = "ti,dra7-scm-core", "simple-bus";
 167                                 reg = <0x2000 0x2000>;
 168                                 #address-cells = <1>;
 169                                 #size-cells = <1>;
 170                                 ranges = <0 0x2000 0x2000>;
 171
 172                                 scm_conf: scm_conf@0 {
 173                                         compatible = "syscon", "simple-bus";
 174                                         reg = <0x0 0x1400>;
 175                                         #address-cells = <1>;
 176                                         #size-cells = <1>;
 177                                         ranges = <0 0x0 0x1400>;
 178
 179                                         pbias_regulator: pbias_regulator@e00 {
 180                                                 compatible = "ti,pbias-dra7", "ti,pbias-omap";
 181                                                 reg = <0xe00 0x4>;
 182                                                 syscon = <&scm_conf>;
 183                                                 pbias_mmc_reg: pbias_mmc_omap5 {
 184                                                         regulator-name = "pbias_mmc_omap5";
 185                                                         regulator-min-microvolt = <1800000>;
 186                                                         regulator-max-microvolt = <3300000>;
 187                                                 };
 188                                         };
 189
 190                                         scm_conf_clocks: clocks {
 191                                                 #address-cells = <1>;
 192                                                 #size-cells = <0>;
 193                                         };
 194                                 };
 195
 196                                 dra7_pmx_core: pinmux@1400 {
 197                                         compatible = "ti,dra7-padconf",
 198                                                      "pinctrl-single";
 199                                         reg = <0x1400 0x0468>;
 200                                         #address-cells = <1>;
 201                                         #size-cells = <0>;
 202                                         #pinctrl-cells = <1>;
 203                                         #interrupt-cells = <1>;
 204                                         interrupt-controller;
 205                                         pinctrl-single,register-width = <32>;
 206                                         pinctrl-single,function-mask = <0x3fffffff>;
 207                                 };
 208
 209                                 scm_conf1: scm_conf@1c04 {
 210                                         compatible = "syscon";
 211                                         reg = <0x1c04 0x0020>;
 212                                         #syscon-cells = <2>;
 213                                 };
 214
 215                                 scm_conf_pcie: scm_conf@1c24 {
 216                                         compatible = "syscon";
 217                                         reg = <0x1c24 0x0024>;
 218                                 };
 219
 220                                 sdma_xbar: dma-router@b78 {
 221                                         compatible = "ti,dra7-dma-crossbar";
 222                                         reg = <0xb78 0xfc>;
 223                                         #dma-cells = <1>;
 224                                         dma-requests = <205>;
 225                                         ti,dma-safe-map = <0>;
 226                                         dma-masters = <&sdma>;
 227                                 };
 228
 229                                 edma_xbar: dma-router@c78 {
 230                                         compatible = "ti,dra7-dma-crossbar";
 231                                         reg = <0xc78 0x7c>;
 232                                         #dma-cells = <2>;
 233                                         dma-requests = <204>;
 234                                         ti,dma-safe-map = <0>;
 235                                         dma-masters = <&edma>;
 236                                 };
 237                         };
 238
 239                         cm_core_aon: cm_core_aon@5000 {
 240                                 compatible = "ti,dra7-cm-core-aon",
 241                                               "simple-bus";
 242                                 #address-cells = <1>;
 243                                 #size-cells = <1>;
 244                                 reg = <0x5000 0x2000>;
 245                                 ranges = <0 0x5000 0x2000>;
 246
 247                                 cm_core_aon_clocks: clocks {
 248                                         #address-cells = <1>;
 249                                         #size-cells = <0>;
 250                                 };
 251
 252                                 cm_core_aon_clockdomains: clockdomains {
 253                                 };
 254                         };
 255
 256                         cm_core: cm_core@8000 {
 257                                 compatible = "ti,dra7-cm-core", "simple-bus";
 258                                 #address-cells = <1>;
 259                                 #size-cells = <1>;
 260                                 reg = <0x8000 0x3000>;
 261                                 ranges = <0 0x8000 0x3000>;
 262
 263                                 cm_core_clocks: clocks {
 264                                         #address-cells = <1>;
 265                                         #size-cells = <0>;
 266                                 };
 267
 268                                 cm_core_clockdomains: clockdomains {
 269                                 };
 270                         };
 271                 };
 272
 273                 l4_wkup: l4@4ae00000 {
 274                         compatible = "ti,dra7-l4-wkup", "simple-bus";
 275                         #address-cells = <1>;
 276                         #size-cells = <1>;
 277                         ranges = <0 0x4ae00000 0x3f000>;
 278
 279                         counter32k: counter@4000 {
 280                                 compatible = "ti,omap-counter32k";
 281                                 reg = <0x4000 0x40>;
 282                                 ti,hwmods = "counter_32k";
 283                         };
 284
 285                         prm: prm@6000 {
 286                                 compatible = "ti,dra7-prm", "simple-bus";
 287                                 reg = <0x6000 0x3000>;
 288                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 289                                 #address-cells = <1>;
 290                                 #size-cells = <1>;
 291                                 ranges = <0 0x6000 0x3000>;
 292
 293                                 prm_clocks: clocks {
 294                                         #address-cells = <1>;
 295                                         #size-cells = <0>;
 296                                 };
 297
 298                                 prm_clockdomains: clockdomains {
 299                                 };
 300                         };
 301
 302                         scm_wkup: scm_conf@c000 {
 303                                 compatible = "syscon";
 304                                 reg = <0xc000 0x1000>;
 305                         };
 306                 };
 307
 308                 axi@0 {
 309                         compatible = "simple-bus";
 310                         #size-cells = <1>;
 311                         #address-cells = <1>;
 312                         ranges = <0x51000000 0x51000000 0x3000
 313                                   0x0        0x20000000 0x10000000>;
 314                         /**
 315                          * To enable PCI endpoint mode, disable the pcie1_rc
 316                          * node and enable pcie1_ep mode.
 317                          */
 318                         pcie1_rc: pcie@51000000 {
 319                                 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
 320                                 reg-names = "rc_dbics", "ti_conf", "config";
 321                                 interrupts = <0 232 0x4>, <0 233 0x4>;
 322                                 #address-cells = <3>;
 323                                 #size-cells = <2>;
 324                                 device_type = "pci";
 325                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 326                                           0x82000000 0 0x20013000 0x13000 0 0xffed000>;
 327                                 bus-range = <0x00 0xff>;
 328                                 #interrupt-cells = <1>;
 329                                 num-lanes = <1>;
 330                                 linux,pci-domain = <0>;
 331                                 ti,hwmods = "pcie1";
 332                                 phys = <&pcie1_phy>;
 333                                 phy-names = "pcie-phy0";
 334                                 interrupt-map-mask = <0 0 0 7>;
 335                                 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
 336                                                 <0 0 0 2 &pcie1_intc 2>,
 337                                                 <0 0 0 3 &pcie1_intc 3>,
 338                                                 <0 0 0 4 &pcie1_intc 4>;
 339                                 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
 340                                 status = "disabled";
 341                                 pcie1_intc: interrupt-controller {
 342                                         interrupt-controller;
 343                                         #address-cells = <0>;
 344                                         #interrupt-cells = <1>;
 345                                 };
 346                         };
 347
 348                         pcie1_ep: pcie_ep@51000000 {
 349                                 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
 350                                 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
 351                                 interrupts = <0 232 0x4>;
 352                                 num-lanes = <1>;
 353                                 num-ib-windows = <4>;
 354                                 num-ob-windows = <16>;
 355                                 ti,hwmods = "pcie1";
 356                                 phys = <&pcie1_phy>;
 357                                 phy-names = "pcie-phy0";
 358                                 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
 359                                 status = "disabled";
 360                         };
 361                 };
 362
 363                 axi@1 {
 364                         compatible = "simple-bus";
 365                         #size-cells = <1>;
 366                         #address-cells = <1>;
 367                         ranges = <0x51800000 0x51800000 0x3000
 368                                   0x0        0x30000000 0x10000000>;
 369                         status = "disabled";
 370                         pcie2_rc: pcie@51800000 {
 371                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
 372                                 reg-names = "rc_dbics", "ti_conf", "config";
 373                                 interrupts = <0 355 0x4>, <0 356 0x4>;
 374                                 #address-cells = <3>;
 375                                 #size-cells = <2>;
 376                                 device_type = "pci";
 377                                 ranges = <0x81000000 0 0          0x03000 0 0x00010000
 378                                           0x82000000 0 0x30013000 0x13000 0 0xffed000>;
 379                                 bus-range = <0x00 0xff>;
 380                                 #interrupt-cells = <1>;
 381                                 num-lanes = <1>;
 382                                 linux,pci-domain = <1>;
 383                                 ti,hwmods = "pcie2";
 384                                 phys = <&pcie2_phy>;
 385                                 phy-names = "pcie-phy0";
 386                                 interrupt-map-mask = <0 0 0 7>;
 387                                 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
 388                                                 <0 0 0 2 &pcie2_intc 2>,
 389                                                 <0 0 0 3 &pcie2_intc 3>,
 390                                                 <0 0 0 4 &pcie2_intc 4>;
 391                                 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
 392                                 pcie2_intc: interrupt-controller {
 393                                         interrupt-controller;
 394                                         #address-cells = <0>;
 395                                         #interrupt-cells = <1>;
 396                                 };
 397                         };
 398                 };
 399
 400                 ocmcram1: ocmcram@40300000 {
 401                         compatible = "mmio-sram";
 402                         reg = <0x40300000 0x80000>;
 403                         ranges = <0x0 0x40300000 0x80000>;
 404                         #address-cells = <1>;
 405                         #size-cells = <1>;
 406                         /*
 407                          * This is a placeholder for an optional reserved
 408                          * region for use by secure software. The size
 409                          * of this region is not known until runtime so it
 410                          * is set as zero to either be updated to reserve
 411                          * space or left unchanged to leave all SRAM for use.
 412                          * On HS parts that that require the reserved region
 413                          * either the bootloader can update the size to
 414                          * the required amount or the node can be overridden
 415                          * from the board dts file for the secure platform.
 416                          */
 417                         sram-hs@0 {
 418                                 compatible = "ti,secure-ram";
 419                                 reg = <0x0 0x0>;
 420                         };
 421                 };
 422
 423                 /*
 424                  * NOTE: ocmcram2 and ocmcram3 are not available on all
 425                  * DRA7xx and AM57xx variants. Confirm availability in
 426                  * the data manual for the exact part number in use
 427                  * before enabling these nodes in the board dts file.
 428                  */
 429                 ocmcram2: ocmcram@40400000 {
 430                         status = "disabled";
 431                         compatible = "mmio-sram";
 432                         reg = <0x40400000 0x100000>;
 433                         ranges = <0x0 0x40400000 0x100000>;
 434                         #address-cells = <1>;
 435                         #size-cells = <1>;
 436                 };
 437
 438                 ocmcram3: ocmcram@40500000 {
 439                         status = "disabled";
 440                         compatible = "mmio-sram";
 441                         reg = <0x40500000 0x100000>;
 442                         ranges = <0x0 0x40500000 0x100000>;
 443                         #address-cells = <1>;
 444                         #size-cells = <1>;
 445                 };
 446
 447                 bandgap: bandgap@4a0021e0 {
 448                         reg = <0x4a0021e0 0xc
 449                                 0x4a00232c 0xc
 450                                 0x4a002380 0x2c
 451                                 0x4a0023C0 0x3c
 452                                 0x4a002564 0x8
 453                                 0x4a002574 0x50>;
 454                                 compatible = "ti,dra752-bandgap";
 455                                 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 456                                 #thermal-sensor-cells = <1>;
 457                 };
 458
 459                 dsp1_system: dsp_system@40d00000 {
 460                         compatible = "syscon";
 461                         reg = <0x40d00000 0x100>;
 462                 };
 463
 464                 dra7_iodelay_core: padconf@4844a000 {
 465                         compatible = "ti,dra7-iodelay";
 466                         reg = <0x4844a000 0x0d1c>;
 467                         #address-cells = <1>;
 468                         #size-cells = <0>;
 469                         #pinctrl-cells = <2>;
 470                 };
 471
 472                 sdma: dma-controller@4a056000 {
 473                         compatible = "ti,omap4430-sdma";
 474                         reg = <0x4a056000 0x1000>;
 475                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 476                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 477                                      <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 478                                      <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 479                         #dma-cells = <1>;
 480                         dma-channels = <32>;
 481                         dma-requests = <127>;
 482                         ti,hwmods = "dma_system";
 483                 };
 484
 485                 edma: edma@43300000 {
 486                         compatible = "ti,edma3-tpcc";
 487                         ti,hwmods = "tpcc";
 488                         reg = <0x43300000 0x100000>;
 489                         reg-names = "edma3_cc";
 490                         interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
 491                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
 492                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
 493                         interrupt-names = "edma3_ccint", "edma3_mperr",
 494                                           "edma3_ccerrint";
 495                         dma-requests = <64>;
 496                         #dma-cells = <2>;
 497
 498                         ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
 499
 500                         /*
 501                          * memcpy is disabled, can be enabled with:
 502                          * ti,edma-memcpy-channels = <20 21>;
 503                          * for example. Note that these channels need to be
 504                          * masked in the xbar as well.
 505                          */
 506                 };
 507
 508                 edma_tptc0: tptc@43400000 {
 509                         compatible = "ti,edma3-tptc";
 510                         ti,hwmods = "tptc0";
 511                         reg =   <0x43400000 0x100000>;
 512                         interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
 513                         interrupt-names = "edma3_tcerrint";
 514                 };
 515
 516                 edma_tptc1: tptc@43500000 {
 517                         compatible = "ti,edma3-tptc";
 518                         ti,hwmods = "tptc1";
 519                         reg =   <0x43500000 0x100000>;
 520                         interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
 521                         interrupt-names = "edma3_tcerrint";
 522                 };
 523
 524                 gpio1: gpio@4ae10000 {
 525                         compatible = "ti,omap4-gpio";
 526                         reg = <0x4ae10000 0x200>;
 527                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 528                         ti,hwmods = "gpio1";
 529                         gpio-controller;
 530                         #gpio-cells = <2>;
 531                         interrupt-controller;
 532                         #interrupt-cells = <2>;
 533                 };
 534
 535                 gpio2: gpio@48055000 {
 536                         compatible = "ti,omap4-gpio";
 537                         reg = <0x48055000 0x200>;
 538                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 539                         ti,hwmods = "gpio2";
 540                         gpio-controller;
 541                         #gpio-cells = <2>;
 542                         interrupt-controller;
 543                         #interrupt-cells = <2>;
 544                 };
 545
 546                 gpio3: gpio@48057000 {
 547                         compatible = "ti,omap4-gpio";
 548                         reg = <0x48057000 0x200>;
 549                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 550                         ti,hwmods = "gpio3";
 551                         gpio-controller;
 552                         #gpio-cells = <2>;
 553                         interrupt-controller;
 554                         #interrupt-cells = <2>;
 555                 };
 556
 557                 gpio4: gpio@48059000 {
 558                         compatible = "ti,omap4-gpio";
 559                         reg = <0x48059000 0x200>;
 560                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 561                         ti,hwmods = "gpio4";
 562                         gpio-controller;
 563                         #gpio-cells = <2>;
 564                         interrupt-controller;
 565                         #interrupt-cells = <2>;
 566                 };
 567
 568                 gpio5: gpio@4805b000 {
 569                         compatible = "ti,omap4-gpio";
 570                         reg = <0x4805b000 0x200>;
 571                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 572                         ti,hwmods = "gpio5";
 573                         gpio-controller;
 574                         #gpio-cells = <2>;
 575                         interrupt-controller;
 576                         #interrupt-cells = <2>;
 577                 };
 578
 579                 gpio6: gpio@4805d000 {
 580                         compatible = "ti,omap4-gpio";
 581                         reg = <0x4805d000 0x200>;
 582                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 583                         ti,hwmods = "gpio6";
 584                         gpio-controller;
 585                         #gpio-cells = <2>;
 586                         interrupt-controller;
 587                         #interrupt-cells = <2>;
 588                 };
 589
 590                 gpio7: gpio@48051000 {
 591                         compatible = "ti,omap4-gpio";
 592                         reg = <0x48051000 0x200>;
 593                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 594                         ti,hwmods = "gpio7";
 595                         gpio-controller;
 596                         #gpio-cells = <2>;
 597                         interrupt-controller;
 598                         #interrupt-cells = <2>;
 599                 };
 600
 601                 gpio8: gpio@48053000 {
 602                         compatible = "ti,omap4-gpio";
 603                         reg = <0x48053000 0x200>;
 604                         interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 605                         ti,hwmods = "gpio8";
 606                         gpio-controller;
 607                         #gpio-cells = <2>;
 608                         interrupt-controller;
 609                         #interrupt-cells = <2>;
 610                 };
 611
 612                 uart1: serial@4806a000 {
 613                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 614                         reg = <0x4806a000 0x100>;
 615                         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 616                         ti,hwmods = "uart1";
 617                         clock-frequency = <48000000>;
 618                         status = "disabled";
 619                         dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
 620                         dma-names = "tx", "rx";
 621                 };
 622
 623                 uart2: serial@4806c000 {
 624                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 625                         reg = <0x4806c000 0x100>;
 626                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 627                         ti,hwmods = "uart2";
 628                         clock-frequency = <48000000>;
 629                         status = "disabled";
 630                         dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
 631                         dma-names = "tx", "rx";
 632                 };
 633
 634                 uart3: serial@48020000 {
 635                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 636                         reg = <0x48020000 0x100>;
 637                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 638                         ti,hwmods = "uart3";
 639                         clock-frequency = <48000000>;
 640                         status = "disabled";
 641                         dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
 642                         dma-names = "tx", "rx";
 643                 };
 644
 645                 uart4: serial@4806e000 {
 646                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 647                         reg = <0x4806e000 0x100>;
 648                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 649                         ti,hwmods = "uart4";
 650                         clock-frequency = <48000000>;
 651                         status = "disabled";
 652                         dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
 653                         dma-names = "tx", "rx";
 654                 };
 655
 656                 uart5: serial@48066000 {
 657                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 658                         reg = <0x48066000 0x100>;
 659                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 660                         ti,hwmods = "uart5";
 661                         clock-frequency = <48000000>;
 662                         status = "disabled";
 663                         dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
 664                         dma-names = "tx", "rx";
 665                 };
 666
 667                 uart6: serial@48068000 {
 668                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 669                         reg = <0x48068000 0x100>;
 670                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 671                         ti,hwmods = "uart6";
 672                         clock-frequency = <48000000>;
 673                         status = "disabled";
 674                         dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
 675                         dma-names = "tx", "rx";
 676                 };
 677
 678                 uart7: serial@48420000 {
 679                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 680                         reg = <0x48420000 0x100>;
 681                         interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
 682                         ti,hwmods = "uart7";
 683                         clock-frequency = <48000000>;
 684                         status = "disabled";
 685                 };
 686
 687                 uart8: serial@48422000 {
 688                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 689                         reg = <0x48422000 0x100>;
 690                         interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
 691                         ti,hwmods = "uart8";
 692                         clock-frequency = <48000000>;
 693                         status = "disabled";
 694                 };
 695
 696                 uart9: serial@48424000 {
 697                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 698                         reg = <0x48424000 0x100>;
 699                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
 700                         ti,hwmods = "uart9";
 701                         clock-frequency = <48000000>;
 702                         status = "disabled";
 703                 };
 704
 705                 uart10: serial@4ae2b000 {
 706                         compatible = "ti,dra742-uart", "ti,omap4-uart";
 707                         reg = <0x4ae2b000 0x100>;
 708                         interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 709                         ti,hwmods = "uart10";
 710                         clock-frequency = <48000000>;
 711                         status = "disabled";
 712                 };
 713
 714                 mailbox1: mailbox@4a0f4000 {
 715                         compatible = "ti,omap4-mailbox";
 716                         reg = <0x4a0f4000 0x200>;
 717                         interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 718                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 719                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 720                         ti,hwmods = "mailbox1";
 721                         #mbox-cells = <1>;
 722                         ti,mbox-num-users = <3>;
 723                         ti,mbox-num-fifos = <8>;
 724                         status = "disabled";
 725                 };
 726
 727                 mailbox2: mailbox@4883a000 {
 728                         compatible = "ti,omap4-mailbox";
 729                         reg = <0x4883a000 0x200>;
 730                         interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
 731                                      <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
 732                                      <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
 733                                      <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
 734                         ti,hwmods = "mailbox2";
 735                         #mbox-cells = <1>;
 736                         ti,mbox-num-users = <4>;
 737                         ti,mbox-num-fifos = <12>;
 738                         status = "disabled";
 739                 };
 740
 741                 mailbox3: mailbox@4883c000 {
 742                         compatible = "ti,omap4-mailbox";
 743                         reg = <0x4883c000 0x200>;
 744                         interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
 745                                      <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
 746                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
 747                                      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
 748                         ti,hwmods = "mailbox3";
 749                         #mbox-cells = <1>;
 750                         ti,mbox-num-users = <4>;
 751                         ti,mbox-num-fifos = <12>;
 752                         status = "disabled";
 753                 };
 754
 755                 mailbox4: mailbox@4883e000 {
 756                         compatible = "ti,omap4-mailbox";
 757                         reg = <0x4883e000 0x200>;
 758                         interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
 759                                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
 760                                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
 761                                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
 762                         ti,hwmods = "mailbox4";
 763                         #mbox-cells = <1>;
 764                         ti,mbox-num-users = <4>;
 765                         ti,mbox-num-fifos = <12>;
 766                         status = "disabled";
 767                 };
 768
 769                 mailbox5: mailbox@48840000 {
 770                         compatible = "ti,omap4-mailbox";
 771                         reg = <0x48840000 0x200>;
 772                         interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
 773                                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
 774                                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
 775                                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
 776                         ti,hwmods = "mailbox5";
 777                         #mbox-cells = <1>;
 778                         ti,mbox-num-users = <4>;
 779                         ti,mbox-num-fifos = <12>;
 780                         status = "disabled";
 781                 };
 782
 783                 mailbox6: mailbox@48842000 {
 784                         compatible = "ti,omap4-mailbox";
 785                         reg = <0x48842000 0x200>;
 786                         interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
 787                                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
 788                                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
 789                                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
 790                         ti,hwmods = "mailbox6";
 791                         #mbox-cells = <1>;
 792                         ti,mbox-num-users = <4>;
 793                         ti,mbox-num-fifos = <12>;
 794                         status = "disabled";
 795                 };
 796
 797                 mailbox7: mailbox@48844000 {
 798                         compatible = "ti,omap4-mailbox";
 799                         reg = <0x48844000 0x200>;
 800                         interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
 801                                      <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
 802                                      <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
 803                                      <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
 804                         ti,hwmods = "mailbox7";
 805                         #mbox-cells = <1>;
 806                         ti,mbox-num-users = <4>;
 807                         ti,mbox-num-fifos = <12>;
 808                         status = "disabled";
 809                 };
 810
 811                 mailbox8: mailbox@48846000 {
 812                         compatible = "ti,omap4-mailbox";
 813                         reg = <0x48846000 0x200>;
 814                         interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
 815                                      <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
 816                                      <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
 817                                      <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
 818                         ti,hwmods = "mailbox8";
 819                         #mbox-cells = <1>;
 820                         ti,mbox-num-users = <4>;
 821                         ti,mbox-num-fifos = <12>;
 822                         status = "disabled";
 823                 };
 824
 825                 mailbox9: mailbox@4885e000 {
 826                         compatible = "ti,omap4-mailbox";
 827                         reg = <0x4885e000 0x200>;
 828                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
 829                                      <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
 830                                      <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
 831                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 832                         ti,hwmods = "mailbox9";
 833                         #mbox-cells = <1>;
 834                         ti,mbox-num-users = <4>;
 835                         ti,mbox-num-fifos = <12>;
 836                         status = "disabled";
 837                 };
 838
 839                 mailbox10: mailbox@48860000 {
 840                         compatible = "ti,omap4-mailbox";
 841                         reg = <0x48860000 0x200>;
 842                         interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
 843                                      <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
 844                                      <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
 845                                      <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 846                         ti,hwmods = "mailbox10";
 847                         #mbox-cells = <1>;
 848                         ti,mbox-num-users = <4>;
 849                         ti,mbox-num-fifos = <12>;
 850                         status = "disabled";
 851                 };
 852
 853                 mailbox11: mailbox@48862000 {
 854                         compatible = "ti,omap4-mailbox";
 855                         reg = <0x48862000 0x200>;
 856                         interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
 857                                      <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
 858                                      <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
 859                                      <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
 860                         ti,hwmods = "mailbox11";
 861                         #mbox-cells = <1>;
 862                         ti,mbox-num-users = <4>;
 863                         ti,mbox-num-fifos = <12>;
 864                         status = "disabled";
 865                 };
 866
 867                 mailbox12: mailbox@48864000 {
 868                         compatible = "ti,omap4-mailbox";
 869                         reg = <0x48864000 0x200>;
 870                         interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
 871                                      <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
 872                                      <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
 873                                      <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
 874                         ti,hwmods = "mailbox12";
 875                         #mbox-cells = <1>;
 876                         ti,mbox-num-users = <4>;
 877                         ti,mbox-num-fifos = <12>;
 878                         status = "disabled";
 879                 };
 880
 881                 mailbox13: mailbox@48802000 {
 882                         compatible = "ti,omap4-mailbox";
 883                         reg = <0x48802000 0x200>;
 884                         interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
 885                                      <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
 886                                      <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
 887                                      <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
 888                         ti,hwmods = "mailbox13";
 889                         #mbox-cells = <1>;
 890                         ti,mbox-num-users = <4>;
 891                         ti,mbox-num-fifos = <12>;
 892                         status = "disabled";
 893                 };
 894
 895                 timer1: timer@4ae18000 {
 896                         compatible = "ti,omap5430-timer";
 897                         reg = <0x4ae18000 0x80>;
 898                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 899                         ti,hwmods = "timer1";
 900                         ti,timer-alwon;
 901                         clock-names = "fck";
 902                         clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
 903                 };
 904
 905                 timer2: timer@48032000 {
 906                         compatible = "ti,omap5430-timer";
 907                         reg = <0x48032000 0x80>;
 908                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 909                         ti,hwmods = "timer2";
 910                 };
 911
 912                 timer3: timer@48034000 {
 913                         compatible = "ti,omap5430-timer";
 914                         reg = <0x48034000 0x80>;
 915                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 916                         ti,hwmods = "timer3";
 917                 };
 918
 919                 timer4: timer@48036000 {
 920                         compatible = "ti,omap5430-timer";
 921                         reg = <0x48036000 0x80>;
 922                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 923                         ti,hwmods = "timer4";
 924                 };
 925
 926                 timer5: timer@48820000 {
 927                         compatible = "ti,omap5430-timer";
 928                         reg = <0x48820000 0x80>;
 929                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 930                         ti,hwmods = "timer5";
 931                 };
 932
 933                 timer6: timer@48822000 {
 934                         compatible = "ti,omap5430-timer";
 935                         reg = <0x48822000 0x80>;
 936                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 937                         ti,hwmods = "timer6";
 938                 };
 939
 940                 timer7: timer@48824000 {
 941                         compatible = "ti,omap5430-timer";
 942                         reg = <0x48824000 0x80>;
 943                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 944                         ti,hwmods = "timer7";
 945                 };
 946
 947                 timer8: timer@48826000 {
 948                         compatible = "ti,omap5430-timer";
 949                         reg = <0x48826000 0x80>;
 950                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 951                         ti,hwmods = "timer8";
 952                 };
 953
 954                 timer9: timer@4803e000 {
 955                         compatible = "ti,omap5430-timer";
 956                         reg = <0x4803e000 0x80>;
 957                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 958                         ti,hwmods = "timer9";
 959                 };
 960
 961                 timer10: timer@48086000 {
 962                         compatible = "ti,omap5430-timer";
 963                         reg = <0x48086000 0x80>;
 964                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 965                         ti,hwmods = "timer10";
 966                 };
 967
 968                 timer11: timer@48088000 {
 969                         compatible = "ti,omap5430-timer";
 970                         reg = <0x48088000 0x80>;
 971                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 972                         ti,hwmods = "timer11";
 973                 };
 974
 975                 timer12: timer@4ae20000 {
 976                         compatible = "ti,omap5430-timer";
 977                         reg = <0x4ae20000 0x80>;
 978                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 979                         ti,hwmods = "timer12";
 980                         ti,timer-alwon;
 981                         ti,timer-secure;
 982                 };
 983
 984                 timer13: timer@48828000 {
 985                         compatible = "ti,omap5430-timer";
 986                         reg = <0x48828000 0x80>;
 987                         interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 988                         ti,hwmods = "timer13";
 989                 };
 990
 991                 timer14: timer@4882a000 {
 992                         compatible = "ti,omap5430-timer";
 993                         reg = <0x4882a000 0x80>;
 994                         interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 995                         ti,hwmods = "timer14";
 996                 };
 997
 998                 timer15: timer@4882c000 {
 999                         compatible = "ti,omap5430-timer";
1000                         reg = <0x4882c000 0x80>;
1001                         interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
1002                         ti,hwmods = "timer15";
1003                 };
1004
1005                 timer16: timer@4882e000 {
1006                         compatible = "ti,omap5430-timer";
1007                         reg = <0x4882e000 0x80>;
1008                         interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
1009                         ti,hwmods = "timer16";
1010                 };
1011
1012                 wdt2: wdt@4ae14000 {
1013                         compatible = "ti,omap3-wdt";
1014                         reg = <0x4ae14000 0x80>;
1015                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1016                         ti,hwmods = "wd_timer2";
1017                 };
1018
1019                 hwspinlock: spinlock@4a0f6000 {
1020                         compatible = "ti,omap4-hwspinlock";
1021                         reg = <0x4a0f6000 0x1000>;
1022                         ti,hwmods = "spinlock";
1023                         #hwlock-cells = <1>;
1024                 };
1025
1026                 dmm@4e000000 {
1027                         compatible = "ti,omap5-dmm";
1028                         reg = <0x4e000000 0x800>;
1029                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1030                         ti,hwmods = "dmm";
1031                 };
1032
1033                 i2c1: i2c@48070000 {
1034                         compatible = "ti,omap4-i2c";
1035                         reg = <0x48070000 0x100>;
1036                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1037                         #address-cells = <1>;
1038                         #size-cells = <0>;
1039                         ti,hwmods = "i2c1";
1040                         status = "disabled";
1041                 };
1042
1043                 i2c2: i2c@48072000 {
1044                         compatible = "ti,omap4-i2c";
1045                         reg = <0x48072000 0x100>;
1046                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1047                         #address-cells = <1>;
1048                         #size-cells = <0>;
1049                         ti,hwmods = "i2c2";
1050                         status = "disabled";
1051                 };
1052
1053                 i2c3: i2c@48060000 {
1054                         compatible = "ti,omap4-i2c";
1055                         reg = <0x48060000 0x100>;
1056                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1057                         #address-cells = <1>;
1058                         #size-cells = <0>;
1059                         ti,hwmods = "i2c3";
1060                         status = "disabled";
1061                 };
1062
1063                 i2c4: i2c@4807a000 {
1064                         compatible = "ti,omap4-i2c";
1065                         reg = <0x4807a000 0x100>;
1066                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1067                         #address-cells = <1>;
1068                         #size-cells = <0>;
1069                         ti,hwmods = "i2c4";
1070                         status = "disabled";
1071                 };
1072
1073                 i2c5: i2c@4807c000 {
1074                         compatible = "ti,omap4-i2c";
1075                         reg = <0x4807c000 0x100>;
1076                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1077                         #address-cells = <1>;
1078                         #size-cells = <0>;
1079                         ti,hwmods = "i2c5";
1080                         status = "disabled";
1081                 };
1082
1083                 mmc1: mmc@4809c000 {
1084                         compatible = "ti,dra7-sdhci";
1085                         reg = <0x4809c000 0x400>;
1086                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1087                         ti,hwmods = "mmc1";
1088                         status = "disabled";
1089                         pbias-supply = <&pbias_mmc_reg>;
1090                         max-frequency = <192000000>;
1091                         mmc-ddr-1_8v;
1092                         mmc-ddr-3_3v;
1093                 };
1094
1095                 hdqw1w: 1w@480b2000 {
1096                         compatible = "ti,omap3-1w";
1097                         reg = <0x480b2000 0x1000>;
1098                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1099                         ti,hwmods = "hdq1w";
1100                 };
1101
1102                 mmc2: mmc@480b4000 {
1103                         compatible = "ti,dra7-sdhci";
1104                         reg = <0x480b4000 0x400>;
1105                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1106                         ti,hwmods = "mmc2";
1107                         status = "disabled";
1108                         max-frequency = <192000000>;
1109                         /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
1110                         sdhci-caps-mask = <0x7 0x0>;
1111                         mmc-hs200-1_8v;
1112                         mmc-ddr-1_8v;
1113                         mmc-ddr-3_3v;
1114                 };
1115
1116                 mmc3: mmc@480ad000 {
1117                         compatible = "ti,dra7-sdhci";
1118                         reg = <0x480ad000 0x400>;
1119                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1120                         ti,hwmods = "mmc3";
1121                         status = "disabled";
1122                         /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
1123                         max-frequency = <64000000>;
1124                         /* SDMA is not supported */
1125                         sdhci-caps-mask = <0x0 0x400000>;
1126                 };
1127
1128                 mmc4: mmc@480d1000 {
1129                         compatible = "ti,dra7-sdhci";
1130                         reg = <0x480d1000 0x400>;
1131                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1132                         ti,hwmods = "mmc4";
1133                         status = "disabled";
1134                         max-frequency = <192000000>;
1135                         /* SDMA is not supported */
1136                         sdhci-caps-mask = <0x0 0x400000>;
1137                 };
1138
1139                 mmu0_dsp1: mmu@40d01000 {
1140                         compatible = "ti,dra7-dsp-iommu";
1141                         reg = <0x40d01000 0x100>;
1142                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1143                         ti,hwmods = "mmu0_dsp1";
1144                         #iommu-cells = <0>;
1145                         ti,syscon-mmuconfig = <&dsp1_system 0x0>;
1146                         status = "disabled";
1147                 };
1148
1149                 mmu1_dsp1: mmu@40d02000 {
1150                         compatible = "ti,dra7-dsp-iommu";
1151                         reg = <0x40d02000 0x100>;
1152                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
1153                         ti,hwmods = "mmu1_dsp1";
1154                         #iommu-cells = <0>;
1155                         ti,syscon-mmuconfig = <&dsp1_system 0x1>;
1156                         status = "disabled";
1157                 };
1158
1159                 mmu_ipu1: mmu@58882000 {
1160                         compatible = "ti,dra7-iommu";
1161                         reg = <0x58882000 0x100>;
1162                         interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
1163                         ti,hwmods = "mmu_ipu1";
1164                         #iommu-cells = <0>;
1165                         ti,iommu-bus-err-back;
1166                         status = "disabled";
1167                 };
1168
1169                 mmu_ipu2: mmu@55082000 {
1170                         compatible = "ti,dra7-iommu";
1171                         reg = <0x55082000 0x100>;
1172                         interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
1173                         ti,hwmods = "mmu_ipu2";
1174                         #iommu-cells = <0>;
1175                         ti,iommu-bus-err-back;
1176                         status = "disabled";
1177                 };
1178
1179                 abb_mpu: regulator-abb-mpu {
1180                         compatible = "ti,abb-v3";
1181                         regulator-name = "abb_mpu";
1182                         #address-cells = <0>;
1183                         #size-cells = <0>;
1184                         clocks = <&sys_clkin1>;
1185                         ti,settling-time = <50>;
1186                         ti,clock-cycles = <16>;
1187
1188                         reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
1189                               <0x4ae06014 0x4>, <0x4a003b20 0xc>,
1190                               <0x4ae0c158 0x4>;
1191                         reg-names = "setup-address", "control-address",
1192                                     "int-address", "efuse-address",
1193                                     "ldo-address";
1194                         ti,tranxdone-status-mask = <0x80>;
1195                         /* LDOVBBMPU_FBB_MUX_CTRL */
1196                         ti,ldovbb-override-mask = <0x400>;
1197                         /* LDOVBBMPU_FBB_VSET_OUT */
1198                         ti,ldovbb-vset-mask = <0x1F>;
1199
1200                         /*
1201                          * NOTE: only FBB mode used but actual vset will
1202                          * determine final biasing
1203                          */
1204                         ti,abb_info = <
1205                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1206                         1060000         0       0x0     0 0x02000000 0x01F00000
1207                         1160000         0       0x4     0 0x02000000 0x01F00000
1208                         1210000         0       0x8     0 0x02000000 0x01F00000
1209                         >;
1210                 };
1211
1212                 abb_ivahd: regulator-abb-ivahd {
1213                         compatible = "ti,abb-v3";
1214                         regulator-name = "abb_ivahd";
1215                         #address-cells = <0>;
1216                         #size-cells = <0>;
1217                         clocks = <&sys_clkin1>;
1218                         ti,settling-time = <50>;
1219                         ti,clock-cycles = <16>;
1220
1221                         reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
1222                               <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
1223                               <0x4a002470 0x4>;
1224                         reg-names = "setup-address", "control-address",
1225                                     "int-address", "efuse-address",
1226                                     "ldo-address";
1227                         ti,tranxdone-status-mask = <0x40000000>;
1228                         /* LDOVBBIVA_FBB_MUX_CTRL */
1229                         ti,ldovbb-override-mask = <0x400>;
1230                         /* LDOVBBIVA_FBB_VSET_OUT */
1231                         ti,ldovbb-vset-mask = <0x1F>;
1232
1233                         /*
1234                          * NOTE: only FBB mode used but actual vset will
1235                          * determine final biasing
1236                          */
1237                         ti,abb_info = <
1238                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1239                         1055000         0       0x0     0 0x02000000 0x01F00000
1240                         1150000         0       0x4     0 0x02000000 0x01F00000
1241                         1250000         0       0x8     0 0x02000000 0x01F00000
1242                         >;
1243                 };
1244
1245                 abb_dspeve: regulator-abb-dspeve {
1246                         compatible = "ti,abb-v3";
1247                         regulator-name = "abb_dspeve";
1248                         #address-cells = <0>;
1249                         #size-cells = <0>;
1250                         clocks = <&sys_clkin1>;
1251                         ti,settling-time = <50>;
1252                         ti,clock-cycles = <16>;
1253
1254                         reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
1255                               <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
1256                               <0x4a00246c 0x4>;
1257                         reg-names = "setup-address", "control-address",
1258                                     "int-address", "efuse-address",
1259                                     "ldo-address";
1260                         ti,tranxdone-status-mask = <0x20000000>;
1261                         /* LDOVBBDSPEVE_FBB_MUX_CTRL */
1262                         ti,ldovbb-override-mask = <0x400>;
1263                         /* LDOVBBDSPEVE_FBB_VSET_OUT */
1264                         ti,ldovbb-vset-mask = <0x1F>;
1265
1266                         /*
1267                          * NOTE: only FBB mode used but actual vset will
1268                          * determine final biasing
1269                          */
1270                         ti,abb_info = <
1271                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1272                         1055000         0       0x0     0 0x02000000 0x01F00000
1273                         1150000         0       0x4     0 0x02000000 0x01F00000
1274                         1250000         0       0x8     0 0x02000000 0x01F00000
1275                         >;
1276                 };
1277
1278                 abb_gpu: regulator-abb-gpu {
1279                         compatible = "ti,abb-v3";
1280                         regulator-name = "abb_gpu";
1281                         #address-cells = <0>;
1282                         #size-cells = <0>;
1283                         clocks = <&sys_clkin1>;
1284                         ti,settling-time = <50>;
1285                         ti,clock-cycles = <16>;
1286
1287                         reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
1288                               <0x4ae06010 0x4>, <0x4a003b08 0xc>,
1289                               <0x4ae0c154 0x4>;
1290                         reg-names = "setup-address", "control-address",
1291                                     "int-address", "efuse-address",
1292                                     "ldo-address";
1293                         ti,tranxdone-status-mask = <0x10000000>;
1294                         /* LDOVBBGPU_FBB_MUX_CTRL */
1295                         ti,ldovbb-override-mask = <0x400>;
1296                         /* LDOVBBGPU_FBB_VSET_OUT */
1297                         ti,ldovbb-vset-mask = <0x1F>;
1298
1299                         /*
1300                          * NOTE: only FBB mode used but actual vset will
1301                          * determine final biasing
1302                          */
1303                         ti,abb_info = <
1304                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1305                         1090000         0       0x0     0 0x02000000 0x01F00000
1306                         1210000         0       0x4     0 0x02000000 0x01F00000
1307                         1280000         0       0x8     0 0x02000000 0x01F00000
1308                         >;
1309                 };
1310
1311                 mcspi1: spi@48098000 {
1312                         compatible = "ti,omap4-mcspi";
1313                         reg = <0x48098000 0x200>;
1314                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1315                         #address-cells = <1>;
1316                         #size-cells = <0>;
1317                         ti,hwmods = "mcspi1";
1318                         ti,spi-num-cs = <4>;
1319                         dmas = <&sdma_xbar 35>,
1320                                <&sdma_xbar 36>,
1321                                <&sdma_xbar 37>,
1322                                <&sdma_xbar 38>,
1323                                <&sdma_xbar 39>,
1324                                <&sdma_xbar 40>,
1325                                <&sdma_xbar 41>,
1326                                <&sdma_xbar 42>;
1327                         dma-names = "tx0", "rx0", "tx1", "rx1",
1328                                     "tx2", "rx2", "tx3", "rx3";
1329                         status = "disabled";
1330                 };
1331
1332                 mcspi2: spi@4809a000 {
1333                         compatible = "ti,omap4-mcspi";
1334                         reg = <0x4809a000 0x200>;
1335                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1336                         #address-cells = <1>;
1337                         #size-cells = <0>;
1338                         ti,hwmods = "mcspi2";
1339                         ti,spi-num-cs = <2>;
1340                         dmas = <&sdma_xbar 43>,
1341                                <&sdma_xbar 44>,
1342                                <&sdma_xbar 45>,
1343                                <&sdma_xbar 46>;
1344                         dma-names = "tx0", "rx0", "tx1", "rx1";
1345                         status = "disabled";
1346                 };
1347
1348                 mcspi3: spi@480b8000 {
1349                         compatible = "ti,omap4-mcspi";
1350                         reg = <0x480b8000 0x200>;
1351                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1352                         #address-cells = <1>;
1353                         #size-cells = <0>;
1354                         ti,hwmods = "mcspi3";
1355                         ti,spi-num-cs = <2>;
1356                         dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
1357                         dma-names = "tx0", "rx0";
1358                         status = "disabled";
1359                 };
1360
1361                 mcspi4: spi@480ba000 {
1362                         compatible = "ti,omap4-mcspi";
1363                         reg = <0x480ba000 0x200>;
1364                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
1365                         #address-cells = <1>;
1366                         #size-cells = <0>;
1367                         ti,hwmods = "mcspi4";
1368                         ti,spi-num-cs = <1>;
1369                         dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
1370                         dma-names = "tx0", "rx0";
1371                         status = "disabled";
1372                 };
1373
1374                 qspi: spi@4b300000 {
1375                         compatible = "ti,dra7xxx-qspi";
1376                         reg = <0x4b300000 0x100>,
1377                               <0x5c000000 0x4000000>;
1378                         reg-names = "qspi_base", "qspi_mmap";
1379                         syscon-chipselects = <&scm_conf 0x558>;
1380                         #address-cells = <1>;
1381                         #size-cells = <0>;
1382                         ti,hwmods = "qspi";
1383                         clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>;
1384                         clock-names = "fck";
1385                         num-cs = <4>;
1386                         interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
1387                         status = "disabled";
1388                 };
1389
1390                 /* OCP2SCP3 */
1391                 ocp2scp@4a090000 {
1392                         compatible = "ti,omap-ocp2scp";
1393                         #address-cells = <1>;
1394                         #size-cells = <1>;
1395                         ranges;
1396                         reg = <0x4a090000 0x20>;
1397                         ti,hwmods = "ocp2scp3";
1398                         sata_phy: phy@4a096000 {
1399                                 compatible = "ti,phy-pipe3-sata";
1400                                 reg = <0x4A096000 0x80>, /* phy_rx */
1401                                       <0x4A096400 0x64>, /* phy_tx */
1402                                       <0x4A096800 0x40>; /* pll_ctrl */
1403                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1404                                 syscon-phy-power = <&scm_conf 0x374>;
1405                                 clocks = <&sys_clkin1>,
1406                                          <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
1407                                 clock-names = "sysclk", "refclk";
1408                                 syscon-pllreset = <&scm_conf 0x3fc>;
1409                                 #phy-cells = <0>;
1410                         };
1411
1412                         pcie1_phy: pciephy@4a094000 {
1413                                 compatible = "ti,phy-pipe3-pcie";
1414                                 reg = <0x4a094000 0x80>, /* phy_rx */
1415                                       <0x4a094400 0x64>; /* phy_tx */
1416                                 reg-names = "phy_rx", "phy_tx";
1417                                 syscon-phy-power = <&scm_conf_pcie 0x1c>;
1418                                 syscon-pcs = <&scm_conf_pcie 0x10>;
1419                                 clocks = <&dpll_pcie_ref_ck>,
1420                                          <&dpll_pcie_ref_m2ldo_ck>,
1421                                          <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>,
1422                                          <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>,
1423                                          <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>,
1424                                          <&optfclk_pciephy_div>,
1425                                          <&sys_clkin1>;
1426                                 clock-names = "dpll_ref", "dpll_ref_m2",
1427                                               "wkupclk", "refclk",
1428                                               "div-clk", "phy-div", "sysclk";
1429                                 #phy-cells = <0>;
1430                         };
1431
1432                         pcie2_phy: pciephy@4a095000 {
1433                                 compatible = "ti,phy-pipe3-pcie";
1434                                 reg = <0x4a095000 0x80>, /* phy_rx */
1435                                       <0x4a095400 0x64>; /* phy_tx */
1436                                 reg-names = "phy_rx", "phy_tx";
1437                                 syscon-phy-power = <&scm_conf_pcie 0x20>;
1438                                 syscon-pcs = <&scm_conf_pcie 0x10>;
1439                                 clocks = <&dpll_pcie_ref_ck>,
1440                                          <&dpll_pcie_ref_m2ldo_ck>,
1441                                          <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>,
1442                                          <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>,
1443                                          <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>,
1444                                          <&optfclk_pciephy_div>,
1445                                          <&sys_clkin1>;
1446                                 clock-names = "dpll_ref", "dpll_ref_m2",
1447                                               "wkupclk", "refclk",
1448                                               "div-clk", "phy-div", "sysclk";
1449                                 #phy-cells = <0>;
1450                                 status = "disabled";
1451                         };
1452                 };
1453
1454                 sata: sata@4a141100 {
1455                         compatible = "snps,dwc-ahci";
1456                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
1457                         interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1458                         phys = <&sata_phy>;
1459                         phy-names = "sata-phy";
1460                         clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
1461                         ti,hwmods = "sata";
1462                         ports-implemented = <0x1>;
1463                 };
1464
1465                 rtc: rtc@48838000 {
1466                         compatible = "ti,am3352-rtc";
1467                         reg = <0x48838000 0x100>;
1468                         interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1469                                      <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1470                         ti,hwmods = "rtcss";
1471                         clocks = <&sys_32k_ck>;
1472                 };
1473
1474                 /* OCP2SCP1 */
1475                 ocp2scp@4a080000 {
1476                         compatible = "ti,omap-ocp2scp";
1477                         #address-cells = <1>;
1478                         #size-cells = <1>;
1479                         ranges;
1480                         reg = <0x4a080000 0x20>;
1481                         ti,hwmods = "ocp2scp1";
1482
1483                         usb2_phy1: phy@4a084000 {
1484                                 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
1485                                 reg = <0x4a084000 0x400>;
1486                                 syscon-phy-power = <&scm_conf 0x300>;
1487                                 clocks = <&usb_phy1_always_on_clk32k>,
1488                                          <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
1489                                 clock-names =   "wkupclk",
1490                                                 "refclk";
1491                                 #phy-cells = <0>;
1492                         };
1493
1494                         usb2_phy2: phy@4a085000 {
1495                                 compatible = "ti,dra7x-usb2-phy2",
1496                                              "ti,omap-usb2";
1497                                 reg = <0x4a085000 0x400>;
1498                                 syscon-phy-power = <&scm_conf 0xe74>;
1499                                 clocks = <&usb_phy2_always_on_clk32k>,
1500                                          <&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>;
1501                                 clock-names =   "wkupclk",
1502                                                 "refclk";
1503                                 #phy-cells = <0>;
1504                         };
1505
1506                         usb3_phy1: phy@4a084400 {
1507                                 compatible = "ti,omap-usb3";
1508                                 reg = <0x4a084400 0x80>,
1509                                       <0x4a084800 0x64>,
1510                                       <0x4a084c00 0x40>;
1511                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1512                                 syscon-phy-power = <&scm_conf 0x370>;
1513                                 clocks = <&usb_phy3_always_on_clk32k>,
1514                                          <&sys_clkin1>,
1515                                          <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
1516                                 clock-names =   "wkupclk",
1517                                                 "sysclk",
1518                                                 "refclk";
1519                                 #phy-cells = <0>;
1520                         };
1521                 };
1522
1523                 target-module@4a0dd000 {
1524                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
1525                         ti,hwmods = "smartreflex_core";
1526                         reg = <0x4a0dd038 0x4>;
1527                         reg-names = "sysc";
1528                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
1529                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1530                                         <SYSC_IDLE_NO>,
1531                                         <SYSC_IDLE_SMART>,
1532                                         <SYSC_IDLE_SMART_WKUP>;
1533                         clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_CORE_CLKCTRL 0>;
1534                         clock-names = "fck";
1535                         #address-cells = <1>;
1536                         #size-cells = <1>;
1537                         ranges = <0 0x4a0dd000 0x001000>;
1538
1539                         /* SmartReflex child device marked reserved in TRM */
1540                 };
1541
1542                 target-module@4a0d9000 {
1543                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
1544                         ti,hwmods = "smartreflex_mpu";
1545                         reg = <0x4a0d9038 0x4>;
1546                         reg-names = "sysc";
1547                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
1548                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1549                                         <SYSC_IDLE_NO>,
1550                                         <SYSC_IDLE_SMART>,
1551                                         <SYSC_IDLE_SMART_WKUP>;
1552                         clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_MPU_CLKCTRL 0>;
1553                         clock-names = "fck";
1554                         #address-cells = <1>;
1555                         #size-cells = <1>;
1556                         ranges = <0 0x4a0d9000 0x001000>;
1557
1558                         /* SmartReflex child device marked reserved in TRM */
1559                 };
1560
1561                 omap_dwc3_1: omap_dwc3_1@48880000 {
1562                         compatible = "ti,dwc3";
1563                         ti,hwmods = "usb_otg_ss1";
1564                         reg = <0x48880000 0x10000>;
1565                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1566                         #address-cells = <1>;
1567                         #size-cells = <1>;
1568                         utmi-mode = <2>;
1569                         ranges;
1570                         usb1: usb@48890000 {
1571                                 compatible = "snps,dwc3";
1572                                 reg = <0x48890000 0x17000>;
1573                                 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1574                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1575                                              <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1576                                 interrupt-names = "peripheral",
1577                                                   "host",
1578                                                   "otg";
1579                                 phys = <&usb2_phy1>, <&usb3_phy1>;
1580                                 phy-names = "usb2-phy", "usb3-phy";
1581                                 maximum-speed = "super-speed";
1582                                 dr_mode = "otg";
1583                                 snps,dis_u3_susphy_quirk;
1584                                 snps,dis_u2_susphy_quirk;
1585                         };
1586                 };
1587
1588                 omap_dwc3_2: omap_dwc3_2@488c0000 {
1589                         compatible = "ti,dwc3";
1590                         ti,hwmods = "usb_otg_ss2";
1591                         reg = <0x488c0000 0x10000>;
1592                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1593                         #address-cells = <1>;
1594                         #size-cells = <1>;
1595                         utmi-mode = <2>;
1596                         ranges;
1597                         usb2: usb@488d0000 {
1598                                 compatible = "snps,dwc3";
1599                                 reg = <0x488d0000 0x17000>;
1600                                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1601                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1602                                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1603                                 interrupt-names = "peripheral",
1604                                                   "host",
1605                                                   "otg";
1606                                 phys = <&usb2_phy2>;
1607                                 phy-names = "usb2-phy";
1608                                 maximum-speed = "high-speed";
1609                                 dr_mode = "otg";
1610                                 snps,dis_u3_susphy_quirk;
1611                                 snps,dis_u2_susphy_quirk;
1612                                 snps,dis_metastability_quirk;
1613                         };
1614                 };
1615
1616                 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1617                 omap_dwc3_3: omap_dwc3_3@48900000 {
1618                         compatible = "ti,dwc3";
1619                         ti,hwmods = "usb_otg_ss3";
1620                         reg = <0x48900000 0x10000>;
1621                         interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1622                         #address-cells = <1>;
1623                         #size-cells = <1>;
1624                         utmi-mode = <2>;
1625                         ranges;
1626                         status = "disabled";
1627                         usb3: usb@48910000 {
1628                                 compatible = "snps,dwc3";
1629                                 reg = <0x48910000 0x17000>;
1630                                 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1631                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1632                                              <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1633                                 interrupt-names = "peripheral",
1634                                                   "host",
1635                                                   "otg";
1636                                 maximum-speed = "high-speed";
1637                                 dr_mode = "otg";
1638                                 snps,dis_u3_susphy_quirk;
1639                                 snps,dis_u2_susphy_quirk;
1640                         };
1641                 };
1642
1643                 elm: elm@48078000 {
1644                         compatible = "ti,am3352-elm";
1645                         reg = <0x48078000 0xfc0>;      /* device IO registers */
1646                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1647                         ti,hwmods = "elm";
1648                         status = "disabled";
1649                 };
1650
1651                 gpmc: gpmc@50000000 {
1652                         compatible = "ti,am3352-gpmc";
1653                         ti,hwmods = "gpmc";
1654                         reg = <0x50000000 0x37c>;      /* device IO registers */
1655                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1656                         dmas = <&edma_xbar 4 0>;
1657                         dma-names = "rxtx";
1658                         gpmc,num-cs = <8>;
1659                         gpmc,num-waitpins = <2>;
1660                         #address-cells = <2>;
1661                         #size-cells = <1>;
1662                         interrupt-controller;
1663                         #interrupt-cells = <2>;
1664                         gpio-controller;
1665                         #gpio-cells = <2>;
1666                         status = "disabled";
1667                 };
1668
1669                 atl: atl@4843c000 {
1670                         compatible = "ti,dra7-atl";
1671                         reg = <0x4843c000 0x3ff>;
1672                         ti,hwmods = "atl";
1673                         ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1674                                              <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1675                         clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
1676                         clock-names = "fck";
1677                         status = "disabled";
1678                 };
1679
1680                 mcasp1: mcasp@48460000 {
1681                         compatible = "ti,dra7-mcasp-audio";
1682                         ti,hwmods = "mcasp1";
1683                         reg = <0x48460000 0x2000>,
1684                               <0x45800000 0x1000>;
1685                         reg-names = "mpu","dat";
1686                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1687                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1688                         interrupt-names = "tx", "rx";
1689                         dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
1690                         dma-names = "tx", "rx";
1691                         clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>,
1692                                  <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>;
1693                         clock-names = "fck", "ahclkx", "ahclkr";
1694                         status = "disabled";
1695                 };
1696
1697                 mcasp2: mcasp@48464000 {
1698                         compatible = "ti,dra7-mcasp-audio";
1699                         ti,hwmods = "mcasp2";
1700                         reg = <0x48464000 0x2000>,
1701                               <0x45c00000 0x1000>;
1702                         reg-names = "mpu","dat";
1703                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1704                                      <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
1705                         interrupt-names = "tx", "rx";
1706                         dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
1707                         dma-names = "tx", "rx";
1708                         clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>,
1709                                  <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>,
1710                                  <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>;
1711                         clock-names = "fck", "ahclkx", "ahclkr";
1712                         status = "disabled";
1713                 };
1714
1715                 mcasp3: mcasp@48468000 {
1716                         compatible = "ti,dra7-mcasp-audio";
1717                         ti,hwmods = "mcasp3";
1718                         reg = <0x48468000 0x2000>,
1719                               <0x46000000 0x1000>;
1720                         reg-names = "mpu","dat";
1721                         interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1722                                      <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1723                         interrupt-names = "tx", "rx";
1724                         dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
1725                         dma-names = "tx", "rx";
1726                         clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>,
1727                                  <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
1728                         clock-names = "fck", "ahclkx";
1729                         status = "disabled";
1730                 };
1731
1732                 mcasp4: mcasp@4846c000 {
1733                         compatible = "ti,dra7-mcasp-audio";
1734                         ti,hwmods = "mcasp4";
1735                         reg = <0x4846c000 0x2000>,
1736                               <0x48436000 0x1000>;
1737                         reg-names = "mpu","dat";
1738                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1739                                      <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1740                         interrupt-names = "tx", "rx";
1741                         dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
1742                         dma-names = "tx", "rx";
1743                         clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>,
1744                                  <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>;
1745                         clock-names = "fck", "ahclkx";
1746                         status = "disabled";
1747                 };
1748
1749                 mcasp5: mcasp@48470000 {
1750                         compatible = "ti,dra7-mcasp-audio";
1751                         ti,hwmods = "mcasp5";
1752                         reg = <0x48470000 0x2000>,
1753                               <0x4843a000 0x1000>;
1754                         reg-names = "mpu","dat";
1755                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1756                                      <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1757                         interrupt-names = "tx", "rx";
1758                         dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
1759                         dma-names = "tx", "rx";
1760                         clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>,
1761                                  <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>;
1762                         clock-names = "fck", "ahclkx";
1763                         status = "disabled";
1764                 };
1765
1766                 mcasp6: mcasp@48474000 {
1767                         compatible = "ti,dra7-mcasp-audio";
1768                         ti,hwmods = "mcasp6";
1769                         reg = <0x48474000 0x2000>,
1770                               <0x4844c000 0x1000>;
1771                         reg-names = "mpu","dat";
1772                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1773                                      <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1774                         interrupt-names = "tx", "rx";
1775                         dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
1776                         dma-names = "tx", "rx";
1777                         clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>,
1778                                  <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>;
1779                         clock-names = "fck", "ahclkx";
1780                         status = "disabled";
1781                 };
1782
1783                 mcasp7: mcasp@48478000 {
1784                         compatible = "ti,dra7-mcasp-audio";
1785                         ti,hwmods = "mcasp7";
1786                         reg = <0x48478000 0x2000>,
1787                               <0x48450000 0x1000>;
1788                         reg-names = "mpu","dat";
1789                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1790                                      <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1791                         interrupt-names = "tx", "rx";
1792                         dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
1793                         dma-names = "tx", "rx";
1794                         clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>,
1795                                  <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>;
1796                         clock-names = "fck", "ahclkx";
1797                         status = "disabled";
1798                 };
1799
1800                 mcasp8: mcasp@4847c000 {
1801                         compatible = "ti,dra7-mcasp-audio";
1802                         ti,hwmods = "mcasp8";
1803                         reg = <0x4847c000 0x2000>,
1804                               <0x48454000 0x1000>;
1805                         reg-names = "mpu","dat";
1806                         interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1807                                      <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
1808                         interrupt-names = "tx", "rx";
1809                         dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
1810                         dma-names = "tx", "rx";
1811                         clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>,
1812                                  <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>;
1813                         clock-names = "fck", "ahclkx";
1814                         status = "disabled";
1815                 };
1816
1817                 crossbar_mpu: crossbar@4a002a48 {
1818                         compatible = "ti,irq-crossbar";
1819                         reg = <0x4a002a48 0x130>;
1820                         interrupt-controller;
1821                         interrupt-parent = <&wakeupgen>;
1822                         #interrupt-cells = <3>;
1823                         ti,max-irqs = <160>;
1824                         ti,max-crossbar-sources = <MAX_SOURCES>;
1825                         ti,reg-size = <2>;
1826                         ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1827                         ti,irqs-skip = <10 133 139 140>;
1828                         ti,irqs-safe-map = <0>;
1829                 };
1830
1831                 mac: ethernet@48484000 {
1832                         compatible = "ti,dra7-cpsw","ti,cpsw";
1833                         ti,hwmods = "gmac";
1834                         clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>;
1835                         clock-names = "fck", "cpts";
1836                         cpdma_channels = <8>;
1837                         ale_entries = <1024>;
1838                         bd_ram_size = <0x2000>;
1839                         mac_control = <0x20>;
1840                         slaves = <2>;
1841                         active_slave = <0>;
1842                         cpts_clock_mult = <0x784CFE14>;
1843                         cpts_clock_shift = <29>;
1844                         reg = <0x48484000 0x1000
1845                                0x48485200 0x2E00>;
1846                         #address-cells = <1>;
1847                         #size-cells = <1>;
1848
1849                         /*
1850                          * Do not allow gating of cpsw clock as workaround
1851                          * for errata i877. Keeping internal clock disabled
1852                          * causes the device switching characteristics
1853                          * to degrade over time and eventually fail to meet
1854                          * the data manual delay time/skew specs.
1855                          */
1856                         ti,no-idle;
1857
1858                         /*
1859                          * rx_thresh_pend
1860                          * rx_pend
1861                          * tx_pend
1862                          * misc_pend
1863                          */
1864                         interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1865                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1866                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1867                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
1868                         ranges;
1869                         syscon = <&scm_conf>;
1870                         status = "disabled";
1871
1872                         davinci_mdio: mdio@48485000 {
1873                                 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
1874                                 #address-cells = <1>;
1875                                 #size-cells = <0>;
1876                                 ti,hwmods = "davinci_mdio";
1877                                 bus_freq = <1000000>;
1878                                 reg = <0x48485000 0x100>;
1879                         };
1880
1881                         cpsw_emac0: slave@48480200 {
1882                                 /* Filled in by U-Boot */
1883                                 mac-address = [ 00 00 00 00 00 00 ];
1884                         };
1885
1886                         cpsw_emac1: slave@48480300 {
1887                                 /* Filled in by U-Boot */
1888                                 mac-address = [ 00 00 00 00 00 00 ];
1889                         };
1890
1891                         phy_sel: cpsw-phy-sel@4a002554 {
1892                                 compatible = "ti,dra7xx-cpsw-phy-sel";
1893                                 reg= <0x4a002554 0x4>;
1894                                 reg-names = "gmii-sel";
1895                         };
1896                 };
1897
1898                 dcan1: can@4ae3c000 {
1899                         compatible = "ti,dra7-d_can";
1900                         ti,hwmods = "dcan1";
1901                         reg = <0x4ae3c000 0x2000>;
1902                         syscon-raminit = <&scm_conf 0x558 0>;
1903                         interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
1904                         clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>;
1905                         status = "disabled";
1906                 };
1907
1908                 dcan2: can@48480000 {
1909                         compatible = "ti,dra7-d_can";
1910                         ti,hwmods = "dcan2";
1911                         reg = <0x48480000 0x2000>;
1912                         syscon-raminit = <&scm_conf 0x558 1>;
1913                         interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1914                         clocks = <&sys_clkin1>;
1915                         status = "disabled";
1916                 };
1917
1918                 dss: dss@58000000 {
1919                         compatible = "ti,dra7-dss";
1920                         /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
1921                         /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
1922                         status = "disabled";
1923                         ti,hwmods = "dss_core";
1924                         /* CTRL_CORE_DSS_PLL_CONTROL */
1925                         syscon-pll-ctrl = <&scm_conf 0x538>;
1926                         #address-cells = <1>;
1927                         #size-cells = <1>;
1928                         ranges;
1929
1930                         dispc@58001000 {
1931                                 compatible = "ti,dra7-dispc";
1932                                 reg = <0x58001000 0x1000>;
1933                                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1934                                 ti,hwmods = "dss_dispc";
1935                                 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
1936                                 clock-names = "fck";
1937                                 /* CTRL_CORE_SMA_SW_1 */
1938                                 syscon-pol = <&scm_conf 0x534>;
1939                         };
1940
1941                         hdmi: encoder@58060000 {
1942                                 compatible = "ti,dra7-hdmi";
1943                                 reg = <0x58040000 0x200>,
1944                                       <0x58040200 0x80>,
1945                                       <0x58040300 0x80>,
1946                                       <0x58060000 0x19000>;
1947                                 reg-names = "wp", "pll", "phy", "core";
1948                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1949                                 status = "disabled";
1950                                 ti,hwmods = "dss_hdmi";
1951                                 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
1952                                          <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>;
1953                                 clock-names = "fck", "sys_clk";
1954                                 dmas = <&sdma_xbar 76>;
1955                                 dma-names = "audio_tx";
1956                         };
1957                 };
1958
1959                 epwmss0: epwmss@4843e000 {
1960                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1961                         reg = <0x4843e000 0x30>;
1962                         ti,hwmods = "epwmss0";
1963                         #address-cells = <1>;
1964                         #size-cells = <1>;
1965                         status = "disabled";
1966                         ranges;
1967
1968                         ehrpwm0: pwm@4843e200 {
1969                                 compatible = "ti,dra746-ehrpwm",
1970                                              "ti,am3352-ehrpwm";
1971                                 #pwm-cells = <3>;
1972                                 reg = <0x4843e200 0x80>;
1973                                 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
1974                                 clock-names = "tbclk", "fck";
1975                                 status = "disabled";
1976                         };
1977
1978                         ecap0: ecap@4843e100 {
1979                                 compatible = "ti,dra746-ecap",
1980                                              "ti,am3352-ecap";
1981                                 #pwm-cells = <3>;
1982                                 reg = <0x4843e100 0x80>;
1983                                 clocks = <&l4_root_clk_div>;
1984                                 clock-names = "fck";
1985                                 status = "disabled";
1986                         };
1987                 };
1988
1989                 epwmss1: epwmss@48440000 {
1990                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
1991                         reg = <0x48440000 0x30>;
1992                         ti,hwmods = "epwmss1";
1993                         #address-cells = <1>;
1994                         #size-cells = <1>;
1995                         status = "disabled";
1996                         ranges;
1997
1998                         ehrpwm1: pwm@48440200 {
1999                                 compatible = "ti,dra746-ehrpwm",
2000                                              "ti,am3352-ehrpwm";
2001                                 #pwm-cells = <3>;
2002                                 reg = <0x48440200 0x80>;
2003                                 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
2004                                 clock-names = "tbclk", "fck";
2005                                 status = "disabled";
2006                         };
2007
2008                         ecap1: ecap@48440100 {
2009                                 compatible = "ti,dra746-ecap",
2010                                              "ti,am3352-ecap";
2011                                 #pwm-cells = <3>;
2012                                 reg = <0x48440100 0x80>;
2013                                 clocks = <&l4_root_clk_div>;
2014                                 clock-names = "fck";
2015                                 status = "disabled";
2016                         };
2017                 };
2018
2019                 epwmss2: epwmss@48442000 {
2020                         compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2021                         reg = <0x48442000 0x30>;
2022                         ti,hwmods = "epwmss2";
2023                         #address-cells = <1>;
2024                         #size-cells = <1>;
2025                         status = "disabled";
2026                         ranges;
2027
2028                         ehrpwm2: pwm@48442200 {
2029                                 compatible = "ti,dra746-ehrpwm",
2030                                              "ti,am3352-ehrpwm";
2031                                 #pwm-cells = <3>;
2032                                 reg = <0x48442200 0x80>;
2033                                 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2034                                 clock-names = "tbclk", "fck";
2035                                 status = "disabled";
2036                         };
2037
2038                         ecap2: ecap@48442100 {
2039                                 compatible = "ti,dra746-ecap",
2040                                              "ti,am3352-ecap";
2041                                 #pwm-cells = <3>;
2042                                 reg = <0x48442100 0x80>;
2043                                 clocks = <&l4_root_clk_div>;
2044                                 clock-names = "fck";
2045                                 status = "disabled";
2046                         };
2047                 };
2048
2049                 aes1: aes@4b500000 {
2050                         compatible = "ti,omap4-aes";
2051                         ti,hwmods = "aes1";
2052                         reg = <0x4b500000 0xa0>;
2053                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
2054                         dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
2055                         dma-names = "tx", "rx";
2056                         clocks = <&l3_iclk_div>;
2057                         clock-names = "fck";
2058                 };
2059
2060                 aes2: aes@4b700000 {
2061                         compatible = "ti,omap4-aes";
2062                         ti,hwmods = "aes2";
2063                         reg = <0x4b700000 0xa0>;
2064                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
2065                         dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
2066                         dma-names = "tx", "rx";
2067                         clocks = <&l3_iclk_div>;
2068                         clock-names = "fck";
2069                 };
2070
2071                 des: des@480a5000 {
2072                         compatible = "ti,omap4-des";
2073                         ti,hwmods = "des";
2074                         reg = <0x480a5000 0xa0>;
2075                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2076                         dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
2077                         dma-names = "tx", "rx";
2078                         clocks = <&l3_iclk_div>;
2079                         clock-names = "fck";
2080                 };
2081
2082                 sham: sham@53100000 {
2083                         compatible = "ti,omap5-sham";
2084                         ti,hwmods = "sham";
2085                         reg = <0x4b101000 0x300>;
2086                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
2087                         dmas = <&edma_xbar 119 0>;
2088                         dma-names = "rx";
2089                         clocks = <&l3_iclk_div>;
2090                         clock-names = "fck";
2091                 };
2092
2093                 rng: rng@48090000 {
2094                         compatible = "ti,omap4-rng";
2095                         ti,hwmods = "rng";
2096                         reg = <0x48090000 0x2000>;
2097                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2098                         clocks = <&l3_iclk_div>;
2099                         clock-names = "fck";
2100                 };
2101
2102                 opp_supply_mpu: opp-supply@4a003b20 {
2103                         compatible = "ti,omap5-opp-supply";
2104                         reg = <0x4a003b20 0xc>;
2105                         ti,efuse-settings = <
2106                         /* uV   offset */
2107                         1060000 0x0
2108                         1160000 0x4
2109                         1210000 0x8
2110                         >;
2111                         ti,absolute-max-voltage-uv = <1500000>;
2112                 };
2113
2114         };
2115
2116         thermal_zones: thermal-zones {
2117                 #include "omap4-cpu-thermal.dtsi"
2118                 #include "omap5-gpu-thermal.dtsi"
2119                 #include "omap5-core-thermal.dtsi"
2120                 #include "dra7-dspeve-thermal.dtsi"
2121                 #include "dra7-iva-thermal.dtsi"
2122         };
2123
2124 };
2125
2126 &cpu_thermal {
2127         polling-delay = <500>; /* milliseconds */
2128         coefficients = <0 2000>;
2129 };
2130
2131 &gpu_thermal {
2132         coefficients = <0 2000>;
2133 };
2134
2135 &core_thermal {
2136         coefficients = <0 2000>;
2137 };
2138
2139 &dspeve_thermal {
2140         coefficients = <0 2000>;
2141 };
2142
2143 &iva_thermal {
2144         coefficients = <0 2000>;
2145 };
2146
2147 &cpu_crit {
2148         temperature = <120000>; /* milli Celsius */
2149 };
2150
2151 #include "dra7xx-clocks.dtsi"
2152
2153 &core_crit {
2154         temperature = <120000>; /* milli Celsius */
2155 };
2156
2157 &gpu_crit {
2158         temperature = <120000>; /* milli Celsius */
2159 };
2160
2161 &dspeve_crit {
2162         temperature = <120000>; /* milli Celsius */
2163 };
2164
2165 &iva_crit {
2166         temperature = <120000>; /* milli Celsius */
2167 };