arch/arm/boot/dts/dra7-l4.dtsi

   1 &l4_cfg {                                               /* 0x4a000000 */
   2         compatible = "ti,dra7-l4-cfg", "simple-bus";
   3         reg = <0x4a000000 0x800>,
   4               <0x4a000800 0x800>,
   5               <0x4a001000 0x1000>;
   6         reg-names = "ap", "la", "ia0";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         ranges = <0x00000000 0x4a000000 0x100000>,      /* segment 0 */
  10                  <0x00100000 0x4a100000 0x100000>,      /* segment 1 */
  11                  <0x00200000 0x4a200000 0x100000>;      /* segment 2 */
  12
  13         segment@0 {                                     /* 0x4a000000 */
  14                 compatible = "simple-bus";
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
  18                          <0x00000800 0x00000800 0x000800>,      /* ap 1 */
  19                          <0x00001000 0x00001000 0x001000>,      /* ap 2 */
  20                          <0x00002000 0x00002000 0x002000>,      /* ap 3 */
  21                          <0x00004000 0x00004000 0x001000>,      /* ap 4 */
  22                          <0x00005000 0x00005000 0x001000>,      /* ap 5 */
  23                          <0x00006000 0x00006000 0x001000>,      /* ap 6 */
  24                          <0x00008000 0x00008000 0x002000>,      /* ap 7 */
  25                          <0x0000a000 0x0000a000 0x001000>,      /* ap 8 */
  26                          <0x00056000 0x00056000 0x001000>,      /* ap 9 */
  27                          <0x00057000 0x00057000 0x001000>,      /* ap 10 */
  28                          <0x0005e000 0x0005e000 0x002000>,      /* ap 11 */
  29                          <0x00060000 0x00060000 0x001000>,      /* ap 12 */
  30                          <0x00080000 0x00080000 0x008000>,      /* ap 13 */
  31                          <0x00088000 0x00088000 0x001000>,      /* ap 14 */
  32                          <0x000a0000 0x000a0000 0x008000>,      /* ap 15 */
  33                          <0x000a8000 0x000a8000 0x001000>,      /* ap 16 */
  34                          <0x000d9000 0x000d9000 0x001000>,      /* ap 17 */
  35                          <0x000da000 0x000da000 0x001000>,      /* ap 18 */
  36                          <0x000dd000 0x000dd000 0x001000>,      /* ap 19 */
  37                          <0x000de000 0x000de000 0x001000>,      /* ap 20 */
  38                          <0x000e0000 0x000e0000 0x001000>,      /* ap 21 */
  39                          <0x000e1000 0x000e1000 0x001000>,      /* ap 22 */
  40                          <0x000f4000 0x000f4000 0x001000>,      /* ap 23 */
  41                          <0x000f5000 0x000f5000 0x001000>,      /* ap 24 */
  42                          <0x000f6000 0x000f6000 0x001000>,      /* ap 25 */
  43                          <0x000f7000 0x000f7000 0x001000>,      /* ap 26 */
  44                          <0x00090000 0x00090000 0x008000>,      /* ap 59 */
  45                          <0x00098000 0x00098000 0x001000>;      /* ap 60 */
  46
  47                 target-module@2000 {                    /* 0x4a002000, ap 3 08.0 */
  48                         compatible = "ti,sysc-omap4", "ti,sysc";
  49                         reg = <0x2000 0x4>;
  50                         reg-names = "rev";
  51                         #address-cells = <1>;
  52                         #size-cells = <1>;
  53                         ranges = <0x0 0x2000 0x2000>;
  54
  55                         scm: scm@0 {
  56                                 compatible = "ti,dra7-scm-core", "simple-bus";
  57                                 reg = <0 0x2000>;
  58                                 #address-cells = <1>;
  59                                 #size-cells = <1>;
  60                                 ranges = <0 0 0x2000>;
  61
  62                                 scm_conf: scm_conf@0 {
  63                                         compatible = "syscon", "simple-bus";
  64                                         reg = <0x0 0x1400>;
  65                                         #address-cells = <1>;
  66                                         #size-cells = <1>;
  67                                         ranges = <0 0x0 0x1400>;
  68
  69                                         pbias_regulator: pbias_regulator@e00 {
  70                                                 compatible = "ti,pbias-dra7", "ti,pbias-omap";
  71                                                 reg = <0xe00 0x4>;
  72                                                 syscon = <&scm_conf>;
  73                                                 pbias_mmc_reg: pbias_mmc_omap5 {
  74                                                         regulator-name = "pbias_mmc_omap5";
  75                                                         regulator-min-microvolt = <1800000>;
  76                                                         regulator-max-microvolt = <3300000>;
  77                                                 };
  78                                         };
  79
  80                                         phy_gmii_sel: phy-gmii-sel {
  81                                                 compatible = "ti,dra7xx-phy-gmii-sel";
  82                                                 reg = <0x554 0x4>;
  83                                                 #phy-cells = <1>;
  84                                         };
  85
  86                                         scm_conf_clocks: clocks {
  87                                                 #address-cells = <1>;
  88                                                 #size-cells = <0>;
  89                                         };
  90                                 };
  91
  92                                 dra7_pmx_core: pinmux@1400 {
  93                                         compatible = "ti,dra7-padconf",
  94                                                      "pinctrl-single";
  95                                         reg = <0x1400 0x0468>;
  96                                         #address-cells = <1>;
  97                                         #size-cells = <0>;
  98                                         #pinctrl-cells = <1>;
  99                                         #interrupt-cells = <1>;
 100                                         interrupt-controller;
 101                                         pinctrl-single,register-width = <32>;
 102                                         pinctrl-single,function-mask = <0x3fffffff>;
 103                                 };
 104
 105                                 scm_conf1: scm_conf@1c04 {
 106                                         compatible = "syscon";
 107                                         reg = <0x1c04 0x0020>;
 108                                         #syscon-cells = <2>;
 109                                 };
 110
 111                                 scm_conf_pcie: scm_conf@1c24 {
 112                                         compatible = "syscon";
 113                                         reg = <0x1c24 0x0024>;
 114                                 };
 115
 116                                 sdma_xbar: dma-router@b78 {
 117                                         compatible = "ti,dra7-dma-crossbar";
 118                                         reg = <0xb78 0xfc>;
 119                                         #dma-cells = <1>;
 120                                         dma-requests = <205>;
 121                                         ti,dma-safe-map = <0>;
 122                                         dma-masters = <&sdma>;
 123                                 };
 124
 125                                 edma_xbar: dma-router@c78 {
 126                                         compatible = "ti,dra7-dma-crossbar";
 127                                         reg = <0xc78 0x7c>;
 128                                         #dma-cells = <2>;
 129                                         dma-requests = <204>;
 130                                         ti,dma-safe-map = <0>;
 131                                         dma-masters = <&edma>;
 132                                 };
 133                         };
 134                 };
 135
 136                 target-module@5000 {                    /* 0x4a005000, ap 5 10.0 */
 137                         compatible = "ti,sysc-omap4", "ti,sysc";
 138                         reg = <0x5000 0x4>;
 139                         reg-names = "rev";
 140                         #address-cells = <1>;
 141                         #size-cells = <1>;
 142                         ranges = <0x0 0x5000 0x1000>;
 143
 144                         cm_core_aon: cm_core_aon@0 {
 145                                 compatible = "ti,dra7-cm-core-aon",
 146                                               "simple-bus";
 147                                 #address-cells = <1>;
 148                                 #size-cells = <1>;
 149                                 reg = <0 0x2000>;
 150                                 ranges = <0 0 0x2000>;
 151
 152                                 cm_core_aon_clocks: clocks {
 153                                         #address-cells = <1>;
 154                                         #size-cells = <0>;
 155                                 };
 156
 157                                 cm_core_aon_clockdomains: clockdomains {
 158                                 };
 159                         };
 160                 };
 161
 162                 target-module@8000 {                    /* 0x4a008000, ap 7 0e.0 */
 163                         compatible = "ti,sysc-omap4", "ti,sysc";
 164                         reg = <0x8000 0x4>;
 165                         reg-names = "rev";
 166                         #address-cells = <1>;
 167                         #size-cells = <1>;
 168                         ranges = <0x0 0x8000 0x2000>;
 169
 170                         cm_core: cm_core@0 {
 171                                 compatible = "ti,dra7-cm-core", "simple-bus";
 172                                 #address-cells = <1>;
 173                                 #size-cells = <1>;
 174                                 reg = <0 0x3000>;
 175                                 ranges = <0 0 0x3000>;
 176
 177                                 cm_core_clocks: clocks {
 178                                         #address-cells = <1>;
 179                                         #size-cells = <0>;
 180                                 };
 181
 182                                 cm_core_clockdomains: clockdomains {
 183                                 };
 184                         };
 185                 };
 186
 187                 target-module@56000 {                   /* 0x4a056000, ap 9 02.0 */
 188                         compatible = "ti,sysc-omap2", "ti,sysc";
 189                         ti,hwmods = "dma_system";
 190                         reg = <0x56000 0x4>,
 191                               <0x5602c 0x4>,
 192                               <0x56028 0x4>;
 193                         reg-names = "rev", "sysc", "syss";
 194                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 195                                          SYSC_OMAP2_EMUFREE |
 196                                          SYSC_OMAP2_SOFTRESET |
 197                                          SYSC_OMAP2_AUTOIDLE)>;
 198                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 199                                         <SYSC_IDLE_NO>,
 200                                         <SYSC_IDLE_SMART>,
 201                                         <SYSC_IDLE_SMART_WKUP>;
 202                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 203                                         <SYSC_IDLE_NO>,
 204                                         <SYSC_IDLE_SMART>,
 205                                         <SYSC_IDLE_SMART_WKUP>;
 206                         ti,syss-mask = <1>;
 207                         /* Domains (P, C): core_pwrdm, dma_clkdm */
 208                         clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
 209                         clock-names = "fck";
 210                         #address-cells = <1>;
 211                         #size-cells = <1>;
 212                         ranges = <0x0 0x56000 0x1000>;
 213
 214                         sdma: dma-controller@0 {
 215                                 compatible = "ti,omap4430-sdma";
 216                                 reg = <0x0 0x1000>;
 217                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 218                                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 219                                              <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 220                                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 221                                 #dma-cells = <1>;
 222                                 dma-channels = <32>;
 223                                 dma-requests = <127>;
 224                         };
 225                 };
 226
 227                 target-module@5e000 {                   /* 0x4a05e000, ap 11 1a.0 */
 228                         compatible = "ti,sysc";
 229                         status = "disabled";
 230                         #address-cells = <1>;
 231                         #size-cells = <1>;
 232                         ranges = <0x0 0x5e000 0x2000>;
 233                 };
 234
 235                 target-module@80000 {                   /* 0x4a080000, ap 13 20.0 */
 236                         compatible = "ti,sysc-omap2", "ti,sysc";
 237                         ti,hwmods = "ocp2scp1";
 238                         reg = <0x80000 0x4>,
 239                               <0x80010 0x4>,
 240                               <0x80014 0x4>;
 241                         reg-names = "rev", "sysc", "syss";
 242                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 243                                          SYSC_OMAP2_AUTOIDLE)>;
 244                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 245                                         <SYSC_IDLE_NO>,
 246                                         <SYSC_IDLE_SMART>;
 247                         ti,syss-mask = <1>;
 248                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
 249                         clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
 250                         clock-names = "fck";
 251                         #address-cells = <1>;
 252                         #size-cells = <1>;
 253                         ranges = <0x0 0x80000 0x8000>;
 254
 255                         ocp2scp@0 {
 256                                 compatible = "ti,omap-ocp2scp";
 257                                 #address-cells = <1>;
 258                                 #size-cells = <1>;
 259                                 ranges = <0 0 0x8000>;
 260                                 reg = <0x0 0x20>;
 261
 262                                 usb2_phy1: phy@4000 {
 263                                         compatible = "ti,dra7x-usb2", "ti,omap-usb2";
 264                                         reg = <0x4000 0x400>;
 265                                         syscon-phy-power = <&scm_conf 0x300>;
 266                                         clocks = <&usb_phy1_always_on_clk32k>,
 267                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
 268                                         clock-names =   "wkupclk",
 269                                                         "refclk";
 270                                         #phy-cells = <0>;
 271                                 };
 272
 273                                 usb2_phy2: phy@5000 {
 274                                         compatible = "ti,dra7x-usb2-phy2",
 275                                                      "ti,omap-usb2";
 276                                         reg = <0x5000 0x400>;
 277                                         syscon-phy-power = <&scm_conf 0xe74>;
 278                                         clocks = <&usb_phy2_always_on_clk32k>,
 279                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
 280                                         clock-names =   "wkupclk",
 281                                                         "refclk";
 282                                         #phy-cells = <0>;
 283                                 };
 284
 285                                 usb3_phy1: phy@4400 {
 286                                         compatible = "ti,omap-usb3";
 287                                         reg = <0x4400 0x80>,
 288                                               <0x4800 0x64>,
 289                                               <0x4c00 0x40>;
 290                                         reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 291                                         syscon-phy-power = <&scm_conf 0x370>;
 292                                         clocks = <&usb_phy3_always_on_clk32k>,
 293                                                  <&sys_clkin1>,
 294                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
 295                                         clock-names =   "wkupclk",
 296                                                         "sysclk",
 297                                                         "refclk";
 298                                         #phy-cells = <0>;
 299                                 };
 300                         };
 301                 };
 302
 303                 target-module@90000 {                   /* 0x4a090000, ap 59 42.0 */
 304                         compatible = "ti,sysc-omap2", "ti,sysc";
 305                         ti,hwmods = "ocp2scp3";
 306                         reg = <0x90000 0x4>,
 307                               <0x90010 0x4>,
 308                               <0x90014 0x4>;
 309                         reg-names = "rev", "sysc", "syss";
 310                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 311                                          SYSC_OMAP2_AUTOIDLE)>;
 312                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 313                                         <SYSC_IDLE_NO>,
 314                                         <SYSC_IDLE_SMART>;
 315                         ti,syss-mask = <1>;
 316                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
 317                         clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
 318                         clock-names = "fck";
 319                         #address-cells = <1>;
 320                         #size-cells = <1>;
 321                         ranges = <0x0 0x90000 0x8000>;
 322
 323                         ocp2scp@0 {
 324                                 compatible = "ti,omap-ocp2scp";
 325                                 #address-cells = <1>;
 326                                 #size-cells = <1>;
 327                                 ranges = <0 0 0x8000>;
 328                                 reg = <0x0 0x20>;
 329
 330                                 pcie1_phy: pciephy@4000 {
 331                                         compatible = "ti,phy-pipe3-pcie";
 332                                         reg = <0x4000 0x80>, /* phy_rx */
 333                                               <0x4400 0x64>; /* phy_tx */
 334                                         reg-names = "phy_rx", "phy_tx";
 335                                         syscon-phy-power = <&scm_conf_pcie 0x1c>;
 336                                         syscon-pcs = <&scm_conf_pcie 0x10>;
 337                                         clocks = <&dpll_pcie_ref_ck>,
 338                                                  <&dpll_pcie_ref_m2ldo_ck>,
 339                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
 340                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
 341                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
 342                                                  <&optfclk_pciephy_div>,
 343                                                  <&sys_clkin1>;
 344                                         clock-names = "dpll_ref", "dpll_ref_m2",
 345                                                       "wkupclk", "refclk",
 346                                                       "div-clk", "phy-div", "sysclk";
 347                                         #phy-cells = <0>;
 348                                 };
 349
 350                                 pcie2_phy: pciephy@5000 {
 351                                         compatible = "ti,phy-pipe3-pcie";
 352                                         reg = <0x5000 0x80>, /* phy_rx */
 353                                               <0x5400 0x64>; /* phy_tx */
 354                                         reg-names = "phy_rx", "phy_tx";
 355                                         syscon-phy-power = <&scm_conf_pcie 0x20>;
 356                                         syscon-pcs = <&scm_conf_pcie 0x10>;
 357                                         clocks = <&dpll_pcie_ref_ck>,
 358                                                  <&dpll_pcie_ref_m2ldo_ck>,
 359                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
 360                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
 361                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
 362                                                  <&optfclk_pciephy_div>,
 363                                                  <&sys_clkin1>;
 364                                         clock-names = "dpll_ref", "dpll_ref_m2",
 365                                                       "wkupclk", "refclk",
 366                                                       "div-clk", "phy-div", "sysclk";
 367                                         #phy-cells = <0>;
 368                                         status = "disabled";
 369                                 };
 370
 371                                 sata_phy: phy@6000 {
 372                                         compatible = "ti,phy-pipe3-sata";
 373                                         reg = <0x6000 0x80>, /* phy_rx */
 374                                               <0x6400 0x64>, /* phy_tx */
 375                                               <0x6800 0x40>; /* pll_ctrl */
 376                                         reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 377                                         syscon-phy-power = <&scm_conf 0x374>;
 378                                         clocks = <&sys_clkin1>,
 379                                                  <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
 380                                         clock-names = "sysclk", "refclk";
 381                                         syscon-pllreset = <&scm_conf 0x3fc>;
 382                                         #phy-cells = <0>;
 383                                 };
 384                         };
 385                 };
 386
 387                 target-module@a0000 {                   /* 0x4a0a0000, ap 15 40.0 */
 388                         compatible = "ti,sysc";
 389                         status = "disabled";
 390                         #address-cells = <1>;
 391                         #size-cells = <1>;
 392                         ranges = <0x0 0xa0000 0x8000>;
 393                 };
 394
 395                 target-module@d9000 {                   /* 0x4a0d9000, ap 17 72.0 */
 396                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
 397                         ti,hwmods = "smartreflex_mpu";
 398                         reg = <0xd9038 0x4>;
 399                         reg-names = "sysc";
 400                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 401                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 402                                         <SYSC_IDLE_NO>,
 403                                         <SYSC_IDLE_SMART>,
 404                                         <SYSC_IDLE_SMART_WKUP>;
 405                         /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
 406                         clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
 407                         clock-names = "fck";
 408                         #address-cells = <1>;
 409                         #size-cells = <1>;
 410                         ranges = <0x0 0xd9000 0x1000>;
 411
 412                         /* SmartReflex child device marked reserved in TRM */
 413                 };
 414
 415                 target-module@dd000 {                   /* 0x4a0dd000, ap 19 18.0 */
 416                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
 417                         ti,hwmods = "smartreflex_core";
 418                         reg = <0xdd038 0x4>;
 419                         reg-names = "sysc";
 420                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 421                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 422                                         <SYSC_IDLE_NO>,
 423                                         <SYSC_IDLE_SMART>,
 424                                         <SYSC_IDLE_SMART_WKUP>;
 425                         /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
 426                         clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
 427                         clock-names = "fck";
 428                         #address-cells = <1>;
 429                         #size-cells = <1>;
 430                         ranges = <0x0 0xdd000 0x1000>;
 431
 432                         /* SmartReflex child device marked reserved in TRM */
 433                 };
 434
 435                 target-module@e0000 {                   /* 0x4a0e0000, ap 21 28.0 */
 436                         compatible = "ti,sysc";
 437                         status = "disabled";
 438                         #address-cells = <1>;
 439                         #size-cells = <1>;
 440                         ranges = <0x0 0xe0000 0x1000>;
 441                 };
 442
 443                 target-module@f4000 {                   /* 0x4a0f4000, ap 23 04.0 */
 444                         compatible = "ti,sysc-omap4", "ti,sysc";
 445                         ti,hwmods = "mailbox1";
 446                         reg = <0xf4000 0x4>,
 447                               <0xf4010 0x4>;
 448                         reg-names = "rev", "sysc";
 449                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 450                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 451                                         <SYSC_IDLE_NO>,
 452                                         <SYSC_IDLE_SMART>;
 453                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 454                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
 455                         clock-names = "fck";
 456                         #address-cells = <1>;
 457                         #size-cells = <1>;
 458                         ranges = <0x0 0xf4000 0x1000>;
 459
 460                         mailbox1: mailbox@0 {
 461                                 compatible = "ti,omap4-mailbox";
 462                                 reg = <0x0 0x200>;
 463                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 464                                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 465                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 466                                 #mbox-cells = <1>;
 467                                 ti,mbox-num-users = <3>;
 468                                 ti,mbox-num-fifos = <8>;
 469                                 status = "disabled";
 470                         };
 471                 };
 472
 473                 target-module@f6000 {                   /* 0x4a0f6000, ap 25 78.0 */
 474                         compatible = "ti,sysc-omap2", "ti,sysc";
 475                         ti,hwmods = "spinlock";
 476                         reg = <0xf6000 0x4>,
 477                               <0xf6010 0x4>,
 478                               <0xf6014 0x4>;
 479                         reg-names = "rev", "sysc", "syss";
 480                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 481                                          SYSC_OMAP2_SOFTRESET |
 482                                          SYSC_OMAP2_AUTOIDLE)>;
 483                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 484                                         <SYSC_IDLE_NO>,
 485                                         <SYSC_IDLE_SMART>;
 486                         ti,syss-mask = <1>;
 487                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 488                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
 489                         clock-names = "fck";
 490                         #address-cells = <1>;
 491                         #size-cells = <1>;
 492                         ranges = <0x0 0xf6000 0x1000>;
 493
 494                         hwspinlock: spinlock@0 {
 495                                 compatible = "ti,omap4-hwspinlock";
 496                                 reg = <0x0 0x1000>;
 497                                 #hwlock-cells = <1>;
 498                         };
 499                 };
 500         };
 501
 502         segment@100000 {                                        /* 0x4a100000 */
 503                 compatible = "simple-bus";
 504                 #address-cells = <1>;
 505                 #size-cells = <1>;
 506                 ranges = <0x00002000 0x00102000 0x001000>,      /* ap 27 */
 507                          <0x00003000 0x00103000 0x001000>,      /* ap 28 */
 508                          <0x00008000 0x00108000 0x001000>,      /* ap 29 */
 509                          <0x00009000 0x00109000 0x001000>,      /* ap 30 */
 510                          <0x00040000 0x00140000 0x010000>,      /* ap 31 */
 511                          <0x00050000 0x00150000 0x001000>,      /* ap 32 */
 512                          <0x00051000 0x00151000 0x001000>,      /* ap 33 */
 513                          <0x00052000 0x00152000 0x001000>,      /* ap 34 */
 514                          <0x00053000 0x00153000 0x001000>,      /* ap 35 */
 515                          <0x00054000 0x00154000 0x001000>,      /* ap 36 */
 516                          <0x00055000 0x00155000 0x001000>,      /* ap 37 */
 517                          <0x00056000 0x00156000 0x001000>,      /* ap 38 */
 518                          <0x00057000 0x00157000 0x001000>,      /* ap 39 */
 519                          <0x00058000 0x00158000 0x001000>,      /* ap 40 */
 520                          <0x0005b000 0x0015b000 0x001000>,      /* ap 41 */
 521                          <0x0005c000 0x0015c000 0x001000>,      /* ap 42 */
 522                          <0x0005d000 0x0015d000 0x001000>,      /* ap 45 */
 523                          <0x0005e000 0x0015e000 0x001000>,      /* ap 46 */
 524                          <0x0005f000 0x0015f000 0x001000>,      /* ap 47 */
 525                          <0x00060000 0x00160000 0x001000>,      /* ap 48 */
 526                          <0x00061000 0x00161000 0x001000>,      /* ap 49 */
 527                          <0x00062000 0x00162000 0x001000>,      /* ap 50 */
 528                          <0x00063000 0x00163000 0x001000>,      /* ap 51 */
 529                          <0x00064000 0x00164000 0x001000>,      /* ap 52 */
 530                          <0x00065000 0x00165000 0x001000>,      /* ap 53 */
 531                          <0x00066000 0x00166000 0x001000>,      /* ap 54 */
 532                          <0x00067000 0x00167000 0x001000>,      /* ap 55 */
 533                          <0x00068000 0x00168000 0x001000>,      /* ap 56 */
 534                          <0x0006d000 0x0016d000 0x001000>,      /* ap 57 */
 535                          <0x0006e000 0x0016e000 0x001000>,      /* ap 58 */
 536                          <0x00071000 0x00171000 0x001000>,      /* ap 61 */
 537                          <0x00072000 0x00172000 0x001000>,      /* ap 62 */
 538                          <0x00073000 0x00173000 0x001000>,      /* ap 63 */
 539                          <0x00074000 0x00174000 0x001000>,      /* ap 64 */
 540                          <0x00075000 0x00175000 0x001000>,      /* ap 65 */
 541                          <0x00076000 0x00176000 0x001000>,      /* ap 66 */
 542                          <0x00077000 0x00177000 0x001000>,      /* ap 67 */
 543                          <0x00078000 0x00178000 0x001000>,      /* ap 68 */
 544                          <0x00081000 0x00181000 0x001000>,      /* ap 69 */
 545                          <0x00082000 0x00182000 0x001000>,      /* ap 70 */
 546                          <0x00083000 0x00183000 0x001000>,      /* ap 71 */
 547                          <0x00084000 0x00184000 0x001000>,      /* ap 72 */
 548                          <0x00085000 0x00185000 0x001000>,      /* ap 73 */
 549                          <0x00086000 0x00186000 0x001000>,      /* ap 74 */
 550                          <0x00087000 0x00187000 0x001000>,      /* ap 75 */
 551                          <0x00088000 0x00188000 0x001000>,      /* ap 76 */
 552                          <0x00069000 0x00169000 0x001000>,      /* ap 103 */
 553                          <0x0006a000 0x0016a000 0x001000>,      /* ap 104 */
 554                          <0x00079000 0x00179000 0x001000>,      /* ap 105 */
 555                          <0x0007a000 0x0017a000 0x001000>,      /* ap 106 */
 556                          <0x0006b000 0x0016b000 0x001000>,      /* ap 107 */
 557                          <0x0006c000 0x0016c000 0x001000>,      /* ap 108 */
 558                          <0x0007b000 0x0017b000 0x001000>,      /* ap 121 */
 559                          <0x0007c000 0x0017c000 0x001000>,      /* ap 122 */
 560                          <0x0007d000 0x0017d000 0x001000>,      /* ap 123 */
 561                          <0x0007e000 0x0017e000 0x001000>,      /* ap 124 */
 562                          <0x00059000 0x00159000 0x001000>,      /* ap 125 */
 563                          <0x0005a000 0x0015a000 0x001000>;      /* ap 126 */
 564
 565                 target-module@2000 {                    /* 0x4a102000, ap 27 3c.0 */
 566                         compatible = "ti,sysc";
 567                         status = "disabled";
 568                         #address-cells = <1>;
 569                         #size-cells = <1>;
 570                         ranges = <0x0 0x2000 0x1000>;
 571                 };
 572
 573                 target-module@8000 {                    /* 0x4a108000, ap 29 1e.0 */
 574                         compatible = "ti,sysc";
 575                         status = "disabled";
 576                         #address-cells = <1>;
 577                         #size-cells = <1>;
 578                         ranges = <0x0 0x8000 0x1000>;
 579                 };
 580
 581                 target-module@40000 {                   /* 0x4a140000, ap 31 06.0 */
 582                         compatible = "ti,sysc";
 583                         status = "disabled";
 584                         #address-cells = <1>;
 585                         #size-cells = <1>;
 586                         ranges = <0x0 0x40000 0x10000>;
 587                 };
 588
 589                 target-module@51000 {                   /* 0x4a151000, ap 33 50.0 */
 590                         compatible = "ti,sysc";
 591                         status = "disabled";
 592                         #address-cells = <1>;
 593                         #size-cells = <1>;
 594                         ranges = <0x0 0x51000 0x1000>;
 595                 };
 596
 597                 target-module@53000 {                   /* 0x4a153000, ap 35 54.0 */
 598                         compatible = "ti,sysc";
 599                         status = "disabled";
 600                         #address-cells = <1>;
 601                         #size-cells = <1>;
 602                         ranges = <0x0 0x53000 0x1000>;
 603                 };
 604
 605                 target-module@55000 {                   /* 0x4a155000, ap 37 46.0 */
 606                         compatible = "ti,sysc";
 607                         status = "disabled";
 608                         #address-cells = <1>;
 609                         #size-cells = <1>;
 610                         ranges = <0x0 0x55000 0x1000>;
 611                 };
 612
 613                 target-module@57000 {                   /* 0x4a157000, ap 39 58.0 */
 614                         compatible = "ti,sysc";
 615                         status = "disabled";
 616                         #address-cells = <1>;
 617                         #size-cells = <1>;
 618                         ranges = <0x0 0x57000 0x1000>;
 619                 };
 620
 621                 target-module@59000 {                   /* 0x4a159000, ap 125 6a.0 */
 622                         compatible = "ti,sysc";
 623                         status = "disabled";
 624                         #address-cells = <1>;
 625                         #size-cells = <1>;
 626                         ranges = <0x0 0x59000 0x1000>;
 627                 };
 628
 629                 target-module@5b000 {                   /* 0x4a15b000, ap 41 60.0 */
 630                         compatible = "ti,sysc";
 631                         status = "disabled";
 632                         #address-cells = <1>;
 633                         #size-cells = <1>;
 634                         ranges = <0x0 0x5b000 0x1000>;
 635                 };
 636
 637                 target-module@5d000 {                   /* 0x4a15d000, ap 45 3a.0 */
 638                         compatible = "ti,sysc";
 639                         status = "disabled";
 640                         #address-cells = <1>;
 641                         #size-cells = <1>;
 642                         ranges = <0x0 0x5d000 0x1000>;
 643                 };
 644
 645                 target-module@5f000 {                   /* 0x4a15f000, ap 47 56.0 */
 646                         compatible = "ti,sysc";
 647                         status = "disabled";
 648                         #address-cells = <1>;
 649                         #size-cells = <1>;
 650                         ranges = <0x0 0x5f000 0x1000>;
 651                 };
 652
 653                 target-module@61000 {                   /* 0x4a161000, ap 49 32.0 */
 654                         compatible = "ti,sysc";
 655                         status = "disabled";
 656                         #address-cells = <1>;
 657                         #size-cells = <1>;
 658                         ranges = <0x0 0x61000 0x1000>;
 659                 };
 660
 661                 target-module@63000 {                   /* 0x4a163000, ap 51 5c.0 */
 662                         compatible = "ti,sysc";
 663                         status = "disabled";
 664                         #address-cells = <1>;
 665                         #size-cells = <1>;
 666                         ranges = <0x0 0x63000 0x1000>;
 667                 };
 668
 669                 target-module@65000 {                   /* 0x4a165000, ap 53 4e.0 */
 670                         compatible = "ti,sysc";
 671                         status = "disabled";
 672                         #address-cells = <1>;
 673                         #size-cells = <1>;
 674                         ranges = <0x0 0x65000 0x1000>;
 675                 };
 676
 677                 target-module@67000 {                   /* 0x4a167000, ap 55 5e.0 */
 678                         compatible = "ti,sysc";
 679                         status = "disabled";
 680                         #address-cells = <1>;
 681                         #size-cells = <1>;
 682                         ranges = <0x0 0x67000 0x1000>;
 683                 };
 684
 685                 target-module@69000 {                   /* 0x4a169000, ap 103 4a.0 */
 686                         compatible = "ti,sysc";
 687                         status = "disabled";
 688                         #address-cells = <1>;
 689                         #size-cells = <1>;
 690                         ranges = <0x0 0x69000 0x1000>;
 691                 };
 692
 693                 target-module@6b000 {                   /* 0x4a16b000, ap 107 52.0 */
 694                         compatible = "ti,sysc";
 695                         status = "disabled";
 696                         #address-cells = <1>;
 697                         #size-cells = <1>;
 698                         ranges = <0x0 0x6b000 0x1000>;
 699                 };
 700
 701                 target-module@6d000 {                   /* 0x4a16d000, ap 57 68.0 */
 702                         compatible = "ti,sysc";
 703                         status = "disabled";
 704                         #address-cells = <1>;
 705                         #size-cells = <1>;
 706                         ranges = <0x0 0x6d000 0x1000>;
 707                 };
 708
 709                 target-module@71000 {                   /* 0x4a171000, ap 61 48.0 */
 710                         compatible = "ti,sysc";
 711                         status = "disabled";
 712                         #address-cells = <1>;
 713                         #size-cells = <1>;
 714                         ranges = <0x0 0x71000 0x1000>;
 715                 };
 716
 717                 target-module@73000 {                   /* 0x4a173000, ap 63 2a.0 */
 718                         compatible = "ti,sysc";
 719                         status = "disabled";
 720                         #address-cells = <1>;
 721                         #size-cells = <1>;
 722                         ranges = <0x0 0x73000 0x1000>;
 723                 };
 724
 725                 target-module@75000 {                   /* 0x4a175000, ap 65 64.0 */
 726                         compatible = "ti,sysc";
 727                         status = "disabled";
 728                         #address-cells = <1>;
 729                         #size-cells = <1>;
 730                         ranges = <0x0 0x75000 0x1000>;
 731                 };
 732
 733                 target-module@77000 {                   /* 0x4a177000, ap 67 66.0 */
 734                         compatible = "ti,sysc";
 735                         status = "disabled";
 736                         #address-cells = <1>;
 737                         #size-cells = <1>;
 738                         ranges = <0x0 0x77000 0x1000>;
 739                 };
 740
 741                 target-module@79000 {                   /* 0x4a179000, ap 105 34.0 */
 742                         compatible = "ti,sysc";
 743                         status = "disabled";
 744                         #address-cells = <1>;
 745                         #size-cells = <1>;
 746                         ranges = <0x0 0x79000 0x1000>;
 747                 };
 748
 749                 target-module@7b000 {                   /* 0x4a17b000, ap 121 7c.0 */
 750                         compatible = "ti,sysc";
 751                         status = "disabled";
 752                         #address-cells = <1>;
 753                         #size-cells = <1>;
 754                         ranges = <0x0 0x7b000 0x1000>;
 755                 };
 756
 757                 target-module@7d000 {                   /* 0x4a17d000, ap 123 7e.0 */
 758                         compatible = "ti,sysc";
 759                         status = "disabled";
 760                         #address-cells = <1>;
 761                         #size-cells = <1>;
 762                         ranges = <0x0 0x7d000 0x1000>;
 763                 };
 764
 765                 target-module@81000 {                   /* 0x4a181000, ap 69 26.0 */
 766                         compatible = "ti,sysc";
 767                         status = "disabled";
 768                         #address-cells = <1>;
 769                         #size-cells = <1>;
 770                         ranges = <0x0 0x81000 0x1000>;
 771                 };
 772
 773                 target-module@83000 {                   /* 0x4a183000, ap 71 2e.0 */
 774                         compatible = "ti,sysc";
 775                         status = "disabled";
 776                         #address-cells = <1>;
 777                         #size-cells = <1>;
 778                         ranges = <0x0 0x83000 0x1000>;
 779                 };
 780
 781                 target-module@85000 {                   /* 0x4a185000, ap 73 36.0 */
 782                         compatible = "ti,sysc";
 783                         status = "disabled";
 784                         #address-cells = <1>;
 785                         #size-cells = <1>;
 786                         ranges = <0x0 0x85000 0x1000>;
 787                 };
 788
 789                 target-module@87000 {                   /* 0x4a187000, ap 75 74.0 */
 790                         compatible = "ti,sysc";
 791                         status = "disabled";
 792                         #address-cells = <1>;
 793                         #size-cells = <1>;
 794                         ranges = <0x0 0x87000 0x1000>;
 795                 };
 796         };
 797
 798         segment@200000 {                                        /* 0x4a200000 */
 799                 compatible = "simple-bus";
 800                 #address-cells = <1>;
 801                 #size-cells = <1>;
 802                 ranges = <0x00018000 0x00218000 0x001000>,      /* ap 43 */
 803                          <0x00019000 0x00219000 0x001000>,      /* ap 44 */
 804                          <0x00000000 0x00200000 0x001000>,      /* ap 77 */
 805                          <0x00001000 0x00201000 0x001000>,      /* ap 78 */
 806                          <0x0000a000 0x0020a000 0x001000>,      /* ap 79 */
 807                          <0x0000b000 0x0020b000 0x001000>,      /* ap 80 */
 808                          <0x0000c000 0x0020c000 0x001000>,      /* ap 81 */
 809                          <0x0000d000 0x0020d000 0x001000>,      /* ap 82 */
 810                          <0x0000e000 0x0020e000 0x001000>,      /* ap 83 */
 811                          <0x0000f000 0x0020f000 0x001000>,      /* ap 84 */
 812                          <0x00010000 0x00210000 0x001000>,      /* ap 85 */
 813                          <0x00011000 0x00211000 0x001000>,      /* ap 86 */
 814                          <0x00012000 0x00212000 0x001000>,      /* ap 87 */
 815                          <0x00013000 0x00213000 0x001000>,      /* ap 88 */
 816                          <0x00014000 0x00214000 0x001000>,      /* ap 89 */
 817                          <0x00015000 0x00215000 0x001000>,      /* ap 90 */
 818                          <0x0002a000 0x0022a000 0x001000>,      /* ap 91 */
 819                          <0x0002b000 0x0022b000 0x001000>,      /* ap 92 */
 820                          <0x0001c000 0x0021c000 0x001000>,      /* ap 93 */
 821                          <0x0001d000 0x0021d000 0x001000>,      /* ap 94 */
 822                          <0x0001e000 0x0021e000 0x001000>,      /* ap 95 */
 823                          <0x0001f000 0x0021f000 0x001000>,      /* ap 96 */
 824                          <0x00020000 0x00220000 0x001000>,      /* ap 97 */
 825                          <0x00021000 0x00221000 0x001000>,      /* ap 98 */
 826                          <0x00024000 0x00224000 0x001000>,      /* ap 99 */
 827                          <0x00025000 0x00225000 0x001000>,      /* ap 100 */
 828                          <0x00026000 0x00226000 0x001000>,      /* ap 101 */
 829                          <0x00027000 0x00227000 0x001000>,      /* ap 102 */
 830                          <0x0002c000 0x0022c000 0x001000>,      /* ap 109 */
 831                          <0x0002d000 0x0022d000 0x001000>,      /* ap 110 */
 832                          <0x0002e000 0x0022e000 0x001000>,      /* ap 111 */
 833                          <0x0002f000 0x0022f000 0x001000>,      /* ap 112 */
 834                          <0x00030000 0x00230000 0x001000>,      /* ap 113 */
 835                          <0x00031000 0x00231000 0x001000>,      /* ap 114 */
 836                          <0x00032000 0x00232000 0x001000>,      /* ap 115 */
 837                          <0x00033000 0x00233000 0x001000>,      /* ap 116 */
 838                          <0x00034000 0x00234000 0x001000>,      /* ap 117 */
 839                          <0x00035000 0x00235000 0x001000>,      /* ap 118 */
 840                          <0x00036000 0x00236000 0x001000>,      /* ap 119 */
 841                          <0x00037000 0x00237000 0x001000>,      /* ap 120 */
 842                          <0x0001a000 0x0021a000 0x001000>,      /* ap 127 */
 843                          <0x0001b000 0x0021b000 0x001000>;      /* ap 128 */
 844
 845                 target-module@0 {                       /* 0x4a200000, ap 77 3e.0 */
 846                         compatible = "ti,sysc";
 847                         status = "disabled";
 848                         #address-cells = <1>;
 849                         #size-cells = <1>;
 850                         ranges = <0x0 0x0 0x1000>;
 851                 };
 852
 853                 target-module@a000 {                    /* 0x4a20a000, ap 79 30.0 */
 854                         compatible = "ti,sysc";
 855                         status = "disabled";
 856                         #address-cells = <1>;
 857                         #size-cells = <1>;
 858                         ranges = <0x0 0xa000 0x1000>;
 859                 };
 860
 861                 target-module@c000 {                    /* 0x4a20c000, ap 81 0c.0 */
 862                         compatible = "ti,sysc";
 863                         status = "disabled";
 864                         #address-cells = <1>;
 865                         #size-cells = <1>;
 866                         ranges = <0x0 0xc000 0x1000>;
 867                 };
 868
 869                 target-module@e000 {                    /* 0x4a20e000, ap 83 22.0 */
 870                         compatible = "ti,sysc";
 871                         status = "disabled";
 872                         #address-cells = <1>;
 873                         #size-cells = <1>;
 874                         ranges = <0x0 0xe000 0x1000>;
 875                 };
 876
 877                 target-module@10000 {                   /* 0x4a210000, ap 85 14.0 */
 878                         compatible = "ti,sysc";
 879                         status = "disabled";
 880                         #address-cells = <1>;
 881                         #size-cells = <1>;
 882                         ranges = <0x0 0x10000 0x1000>;
 883                 };
 884
 885                 target-module@12000 {                   /* 0x4a212000, ap 87 16.0 */
 886                         compatible = "ti,sysc";
 887                         status = "disabled";
 888                         #address-cells = <1>;
 889                         #size-cells = <1>;
 890                         ranges = <0x0 0x12000 0x1000>;
 891                 };
 892
 893                 target-module@14000 {                   /* 0x4a214000, ap 89 1c.0 */
 894                         compatible = "ti,sysc";
 895                         status = "disabled";
 896                         #address-cells = <1>;
 897                         #size-cells = <1>;
 898                         ranges = <0x0 0x14000 0x1000>;
 899                 };
 900
 901                 target-module@18000 {                   /* 0x4a218000, ap 43 12.0 */
 902                         compatible = "ti,sysc";
 903                         status = "disabled";
 904                         #address-cells = <1>;
 905                         #size-cells = <1>;
 906                         ranges = <0x0 0x18000 0x1000>;
 907                 };
 908
 909                 target-module@1a000 {                   /* 0x4a21a000, ap 127 7a.0 */
 910                         compatible = "ti,sysc";
 911                         status = "disabled";
 912                         #address-cells = <1>;
 913                         #size-cells = <1>;
 914                         ranges = <0x0 0x1a000 0x1000>;
 915                 };
 916
 917                 target-module@1c000 {                   /* 0x4a21c000, ap 93 38.0 */
 918                         compatible = "ti,sysc";
 919                         status = "disabled";
 920                         #address-cells = <1>;
 921                         #size-cells = <1>;
 922                         ranges = <0x0 0x1c000 0x1000>;
 923                 };
 924
 925                 target-module@1e000 {                   /* 0x4a21e000, ap 95 0a.0 */
 926                         compatible = "ti,sysc";
 927                         status = "disabled";
 928                         #address-cells = <1>;
 929                         #size-cells = <1>;
 930                         ranges = <0x0 0x1e000 0x1000>;
 931                 };
 932
 933                 target-module@20000 {                   /* 0x4a220000, ap 97 24.0 */
 934                         compatible = "ti,sysc";
 935                         status = "disabled";
 936                         #address-cells = <1>;
 937                         #size-cells = <1>;
 938                         ranges = <0x0 0x20000 0x1000>;
 939                 };
 940
 941                 target-module@24000 {                   /* 0x4a224000, ap 99 44.0 */
 942                         compatible = "ti,sysc";
 943                         status = "disabled";
 944                         #address-cells = <1>;
 945                         #size-cells = <1>;
 946                         ranges = <0x0 0x24000 0x1000>;
 947                 };
 948
 949                 target-module@26000 {                   /* 0x4a226000, ap 101 2c.0 */
 950                         compatible = "ti,sysc";
 951                         status = "disabled";
 952                         #address-cells = <1>;
 953                         #size-cells = <1>;
 954                         ranges = <0x0 0x26000 0x1000>;
 955                 };
 956
 957                 target-module@2a000 {                   /* 0x4a22a000, ap 91 4c.0 */
 958                         compatible = "ti,sysc";
 959                         status = "disabled";
 960                         #address-cells = <1>;
 961                         #size-cells = <1>;
 962                         ranges = <0x0 0x2a000 0x1000>;
 963                 };
 964
 965                 target-module@2c000 {                   /* 0x4a22c000, ap 109 6c.0 */
 966                         compatible = "ti,sysc";
 967                         status = "disabled";
 968                         #address-cells = <1>;
 969                         #size-cells = <1>;
 970                         ranges = <0x0 0x2c000 0x1000>;
 971                 };
 972
 973                 target-module@2e000 {                   /* 0x4a22e000, ap 111 6e.0 */
 974                         compatible = "ti,sysc";
 975                         status = "disabled";
 976                         #address-cells = <1>;
 977                         #size-cells = <1>;
 978                         ranges = <0x0 0x2e000 0x1000>;
 979                 };
 980
 981                 target-module@30000 {                   /* 0x4a230000, ap 113 70.0 */
 982                         compatible = "ti,sysc";
 983                         status = "disabled";
 984                         #address-cells = <1>;
 985                         #size-cells = <1>;
 986                         ranges = <0x0 0x30000 0x1000>;
 987                 };
 988
 989                 target-module@32000 {                   /* 0x4a232000, ap 115 5a.0 */
 990                         compatible = "ti,sysc";
 991                         status = "disabled";
 992                         #address-cells = <1>;
 993                         #size-cells = <1>;
 994                         ranges = <0x0 0x32000 0x1000>;
 995                 };
 996
 997                 target-module@34000 {                   /* 0x4a234000, ap 117 76.1 */
 998                         compatible = "ti,sysc";
 999                         status = "disabled";
1000                         #address-cells = <1>;
1001                         #size-cells = <1>;
1002                         ranges = <0x0 0x34000 0x1000>;
1003                 };
1004
1005                 target-module@36000 {                   /* 0x4a236000, ap 119 62.0 */
1006                         compatible = "ti,sysc";
1007                         status = "disabled";
1008                         #address-cells = <1>;
1009                         #size-cells = <1>;
1010                         ranges = <0x0 0x36000 0x1000>;
1011                 };
1012         };
1013 };
1014
1015 &l4_per1 {                                              /* 0x48000000 */
1016         compatible = "ti,dra7-l4-per1", "simple-bus";
1017         reg = <0x48000000 0x800>,
1018               <0x48000800 0x800>,
1019               <0x48001000 0x400>,
1020               <0x48001400 0x400>,
1021               <0x48001800 0x400>,
1022               <0x48001c00 0x400>;
1023         reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
1024         #address-cells = <1>;
1025         #size-cells = <1>;
1026         ranges = <0x00000000 0x48000000 0x200000>,      /* segment 0 */
1027                  <0x00200000 0x48200000 0x200000>;      /* segment 1 */
1028
1029         segment@0 {                                     /* 0x48000000 */
1030                 compatible = "simple-bus";
1031                 #address-cells = <1>;
1032                 #size-cells = <1>;
1033                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
1034                          <0x00001000 0x00001000 0x000400>,      /* ap 1 */
1035                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
1036                          <0x00020000 0x00020000 0x001000>,      /* ap 3 */
1037                          <0x00021000 0x00021000 0x001000>,      /* ap 4 */
1038                          <0x00032000 0x00032000 0x001000>,      /* ap 5 */
1039                          <0x00033000 0x00033000 0x001000>,      /* ap 6 */
1040                          <0x00034000 0x00034000 0x001000>,      /* ap 7 */
1041                          <0x00035000 0x00035000 0x001000>,      /* ap 8 */
1042                          <0x00036000 0x00036000 0x001000>,      /* ap 9 */
1043                          <0x00037000 0x00037000 0x001000>,      /* ap 10 */
1044                          <0x0003e000 0x0003e000 0x001000>,      /* ap 11 */
1045                          <0x0003f000 0x0003f000 0x001000>,      /* ap 12 */
1046                          <0x00055000 0x00055000 0x001000>,      /* ap 13 */
1047                          <0x00056000 0x00056000 0x001000>,      /* ap 14 */
1048                          <0x00057000 0x00057000 0x001000>,      /* ap 15 */
1049                          <0x00058000 0x00058000 0x001000>,      /* ap 16 */
1050                          <0x00059000 0x00059000 0x001000>,      /* ap 17 */
1051                          <0x0005a000 0x0005a000 0x001000>,      /* ap 18 */
1052                          <0x0005b000 0x0005b000 0x001000>,      /* ap 19 */
1053                          <0x0005c000 0x0005c000 0x001000>,      /* ap 20 */
1054                          <0x0005d000 0x0005d000 0x001000>,      /* ap 21 */
1055                          <0x0005e000 0x0005e000 0x001000>,      /* ap 22 */
1056                          <0x00060000 0x00060000 0x001000>,      /* ap 23 */
1057                          <0x0006a000 0x0006a000 0x001000>,      /* ap 24 */
1058                          <0x0006b000 0x0006b000 0x001000>,      /* ap 25 */
1059                          <0x0006c000 0x0006c000 0x001000>,      /* ap 26 */
1060                          <0x0006d000 0x0006d000 0x001000>,      /* ap 27 */
1061                          <0x0006e000 0x0006e000 0x001000>,      /* ap 28 */
1062                          <0x0006f000 0x0006f000 0x001000>,      /* ap 29 */
1063                          <0x00070000 0x00070000 0x001000>,      /* ap 30 */
1064                          <0x00071000 0x00071000 0x001000>,      /* ap 31 */
1065                          <0x00072000 0x00072000 0x001000>,      /* ap 32 */
1066                          <0x00073000 0x00073000 0x001000>,      /* ap 33 */
1067                          <0x00061000 0x00061000 0x001000>,      /* ap 34 */
1068                          <0x00053000 0x00053000 0x001000>,      /* ap 35 */
1069                          <0x00054000 0x00054000 0x001000>,      /* ap 36 */
1070                          <0x000b2000 0x000b2000 0x001000>,      /* ap 37 */
1071                          <0x000b3000 0x000b3000 0x001000>,      /* ap 38 */
1072                          <0x00078000 0x00078000 0x001000>,      /* ap 39 */
1073                          <0x00079000 0x00079000 0x001000>,      /* ap 40 */
1074                          <0x00086000 0x00086000 0x001000>,      /* ap 41 */
1075                          <0x00087000 0x00087000 0x001000>,      /* ap 42 */
1076                          <0x00088000 0x00088000 0x001000>,      /* ap 43 */
1077                          <0x00089000 0x00089000 0x001000>,      /* ap 44 */
1078                          <0x00051000 0x00051000 0x001000>,      /* ap 45 */
1079                          <0x00052000 0x00052000 0x001000>,      /* ap 46 */
1080                          <0x00098000 0x00098000 0x001000>,      /* ap 47 */
1081                          <0x00099000 0x00099000 0x001000>,      /* ap 48 */
1082                          <0x0009a000 0x0009a000 0x001000>,      /* ap 49 */
1083                          <0x0009b000 0x0009b000 0x001000>,      /* ap 50 */
1084                          <0x0009c000 0x0009c000 0x001000>,      /* ap 51 */
1085                          <0x0009d000 0x0009d000 0x001000>,      /* ap 52 */
1086                          <0x00068000 0x00068000 0x001000>,      /* ap 53 */
1087                          <0x00069000 0x00069000 0x001000>,      /* ap 54 */
1088                          <0x00090000 0x00090000 0x002000>,      /* ap 55 */
1089                          <0x00092000 0x00092000 0x001000>,      /* ap 56 */
1090                          <0x000a4000 0x000a4000 0x001000>,      /* ap 57 */
1091                          <0x000a6000 0x000a6000 0x001000>,      /* ap 58 */
1092                          <0x000a8000 0x000a8000 0x004000>,      /* ap 59 */
1093                          <0x000ac000 0x000ac000 0x001000>,      /* ap 60 */
1094                          <0x000ad000 0x000ad000 0x001000>,      /* ap 61 */
1095                          <0x000ae000 0x000ae000 0x001000>,      /* ap 62 */
1096                          <0x00066000 0x00066000 0x001000>,      /* ap 63 */
1097                          <0x00067000 0x00067000 0x001000>,      /* ap 64 */
1098                          <0x000b4000 0x000b4000 0x001000>,      /* ap 65 */
1099                          <0x000b5000 0x000b5000 0x001000>,      /* ap 66 */
1100                          <0x000b8000 0x000b8000 0x001000>,      /* ap 67 */
1101                          <0x000b9000 0x000b9000 0x001000>,      /* ap 68 */
1102                          <0x000ba000 0x000ba000 0x001000>,      /* ap 69 */
1103                          <0x000bb000 0x000bb000 0x001000>,      /* ap 70 */
1104                          <0x000d1000 0x000d1000 0x001000>,      /* ap 71 */
1105                          <0x000d2000 0x000d2000 0x001000>,      /* ap 72 */
1106                          <0x000d5000 0x000d5000 0x001000>,      /* ap 73 */
1107                          <0x000d6000 0x000d6000 0x001000>,      /* ap 74 */
1108                          <0x000a2000 0x000a2000 0x001000>,      /* ap 75 */
1109                          <0x000a3000 0x000a3000 0x001000>,      /* ap 76 */
1110                          <0x00001400 0x00001400 0x000400>,      /* ap 77 */
1111                          <0x00001800 0x00001800 0x000400>,      /* ap 78 */
1112                          <0x00001c00 0x00001c00 0x000400>,      /* ap 79 */
1113                          <0x000a5000 0x000a5000 0x001000>,      /* ap 80 */
1114                          <0x0007a000 0x0007a000 0x001000>,      /* ap 81 */
1115                          <0x0007b000 0x0007b000 0x001000>,      /* ap 82 */
1116                          <0x0007c000 0x0007c000 0x001000>,      /* ap 83 */
1117                          <0x0007d000 0x0007d000 0x001000>;      /* ap 84 */
1118
1119                 target-module@20000 {                   /* 0x48020000, ap 3 04.0 */
1120                         compatible = "ti,sysc-omap2", "ti,sysc";
1121                         reg = <0x20050 0x4>,
1122                               <0x20054 0x4>,
1123                               <0x20058 0x4>;
1124                         reg-names = "rev", "sysc", "syss";
1125                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1126                                          SYSC_OMAP2_SOFTRESET |
1127                                          SYSC_OMAP2_AUTOIDLE)>;
1128                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1129                                         <SYSC_IDLE_NO>,
1130                                         <SYSC_IDLE_SMART>,
1131                                         <SYSC_IDLE_SMART_WKUP>;
1132                         ti,syss-mask = <1>;
1133                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1134                         clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1135                         clock-names = "fck";
1136                         #address-cells = <1>;
1137                         #size-cells = <1>;
1138                         ranges = <0x0 0x20000 0x1000>;
1139
1140                         uart3: serial@0 {
1141                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1142                                 reg = <0x0 0x100>;
1143                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1144                                 clock-frequency = <48000000>;
1145                                 status = "disabled";
1146                                 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
1147                                 dma-names = "tx", "rx";
1148                         };
1149                 };
1150
1151                 target-module@32000 {                   /* 0x48032000, ap 5 3e.0 */
1152                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1153                         ti,hwmods = "timer2";
1154                         reg = <0x32000 0x4>,
1155                               <0x32010 0x4>;
1156                         reg-names = "rev", "sysc";
1157                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1158                                          SYSC_OMAP4_SOFTRESET)>;
1159                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1160                                         <SYSC_IDLE_NO>,
1161                                         <SYSC_IDLE_SMART>,
1162                                         <SYSC_IDLE_SMART_WKUP>;
1163                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1164                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1165                         clock-names = "fck";
1166                         #address-cells = <1>;
1167                         #size-cells = <1>;
1168                         ranges = <0x0 0x32000 0x1000>;
1169
1170                         timer2: timer@0 {
1171                                 compatible = "ti,omap5430-timer";
1172                                 reg = <0x0 0x80>;
1173                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>;
1174                                 clock-names = "fck";
1175                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1176                         };
1177                 };
1178
1179                 target-module@34000 {                   /* 0x48034000, ap 7 46.0 */
1180                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1181                         ti,hwmods = "timer3";
1182                         reg = <0x34000 0x4>,
1183                               <0x34010 0x4>;
1184                         reg-names = "rev", "sysc";
1185                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1186                                          SYSC_OMAP4_SOFTRESET)>;
1187                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1188                                         <SYSC_IDLE_NO>,
1189                                         <SYSC_IDLE_SMART>,
1190                                         <SYSC_IDLE_SMART_WKUP>;
1191                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1192                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1193                         clock-names = "fck";
1194                         #address-cells = <1>;
1195                         #size-cells = <1>;
1196                         ranges = <0x0 0x34000 0x1000>;
1197
1198                         timer3: timer@0 {
1199                                 compatible = "ti,omap5430-timer";
1200                                 reg = <0x0 0x80>;
1201                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
1202                                 clock-names = "fck";
1203                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1204                         };
1205                 };
1206
1207                 target-module@36000 {                   /* 0x48036000, ap 9 4e.0 */
1208                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1209                         ti,hwmods = "timer4";
1210                         reg = <0x36000 0x4>,
1211                               <0x36010 0x4>;
1212                         reg-names = "rev", "sysc";
1213                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1214                                          SYSC_OMAP4_SOFTRESET)>;
1215                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1216                                         <SYSC_IDLE_NO>,
1217                                         <SYSC_IDLE_SMART>,
1218                                         <SYSC_IDLE_SMART_WKUP>;
1219                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1220                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1221                         clock-names = "fck";
1222                         #address-cells = <1>;
1223                         #size-cells = <1>;
1224                         ranges = <0x0 0x36000 0x1000>;
1225
1226                         timer4: timer@0 {
1227                                 compatible = "ti,omap5430-timer";
1228                                 reg = <0x0 0x80>;
1229                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
1230                                 clock-names = "fck";
1231                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1232                         };
1233                 };
1234
1235                 target-module@3e000 {                   /* 0x4803e000, ap 11 56.0 */
1236                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1237                         ti,hwmods = "timer9";
1238                         reg = <0x3e000 0x4>,
1239                               <0x3e010 0x4>;
1240                         reg-names = "rev", "sysc";
1241                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1242                                          SYSC_OMAP4_SOFTRESET)>;
1243                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1244                                         <SYSC_IDLE_NO>,
1245                                         <SYSC_IDLE_SMART>,
1246                                         <SYSC_IDLE_SMART_WKUP>;
1247                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1248                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1249                         clock-names = "fck";
1250                         #address-cells = <1>;
1251                         #size-cells = <1>;
1252                         ranges = <0x0 0x3e000 0x1000>;
1253
1254                         timer9: timer@0 {
1255                                 compatible = "ti,omap5430-timer";
1256                                 reg = <0x0 0x80>;
1257                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>;
1258                                 clock-names = "fck";
1259                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1260                         };
1261                 };
1262
1263                 gpio7_target: target-module@51000 {             /* 0x48051000, ap 45 2e.0 */
1264                         compatible = "ti,sysc-omap2", "ti,sysc";
1265                         reg = <0x51000 0x4>,
1266                               <0x51010 0x4>,
1267                               <0x51114 0x4>;
1268                         reg-names = "rev", "sysc", "syss";
1269                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1270                                          SYSC_OMAP2_SOFTRESET |
1271                                          SYSC_OMAP2_AUTOIDLE)>;
1272                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1273                                         <SYSC_IDLE_NO>,
1274                                         <SYSC_IDLE_SMART>,
1275                                         <SYSC_IDLE_SMART_WKUP>;
1276                         ti,syss-mask = <1>;
1277                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1278                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1279                                  <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
1280                         clock-names = "fck", "dbclk";
1281                         #address-cells = <1>;
1282                         #size-cells = <1>;
1283                         ranges = <0x0 0x51000 0x1000>;
1284
1285                         gpio7: gpio@0 {
1286                                 compatible = "ti,omap4-gpio";
1287                                 reg = <0x0 0x200>;
1288                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1289                                 gpio-controller;
1290                                 #gpio-cells = <2>;
1291                                 interrupt-controller;
1292                                 #interrupt-cells = <2>;
1293                         };
1294                 };
1295
1296                 target-module@53000 {                   /* 0x48053000, ap 35 36.0 */
1297                         compatible = "ti,sysc-omap2", "ti,sysc";
1298                         reg = <0x53000 0x4>,
1299                               <0x53010 0x4>,
1300                               <0x53114 0x4>;
1301                         reg-names = "rev", "sysc", "syss";
1302                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1303                                          SYSC_OMAP2_SOFTRESET |
1304                                          SYSC_OMAP2_AUTOIDLE)>;
1305                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1306                                         <SYSC_IDLE_NO>,
1307                                         <SYSC_IDLE_SMART>,
1308                                         <SYSC_IDLE_SMART_WKUP>;
1309                         ti,syss-mask = <1>;
1310                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1311                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1312                                  <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
1313                         clock-names = "fck", "dbclk";
1314                         #address-cells = <1>;
1315                         #size-cells = <1>;
1316                         ranges = <0x0 0x53000 0x1000>;
1317
1318                         gpio8: gpio@0 {
1319                                 compatible = "ti,omap4-gpio";
1320                                 reg = <0x0 0x200>;
1321                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1322                                 gpio-controller;
1323                                 #gpio-cells = <2>;
1324                                 interrupt-controller;
1325                                 #interrupt-cells = <2>;
1326                         };
1327                 };
1328
1329                 target-module@55000 {                   /* 0x48055000, ap 13 0e.0 */
1330                         compatible = "ti,sysc-omap2", "ti,sysc";
1331                         reg = <0x55000 0x4>,
1332                               <0x55010 0x4>,
1333                               <0x55114 0x4>;
1334                         reg-names = "rev", "sysc", "syss";
1335                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1336                                          SYSC_OMAP2_SOFTRESET |
1337                                          SYSC_OMAP2_AUTOIDLE)>;
1338                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1339                                         <SYSC_IDLE_NO>,
1340                                         <SYSC_IDLE_SMART>,
1341                                         <SYSC_IDLE_SMART_WKUP>;
1342                         ti,syss-mask = <1>;
1343                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1344                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1345                                  <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
1346                         clock-names = "fck", "dbclk";
1347                         #address-cells = <1>;
1348                         #size-cells = <1>;
1349                         ranges = <0x0 0x55000 0x1000>;
1350
1351                         gpio2: gpio@0 {
1352                                 compatible = "ti,omap4-gpio";
1353                                 reg = <0x0 0x200>;
1354                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1355                                 gpio-controller;
1356                                 #gpio-cells = <2>;
1357                                 interrupt-controller;
1358                                 #interrupt-cells = <2>;
1359                         };
1360                 };
1361
1362                 target-module@57000 {                   /* 0x48057000, ap 15 06.0 */
1363                         compatible = "ti,sysc-omap2", "ti,sysc";
1364                         reg = <0x57000 0x4>,
1365                               <0x57010 0x4>,
1366                               <0x57114 0x4>;
1367                         reg-names = "rev", "sysc", "syss";
1368                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1369                                          SYSC_OMAP2_SOFTRESET |
1370                                          SYSC_OMAP2_AUTOIDLE)>;
1371                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1372                                         <SYSC_IDLE_NO>,
1373                                         <SYSC_IDLE_SMART>,
1374                                         <SYSC_IDLE_SMART_WKUP>;
1375                         ti,syss-mask = <1>;
1376                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1377                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1378                                  <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
1379                         clock-names = "fck", "dbclk";
1380                         #address-cells = <1>;
1381                         #size-cells = <1>;
1382                         ranges = <0x0 0x57000 0x1000>;
1383
1384                         gpio3: gpio@0 {
1385                                 compatible = "ti,omap4-gpio";
1386                                 reg = <0x0 0x200>;
1387                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1388                                 gpio-controller;
1389                                 #gpio-cells = <2>;
1390                                 interrupt-controller;
1391                                 #interrupt-cells = <2>;
1392                         };
1393                 };
1394
1395                 target-module@59000 {                   /* 0x48059000, ap 17 16.0 */
1396                         compatible = "ti,sysc-omap2", "ti,sysc";
1397                         reg = <0x59000 0x4>,
1398                               <0x59010 0x4>,
1399                               <0x59114 0x4>;
1400                         reg-names = "rev", "sysc", "syss";
1401                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1402                                          SYSC_OMAP2_SOFTRESET |
1403                                          SYSC_OMAP2_AUTOIDLE)>;
1404                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1405                                         <SYSC_IDLE_NO>,
1406                                         <SYSC_IDLE_SMART>,
1407                                         <SYSC_IDLE_SMART_WKUP>;
1408                         ti,syss-mask = <1>;
1409                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1410                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1411                                  <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
1412                         clock-names = "fck", "dbclk";
1413                         #address-cells = <1>;
1414                         #size-cells = <1>;
1415                         ranges = <0x0 0x59000 0x1000>;
1416
1417                         gpio4: gpio@0 {
1418                                 compatible = "ti,omap4-gpio";
1419                                 reg = <0x0 0x200>;
1420                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1421                                 gpio-controller;
1422                                 #gpio-cells = <2>;
1423                                 interrupt-controller;
1424                                 #interrupt-cells = <2>;
1425                         };
1426                 };
1427
1428                 target-module@5b000 {                   /* 0x4805b000, ap 19 1e.0 */
1429                         compatible = "ti,sysc-omap2", "ti,sysc";
1430                         reg = <0x5b000 0x4>,
1431                               <0x5b010 0x4>,
1432                               <0x5b114 0x4>;
1433                         reg-names = "rev", "sysc", "syss";
1434                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1435                                          SYSC_OMAP2_SOFTRESET |
1436                                          SYSC_OMAP2_AUTOIDLE)>;
1437                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1438                                         <SYSC_IDLE_NO>,
1439                                         <SYSC_IDLE_SMART>,
1440                                         <SYSC_IDLE_SMART_WKUP>;
1441                         ti,syss-mask = <1>;
1442                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1443                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1444                                  <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
1445                         clock-names = "fck", "dbclk";
1446                         #address-cells = <1>;
1447                         #size-cells = <1>;
1448                         ranges = <0x0 0x5b000 0x1000>;
1449
1450                         gpio5: gpio@0 {
1451                                 compatible = "ti,omap4-gpio";
1452                                 reg = <0x0 0x200>;
1453                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1454                                 gpio-controller;
1455                                 #gpio-cells = <2>;
1456                                 interrupt-controller;
1457                                 #interrupt-cells = <2>;
1458                         };
1459                 };
1460
1461                 target-module@5d000 {                   /* 0x4805d000, ap 21 26.0 */
1462                         compatible = "ti,sysc-omap2", "ti,sysc";
1463                         reg = <0x5d000 0x4>,
1464                               <0x5d010 0x4>,
1465                               <0x5d114 0x4>;
1466                         reg-names = "rev", "sysc", "syss";
1467                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1468                                          SYSC_OMAP2_SOFTRESET |
1469                                          SYSC_OMAP2_AUTOIDLE)>;
1470                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1471                                         <SYSC_IDLE_NO>,
1472                                         <SYSC_IDLE_SMART>,
1473                                         <SYSC_IDLE_SMART_WKUP>;
1474                         ti,syss-mask = <1>;
1475                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1476                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1477                                  <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
1478                         clock-names = "fck", "dbclk";
1479                         #address-cells = <1>;
1480                         #size-cells = <1>;
1481                         ranges = <0x0 0x5d000 0x1000>;
1482
1483                         gpio6: gpio@0 {
1484                                 compatible = "ti,omap4-gpio";
1485                                 reg = <0x0 0x200>;
1486                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1487                                 gpio-controller;
1488                                 #gpio-cells = <2>;
1489                                 interrupt-controller;
1490                                 #interrupt-cells = <2>;
1491                         };
1492                 };
1493
1494                 target-module@60000 {                   /* 0x48060000, ap 23 32.0 */
1495                         compatible = "ti,sysc-omap2", "ti,sysc";
1496                         reg = <0x60000 0x8>,
1497                               <0x60010 0x8>,
1498                               <0x60090 0x8>;
1499                         reg-names = "rev", "sysc", "syss";
1500                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1501                                          SYSC_OMAP2_ENAWAKEUP |
1502                                          SYSC_OMAP2_SOFTRESET |
1503                                          SYSC_OMAP2_AUTOIDLE)>;
1504                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1505                                         <SYSC_IDLE_NO>,
1506                                         <SYSC_IDLE_SMART>,
1507                                         <SYSC_IDLE_SMART_WKUP>;
1508                         ti,syss-mask = <1>;
1509                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1510                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1511                         clock-names = "fck";
1512                         #address-cells = <1>;
1513                         #size-cells = <1>;
1514                         ranges = <0x0 0x60000 0x1000>;
1515
1516                         i2c3: i2c@0 {
1517                                 compatible = "ti,omap4-i2c";
1518                                 reg = <0x0 0x100>;
1519                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1520                                 #address-cells = <1>;
1521                                 #size-cells = <0>;
1522                                 status = "disabled";
1523                         };
1524                 };
1525
1526                 target-module@66000 {                   /* 0x48066000, ap 63 14.0 */
1527                         compatible = "ti,sysc-omap2", "ti,sysc";
1528                         reg = <0x66050 0x4>,
1529                               <0x66054 0x4>,
1530                               <0x66058 0x4>;
1531                         reg-names = "rev", "sysc", "syss";
1532                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1533                                          SYSC_OMAP2_SOFTRESET |
1534                                          SYSC_OMAP2_AUTOIDLE)>;
1535                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1536                                         <SYSC_IDLE_NO>,
1537                                         <SYSC_IDLE_SMART>,
1538                                         <SYSC_IDLE_SMART_WKUP>;
1539                         ti,syss-mask = <1>;
1540                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1541                         clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1542                         clock-names = "fck";
1543                         #address-cells = <1>;
1544                         #size-cells = <1>;
1545                         ranges = <0x0 0x66000 0x1000>;
1546
1547                         uart5: serial@0 {
1548                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1549                                 reg = <0x0 0x100>;
1550                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1551                                 clock-frequency = <48000000>;
1552                                 status = "disabled";
1553                                 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
1554                                 dma-names = "tx", "rx";
1555                         };
1556                 };
1557
1558                 target-module@68000 {                   /* 0x48068000, ap 53 1c.0 */
1559                         compatible = "ti,sysc-omap2", "ti,sysc";
1560                         reg = <0x68050 0x4>,
1561                               <0x68054 0x4>,
1562                               <0x68058 0x4>;
1563                         reg-names = "rev", "sysc", "syss";
1564                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1565                                          SYSC_OMAP2_SOFTRESET |
1566                                          SYSC_OMAP2_AUTOIDLE)>;
1567                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1568                                         <SYSC_IDLE_NO>,
1569                                         <SYSC_IDLE_SMART>,
1570                                         <SYSC_IDLE_SMART_WKUP>;
1571                         ti,syss-mask = <1>;
1572                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1573                         clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1574                         clock-names = "fck";
1575                         #address-cells = <1>;
1576                         #size-cells = <1>;
1577                         ranges = <0x0 0x68000 0x1000>;
1578
1579                         uart6: serial@0 {
1580                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1581                                 reg = <0x0 0x100>;
1582                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1583                                 clock-frequency = <48000000>;
1584                                 status = "disabled";
1585                                 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
1586                                 dma-names = "tx", "rx";
1587                         };
1588                 };
1589
1590                 target-module@6a000 {                   /* 0x4806a000, ap 24 24.0 */
1591                         compatible = "ti,sysc-omap2", "ti,sysc";
1592                         reg = <0x6a050 0x4>,
1593                               <0x6a054 0x4>,
1594                               <0x6a058 0x4>;
1595                         reg-names = "rev", "sysc", "syss";
1596                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1597                                          SYSC_OMAP2_SOFTRESET |
1598                                          SYSC_OMAP2_AUTOIDLE)>;
1599                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1600                                         <SYSC_IDLE_NO>,
1601                                         <SYSC_IDLE_SMART>,
1602                                         <SYSC_IDLE_SMART_WKUP>;
1603                         ti,syss-mask = <1>;
1604                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1605                         clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1606                         clock-names = "fck";
1607                         #address-cells = <1>;
1608                         #size-cells = <1>;
1609                         ranges = <0x0 0x6a000 0x1000>;
1610
1611                         uart1: serial@0 {
1612                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1613                                 reg = <0x0 0x100>;
1614                                 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1615                                 clock-frequency = <48000000>;
1616                                 status = "disabled";
1617                                 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
1618                                 dma-names = "tx", "rx";
1619                         };
1620                 };
1621
1622                 target-module@6c000 {                   /* 0x4806c000, ap 26 2c.0 */
1623                         compatible = "ti,sysc-omap2", "ti,sysc";
1624                         reg = <0x6c050 0x4>,
1625                               <0x6c054 0x4>,
1626                               <0x6c058 0x4>;
1627                         reg-names = "rev", "sysc", "syss";
1628                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1629                                          SYSC_OMAP2_SOFTRESET |
1630                                          SYSC_OMAP2_AUTOIDLE)>;
1631                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1632                                         <SYSC_IDLE_NO>,
1633                                         <SYSC_IDLE_SMART>,
1634                                         <SYSC_IDLE_SMART_WKUP>;
1635                         ti,syss-mask = <1>;
1636                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1637                         clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1638                         clock-names = "fck";
1639                         #address-cells = <1>;
1640                         #size-cells = <1>;
1641                         ranges = <0x0 0x6c000 0x1000>;
1642
1643                         uart2: serial@0 {
1644                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1645                                 reg = <0x0 0x100>;
1646                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1647                                 clock-frequency = <48000000>;
1648                                 status = "disabled";
1649                                 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
1650                                 dma-names = "tx", "rx";
1651                         };
1652                 };
1653
1654                 target-module@6e000 {                   /* 0x4806e000, ap 28 0c.1 */
1655                         compatible = "ti,sysc-omap2", "ti,sysc";
1656                         reg = <0x6e050 0x4>,
1657                               <0x6e054 0x4>,
1658                               <0x6e058 0x4>;
1659                         reg-names = "rev", "sysc", "syss";
1660                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1661                                          SYSC_OMAP2_SOFTRESET |
1662                                          SYSC_OMAP2_AUTOIDLE)>;
1663                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1664                                         <SYSC_IDLE_NO>,
1665                                         <SYSC_IDLE_SMART>,
1666                                         <SYSC_IDLE_SMART_WKUP>;
1667                         ti,syss-mask = <1>;
1668                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1669                         clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1670                         clock-names = "fck";
1671                         #address-cells = <1>;
1672                         #size-cells = <1>;
1673                         ranges = <0x0 0x6e000 0x1000>;
1674
1675                         uart4: serial@0 {
1676                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1677                                 reg = <0x0 0x100>;
1678                                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1679                                 clock-frequency = <48000000>;
1680                                                 status = "disabled";
1681                                 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
1682                                 dma-names = "tx", "rx";
1683                         };
1684                 };
1685
1686                 target-module@70000 {                   /* 0x48070000, ap 30 22.0 */
1687                         compatible = "ti,sysc-omap2", "ti,sysc";
1688                         reg = <0x70000 0x8>,
1689                               <0x70010 0x8>,
1690                               <0x70090 0x8>;
1691                         reg-names = "rev", "sysc", "syss";
1692                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1693                                          SYSC_OMAP2_ENAWAKEUP |
1694                                          SYSC_OMAP2_SOFTRESET |
1695                                          SYSC_OMAP2_AUTOIDLE)>;
1696                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1697                                         <SYSC_IDLE_NO>,
1698                                         <SYSC_IDLE_SMART>,
1699                                         <SYSC_IDLE_SMART_WKUP>;
1700                         ti,syss-mask = <1>;
1701                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1702                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1703                         clock-names = "fck";
1704                         #address-cells = <1>;
1705                         #size-cells = <1>;
1706                         ranges = <0x0 0x70000 0x1000>;
1707
1708                         i2c1: i2c@0 {
1709                                 compatible = "ti,omap4-i2c";
1710                                 reg = <0x0 0x100>;
1711                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1712                                 #address-cells = <1>;
1713                                 #size-cells = <0>;
1714                                 status = "disabled";
1715                         };
1716                 };
1717
1718                 target-module@72000 {                   /* 0x48072000, ap 32 2a.0 */
1719                         compatible = "ti,sysc-omap2", "ti,sysc";
1720                         reg = <0x72000 0x8>,
1721                               <0x72010 0x8>,
1722                               <0x72090 0x8>;
1723                         reg-names = "rev", "sysc", "syss";
1724                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1725                                          SYSC_OMAP2_ENAWAKEUP |
1726                                          SYSC_OMAP2_SOFTRESET |
1727                                          SYSC_OMAP2_AUTOIDLE)>;
1728                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1729                                         <SYSC_IDLE_NO>,
1730                                         <SYSC_IDLE_SMART>,
1731                                         <SYSC_IDLE_SMART_WKUP>;
1732                         ti,syss-mask = <1>;
1733                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1734                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1735                         clock-names = "fck";
1736                         #address-cells = <1>;
1737                         #size-cells = <1>;
1738                         ranges = <0x0 0x72000 0x1000>;
1739
1740                         i2c2: i2c@0 {
1741                                 compatible = "ti,omap4-i2c";
1742                                 reg = <0x0 0x100>;
1743                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1744                                 #address-cells = <1>;
1745                                 #size-cells = <0>;
1746                                 status = "disabled";
1747                         };
1748                 };
1749
1750                 target-module@78000 {                   /* 0x48078000, ap 39 0a.0 */
1751                         compatible = "ti,sysc-omap2", "ti,sysc";
1752                         ti,hwmods = "elm";
1753                         reg = <0x78000 0x4>,
1754                               <0x78010 0x4>,
1755                               <0x78014 0x4>;
1756                         reg-names = "rev", "sysc", "syss";
1757                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1758                                          SYSC_OMAP2_SOFTRESET |
1759                                          SYSC_OMAP2_AUTOIDLE)>;
1760                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1761                                         <SYSC_IDLE_NO>,
1762                                         <SYSC_IDLE_SMART>,
1763                                         <SYSC_IDLE_SMART_WKUP>;
1764                         ti,syss-mask = <1>;
1765                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1766                         clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1767                         clock-names = "fck";
1768                         #address-cells = <1>;
1769                         #size-cells = <1>;
1770                         ranges = <0x0 0x78000 0x1000>;
1771
1772                         elm: elm@0 {
1773                                 compatible = "ti,am3352-elm";
1774                                 reg = <0x0 0xfc0>;      /* device IO registers */
1775                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1776                                 status = "disabled";
1777                         };
1778                 };
1779
1780                 target-module@7a000 {                   /* 0x4807a000, ap 81 3a.0 */
1781                         compatible = "ti,sysc-omap2", "ti,sysc";
1782                         reg = <0x7a000 0x8>,
1783                               <0x7a010 0x8>,
1784                               <0x7a090 0x8>;
1785                         reg-names = "rev", "sysc", "syss";
1786                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1787                                          SYSC_OMAP2_ENAWAKEUP |
1788                                          SYSC_OMAP2_SOFTRESET |
1789                                          SYSC_OMAP2_AUTOIDLE)>;
1790                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1791                                         <SYSC_IDLE_NO>,
1792                                         <SYSC_IDLE_SMART>,
1793                                         <SYSC_IDLE_SMART_WKUP>;
1794                         ti,syss-mask = <1>;
1795                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1796                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1797                         clock-names = "fck";
1798                         #address-cells = <1>;
1799                         #size-cells = <1>;
1800                         ranges = <0x0 0x7a000 0x1000>;
1801
1802                         i2c4: i2c@0 {
1803                                 compatible = "ti,omap4-i2c";
1804                                 reg = <0x0 0x100>;
1805                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1806                                 #address-cells = <1>;
1807                                 #size-cells = <0>;
1808                                 status = "disabled";
1809                         };
1810                 };
1811
1812                 target-module@7c000 {                   /* 0x4807c000, ap 83 4a.0 */
1813                         compatible = "ti,sysc-omap2", "ti,sysc";
1814                         reg = <0x7c000 0x8>,
1815                               <0x7c010 0x8>,
1816                               <0x7c090 0x8>;
1817                         reg-names = "rev", "sysc", "syss";
1818                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1819                                          SYSC_OMAP2_ENAWAKEUP |
1820                                          SYSC_OMAP2_SOFTRESET |
1821                                          SYSC_OMAP2_AUTOIDLE)>;
1822                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1823                                         <SYSC_IDLE_NO>,
1824                                         <SYSC_IDLE_SMART>,
1825                                         <SYSC_IDLE_SMART_WKUP>;
1826                         ti,syss-mask = <1>;
1827                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1828                         clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1829                         clock-names = "fck";
1830                         #address-cells = <1>;
1831                         #size-cells = <1>;
1832                         ranges = <0x0 0x7c000 0x1000>;
1833
1834                         i2c5: i2c@0 {
1835                                 compatible = "ti,omap4-i2c";
1836                                 reg = <0x0 0x100>;
1837                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1838                                 #address-cells = <1>;
1839                                 #size-cells = <0>;
1840                                 status = "disabled";
1841                         };
1842                 };
1843
1844                 target-module@86000 {                   /* 0x48086000, ap 41 5e.0 */
1845                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1846                         ti,hwmods = "timer10";
1847                         reg = <0x86000 0x4>,
1848                               <0x86010 0x4>;
1849                         reg-names = "rev", "sysc";
1850                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1851                                          SYSC_OMAP4_SOFTRESET)>;
1852                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1853                                         <SYSC_IDLE_NO>,
1854                                         <SYSC_IDLE_SMART>,
1855                                         <SYSC_IDLE_SMART_WKUP>;
1856                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1857                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1858                         clock-names = "fck";
1859                         #address-cells = <1>;
1860                         #size-cells = <1>;
1861                         ranges = <0x0 0x86000 0x1000>;
1862
1863                         timer10: timer@0 {
1864                                 compatible = "ti,omap5430-timer";
1865                                 reg = <0x0 0x80>;
1866                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>;
1867                                 clock-names = "fck";
1868                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1869                         };
1870                 };
1871
1872                 target-module@88000 {                   /* 0x48088000, ap 43 66.0 */
1873                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1874                         ti,hwmods = "timer11";
1875                         reg = <0x88000 0x4>,
1876                               <0x88010 0x4>;
1877                         reg-names = "rev", "sysc";
1878                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1879                                          SYSC_OMAP4_SOFTRESET)>;
1880                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1881                                         <SYSC_IDLE_NO>,
1882                                         <SYSC_IDLE_SMART>,
1883                                         <SYSC_IDLE_SMART_WKUP>;
1884                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1885                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1886                         clock-names = "fck";
1887                         #address-cells = <1>;
1888                         #size-cells = <1>;
1889                         ranges = <0x0 0x88000 0x1000>;
1890
1891                         timer11: timer@0 {
1892                                 compatible = "ti,omap5430-timer";
1893                                 reg = <0x0 0x80>;
1894                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>;
1895                                 clock-names = "fck";
1896                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1897                         };
1898                 };
1899
1900                 target-module@90000 {                   /* 0x48090000, ap 55 12.0 */
1901                         compatible = "ti,sysc-omap2", "ti,sysc";
1902                         ti,hwmods = "rng";
1903                         reg = <0x91fe0 0x4>,
1904                               <0x91fe4 0x4>;
1905                         reg-names = "rev", "sysc";
1906                         ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
1907                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1908                                         <SYSC_IDLE_NO>;
1909                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1910                         clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1911                         clock-names = "fck";
1912                         #address-cells = <1>;
1913                         #size-cells = <1>;
1914                         ranges = <0x0 0x90000 0x2000>;
1915
1916                         rng: rng@0 {
1917                                 compatible = "ti,omap4-rng";
1918                                 reg = <0x0 0x2000>;
1919                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1920                                 clocks = <&l3_iclk_div>;
1921                                 clock-names = "fck";
1922                         };
1923                 };
1924
1925                 target-module@98000 {                   /* 0x48098000, ap 47 08.0 */
1926                         compatible = "ti,sysc-omap4", "ti,sysc";
1927                         reg = <0x98000 0x4>,
1928                               <0x98010 0x4>;
1929                         reg-names = "rev", "sysc";
1930                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1931                                          SYSC_OMAP4_SOFTRESET)>;
1932                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1933                                         <SYSC_IDLE_NO>,
1934                                         <SYSC_IDLE_SMART>,
1935                                         <SYSC_IDLE_SMART_WKUP>;
1936                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1937                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1938                         clock-names = "fck";
1939                         #address-cells = <1>;
1940                         #size-cells = <1>;
1941                         ranges = <0x0 0x98000 0x1000>;
1942
1943                         mcspi1: spi@0 {
1944                                 compatible = "ti,omap4-mcspi";
1945                                 reg = <0x0 0x200>;
1946                                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1947                                 #address-cells = <1>;
1948                                 #size-cells = <0>;
1949                                 ti,spi-num-cs = <4>;
1950                                 dmas = <&sdma_xbar 35>,
1951                                        <&sdma_xbar 36>,
1952                                        <&sdma_xbar 37>,
1953                                        <&sdma_xbar 38>,
1954                                        <&sdma_xbar 39>,
1955                                        <&sdma_xbar 40>,
1956                                        <&sdma_xbar 41>,
1957                                        <&sdma_xbar 42>;
1958                                 dma-names = "tx0", "rx0", "tx1", "rx1",
1959                                             "tx2", "rx2", "tx3", "rx3";
1960                                 status = "disabled";
1961                         };
1962                 };
1963
1964                 target-module@9a000 {                   /* 0x4809a000, ap 49 10.0 */
1965                         compatible = "ti,sysc-omap4", "ti,sysc";
1966                         reg = <0x9a000 0x4>,
1967                               <0x9a010 0x4>;
1968                         reg-names = "rev", "sysc";
1969                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1970                                          SYSC_OMAP4_SOFTRESET)>;
1971                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1972                                         <SYSC_IDLE_NO>,
1973                                         <SYSC_IDLE_SMART>,
1974                                         <SYSC_IDLE_SMART_WKUP>;
1975                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1976                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1977                         clock-names = "fck";
1978                         #address-cells = <1>;
1979                         #size-cells = <1>;
1980                         ranges = <0x0 0x9a000 0x1000>;
1981
1982                         mcspi2: spi@0 {
1983                                 compatible = "ti,omap4-mcspi";
1984                                 reg = <0x0 0x200>;
1985                                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1986                                 #address-cells = <1>;
1987                                 #size-cells = <0>;
1988                                 ti,spi-num-cs = <2>;
1989                                 dmas = <&sdma_xbar 43>,
1990                                        <&sdma_xbar 44>,
1991                                        <&sdma_xbar 45>,
1992                                        <&sdma_xbar 46>;
1993                                 dma-names = "tx0", "rx0", "tx1", "rx1";
1994                                 status = "disabled";
1995                         };
1996                 };
1997
1998                 target-module@9c000 {                   /* 0x4809c000, ap 51 38.0 */
1999                         compatible = "ti,sysc-omap4", "ti,sysc";
2000                         reg = <0x9c000 0x4>,
2001                               <0x9c010 0x4>;
2002                         reg-names = "rev", "sysc";
2003                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2004                                          SYSC_OMAP4_SOFTRESET)>;
2005                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2006                                         <SYSC_IDLE_NO>,
2007                                         <SYSC_IDLE_SMART>,
2008                                         <SYSC_IDLE_SMART_WKUP>;
2009                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2010                                         <SYSC_IDLE_NO>,
2011                                         <SYSC_IDLE_SMART>,
2012                                         <SYSC_IDLE_SMART_WKUP>;
2013                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2014                         clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2015                         clock-names = "fck";
2016                         #address-cells = <1>;
2017                         #size-cells = <1>;
2018                         ranges = <0x0 0x9c000 0x1000>;
2019
2020                         mmc1: mmc@0 {
2021                                 compatible = "ti,dra7-sdhci";
2022                                 reg = <0x0 0x400>;
2023                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
2024                                 status = "disabled";
2025                                 pbias-supply = <&pbias_mmc_reg>;
2026                                 max-frequency = <192000000>;
2027                                 mmc-ddr-1_8v;
2028                                 mmc-ddr-3_3v;
2029                         };
2030                 };
2031
2032                 target-module@a2000 {                   /* 0x480a2000, ap 75 02.0 */
2033                         compatible = "ti,sysc";
2034                         status = "disabled";
2035                         #address-cells = <1>;
2036                         #size-cells = <1>;
2037                         ranges = <0x0 0xa2000 0x1000>;
2038                 };
2039
2040                 target-module@a4000 {                   /* 0x480a4000, ap 57 42.0 */
2041                         compatible = "ti,sysc";
2042                         status = "disabled";
2043                         #address-cells = <1>;
2044                         #size-cells = <1>;
2045                         ranges = <0x00000000 0x000a4000 0x00001000>,
2046                                  <0x00001000 0x000a5000 0x00001000>;
2047                 };
2048
2049                 target-module@a8000 {                   /* 0x480a8000, ap 59 1a.0 */
2050                         compatible = "ti,sysc";
2051                         status = "disabled";
2052                         #address-cells = <1>;
2053                         #size-cells = <1>;
2054                         ranges = <0x0 0xa8000 0x4000>;
2055                 };
2056
2057                 target-module@ad000 {                   /* 0x480ad000, ap 61 20.0 */
2058                         compatible = "ti,sysc-omap4", "ti,sysc";
2059                         reg = <0xad000 0x4>,
2060                               <0xad010 0x4>;
2061                         reg-names = "rev", "sysc";
2062                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2063                                          SYSC_OMAP4_SOFTRESET)>;
2064                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2065                                         <SYSC_IDLE_NO>,
2066                                         <SYSC_IDLE_SMART>,
2067                                         <SYSC_IDLE_SMART_WKUP>;
2068                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2069                                         <SYSC_IDLE_NO>,
2070                                         <SYSC_IDLE_SMART>,
2071                                         <SYSC_IDLE_SMART_WKUP>;
2072                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2073                         clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2074                         clock-names = "fck";
2075                         #address-cells = <1>;
2076                         #size-cells = <1>;
2077                         ranges = <0x0 0xad000 0x1000>;
2078
2079                         mmc3: mmc@0 {
2080                                 compatible = "ti,dra7-sdhci";
2081                                 reg = <0x0 0x400>;
2082                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
2083                                 status = "disabled";
2084                                 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
2085                                 max-frequency = <64000000>;
2086                                 /* SDMA is not supported */
2087                                 sdhci-caps-mask = <0x0 0x400000>;
2088                         };
2089                 };
2090
2091                 target-module@b2000 {                   /* 0x480b2000, ap 37 52.0 */
2092                         compatible = "ti,sysc-omap2", "ti,sysc";
2093                         ti,hwmods = "hdq1w";
2094                         reg = <0xb2000 0x4>,
2095                               <0xb2014 0x4>,
2096                               <0xb2018 0x4>;
2097                         reg-names = "rev", "sysc", "syss";
2098                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2099                                          SYSC_OMAP2_AUTOIDLE)>;
2100                         ti,syss-mask = <1>;
2101                         ti,no-reset-on-init;
2102                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2103                         clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2104                         clock-names = "fck";
2105                         #address-cells = <1>;
2106                         #size-cells = <1>;
2107                         ranges = <0x0 0xb2000 0x1000>;
2108
2109                         hdqw1w: 1w@0 {
2110                                 compatible = "ti,omap3-1w";
2111                                 reg = <0x0 0x1000>;
2112                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2113                         };
2114                 };
2115
2116                 target-module@b4000 {                   /* 0x480b4000, ap 65 40.0 */
2117                         compatible = "ti,sysc-omap4", "ti,sysc";
2118                         reg = <0xb4000 0x4>,
2119                               <0xb4010 0x4>;
2120                         reg-names = "rev", "sysc";
2121                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2122                                          SYSC_OMAP4_SOFTRESET)>;
2123                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2124                                         <SYSC_IDLE_NO>,
2125                                         <SYSC_IDLE_SMART>,
2126                                         <SYSC_IDLE_SMART_WKUP>;
2127                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2128                                         <SYSC_IDLE_NO>,
2129                                         <SYSC_IDLE_SMART>,
2130                                         <SYSC_IDLE_SMART_WKUP>;
2131                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2132                         clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2133                         clock-names = "fck";
2134                         #address-cells = <1>;
2135                         #size-cells = <1>;
2136                         ranges = <0x0 0xb4000 0x1000>;
2137
2138                         mmc2: mmc@0 {
2139                                 compatible = "ti,dra7-sdhci";
2140                                 reg = <0x0 0x400>;
2141                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2142                                 status = "disabled";
2143                                 max-frequency = <192000000>;
2144                                 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
2145                                 sdhci-caps-mask = <0x7 0x0>;
2146                                 mmc-hs200-1_8v;
2147                                 mmc-ddr-1_8v;
2148                                 mmc-ddr-3_3v;
2149                         };
2150                 };
2151
2152                 target-module@b8000 {                   /* 0x480b8000, ap 67 48.0 */
2153                         compatible = "ti,sysc-omap4", "ti,sysc";
2154                         reg = <0xb8000 0x4>,
2155                               <0xb8010 0x4>;
2156                         reg-names = "rev", "sysc";
2157                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2158                                          SYSC_OMAP4_SOFTRESET)>;
2159                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2160                                         <SYSC_IDLE_NO>,
2161                                         <SYSC_IDLE_SMART>,
2162                                         <SYSC_IDLE_SMART_WKUP>;
2163                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2164                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2165                         clock-names = "fck";
2166                         #address-cells = <1>;
2167                         #size-cells = <1>;
2168                         ranges = <0x0 0xb8000 0x1000>;
2169
2170                         mcspi3: spi@0 {
2171                                 compatible = "ti,omap4-mcspi";
2172                                 reg = <0x0 0x200>;
2173                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2174                                 #address-cells = <1>;
2175                                 #size-cells = <0>;
2176                                 ti,spi-num-cs = <2>;
2177                                 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
2178                                 dma-names = "tx0", "rx0";
2179                                 status = "disabled";
2180                         };
2181                 };
2182
2183                 target-module@ba000 {                   /* 0x480ba000, ap 69 18.0 */
2184                         compatible = "ti,sysc-omap4", "ti,sysc";
2185                         reg = <0xba000 0x4>,
2186                               <0xba010 0x4>;
2187                         reg-names = "rev", "sysc";
2188                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2189                                          SYSC_OMAP4_SOFTRESET)>;
2190                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2191                                         <SYSC_IDLE_NO>,
2192                                         <SYSC_IDLE_SMART>,
2193                                         <SYSC_IDLE_SMART_WKUP>;
2194                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2195                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2196                         clock-names = "fck";
2197                         #address-cells = <1>;
2198                         #size-cells = <1>;
2199                         ranges = <0x0 0xba000 0x1000>;
2200
2201                         mcspi4: spi@0 {
2202                                 compatible = "ti,omap4-mcspi";
2203                                 reg = <0x0 0x200>;
2204                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
2205                                 #address-cells = <1>;
2206                                 #size-cells = <0>;
2207                                 ti,spi-num-cs = <1>;
2208                                 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
2209                                 dma-names = "tx0", "rx0";
2210                                 status = "disabled";
2211                         };
2212                 };
2213
2214                 target-module@d1000 {                   /* 0x480d1000, ap 71 28.0 */
2215                         compatible = "ti,sysc-omap4", "ti,sysc";
2216                         reg = <0xd1000 0x4>,
2217                               <0xd1010 0x4>;
2218                         reg-names = "rev", "sysc";
2219                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2220                                          SYSC_OMAP4_SOFTRESET)>;
2221                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2222                                         <SYSC_IDLE_NO>,
2223                                         <SYSC_IDLE_SMART>,
2224                                         <SYSC_IDLE_SMART_WKUP>;
2225                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2226                                         <SYSC_IDLE_NO>,
2227                                         <SYSC_IDLE_SMART>,
2228                                         <SYSC_IDLE_SMART_WKUP>;
2229                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2230                         clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2231                         clock-names = "fck";
2232                         #address-cells = <1>;
2233                         #size-cells = <1>;
2234                         ranges = <0x0 0xd1000 0x1000>;
2235
2236                         mmc4: mmc@0 {
2237                                 compatible = "ti,dra7-sdhci";
2238                                 reg = <0x0 0x400>;
2239                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2240                                 status = "disabled";
2241                                 max-frequency = <192000000>;
2242                                 /* SDMA is not supported */
2243                                 sdhci-caps-mask = <0x0 0x400000>;
2244                         };
2245                 };
2246
2247                 target-module@d5000 {                   /* 0x480d5000, ap 73 30.0 */
2248                         compatible = "ti,sysc";
2249                         status = "disabled";
2250                         #address-cells = <1>;
2251                         #size-cells = <1>;
2252                         ranges = <0x0 0xd5000 0x1000>;
2253                 };
2254         };
2255
2256         segment@200000 {                                        /* 0x48200000 */
2257                 compatible = "simple-bus";
2258                 #address-cells = <1>;
2259                 #size-cells = <1>;
2260         };
2261 };
2262
2263 &l4_per2 {                                              /* 0x48400000 */
2264         compatible = "ti,dra7-l4-per2", "simple-bus";
2265         reg = <0x48400000 0x800>,
2266               <0x48400800 0x800>,
2267               <0x48401000 0x400>,
2268               <0x48401400 0x400>,
2269               <0x48401800 0x400>;
2270         reg-names = "ap", "la", "ia0", "ia1", "ia2";
2271         #address-cells = <1>;
2272         #size-cells = <1>;
2273         ranges = <0x00000000 0x48400000 0x400000>,      /* segment 0 */
2274                  <0x45800000 0x45800000 0x400000>,      /* L3 data port */
2275                  <0x45c00000 0x45c00000 0x400000>,      /* L3 data port */
2276                  <0x46000000 0x46000000 0x400000>,      /* L3 data port */
2277                  <0x48436000 0x48436000 0x400000>,      /* L3 data port */
2278                  <0x4843a000 0x4843a000 0x400000>,      /* L3 data port */
2279                  <0x4844c000 0x4844c000 0x400000>,      /* L3 data port */
2280                  <0x48450000 0x48450000 0x400000>,      /* L3 data port */
2281                  <0x48454000 0x48454000 0x400000>;      /* L3 data port */
2282
2283         segment@0 {                                     /* 0x48400000 */
2284                 compatible = "simple-bus";
2285                 #address-cells = <1>;
2286                 #size-cells = <1>;
2287                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
2288                          <0x00001000 0x00001000 0x000400>,      /* ap 1 */
2289                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
2290                          <0x00084000 0x00084000 0x004000>,      /* ap 3 */
2291                          <0x00001400 0x00001400 0x000400>,      /* ap 4 */
2292                          <0x00001800 0x00001800 0x000400>,      /* ap 5 */
2293                          <0x00088000 0x00088000 0x001000>,      /* ap 6 */
2294                          <0x0002c000 0x0002c000 0x001000>,      /* ap 7 */
2295                          <0x0002d000 0x0002d000 0x001000>,      /* ap 8 */
2296                          <0x00060000 0x00060000 0x002000>,      /* ap 9 */
2297                          <0x00062000 0x00062000 0x001000>,      /* ap 10 */
2298                          <0x00064000 0x00064000 0x002000>,      /* ap 11 */
2299                          <0x00066000 0x00066000 0x001000>,      /* ap 12 */
2300                          <0x00068000 0x00068000 0x002000>,      /* ap 13 */
2301                          <0x0006a000 0x0006a000 0x001000>,      /* ap 14 */
2302                          <0x0006c000 0x0006c000 0x002000>,      /* ap 15 */
2303                          <0x0006e000 0x0006e000 0x001000>,      /* ap 16 */
2304                          <0x00036000 0x00036000 0x001000>,      /* ap 17 */
2305                          <0x00037000 0x00037000 0x001000>,      /* ap 18 */
2306                          <0x00070000 0x00070000 0x002000>,      /* ap 19 */
2307                          <0x00072000 0x00072000 0x001000>,      /* ap 20 */
2308                          <0x0003a000 0x0003a000 0x001000>,      /* ap 21 */
2309                          <0x0003b000 0x0003b000 0x001000>,      /* ap 22 */
2310                          <0x0003c000 0x0003c000 0x001000>,      /* ap 23 */
2311                          <0x0003d000 0x0003d000 0x001000>,      /* ap 24 */
2312                          <0x0003e000 0x0003e000 0x001000>,      /* ap 25 */
2313                          <0x0003f000 0x0003f000 0x001000>,      /* ap 26 */
2314                          <0x00040000 0x00040000 0x001000>,      /* ap 27 */
2315                          <0x00041000 0x00041000 0x001000>,      /* ap 28 */
2316                          <0x00042000 0x00042000 0x001000>,      /* ap 29 */
2317                          <0x00043000 0x00043000 0x001000>,      /* ap 30 */
2318                          <0x00080000 0x00080000 0x002000>,      /* ap 31 */
2319                          <0x00082000 0x00082000 0x001000>,      /* ap 32 */
2320                          <0x0004a000 0x0004a000 0x001000>,      /* ap 33 */
2321                          <0x0004b000 0x0004b000 0x001000>,      /* ap 34 */
2322                          <0x00074000 0x00074000 0x002000>,      /* ap 35 */
2323                          <0x00076000 0x00076000 0x001000>,      /* ap 36 */
2324                          <0x00050000 0x00050000 0x001000>,      /* ap 37 */
2325                          <0x00051000 0x00051000 0x001000>,      /* ap 38 */
2326                          <0x00078000 0x00078000 0x002000>,      /* ap 39 */
2327                          <0x0007a000 0x0007a000 0x001000>,      /* ap 40 */
2328                          <0x00054000 0x00054000 0x001000>,      /* ap 41 */
2329                          <0x00055000 0x00055000 0x001000>,      /* ap 42 */
2330                          <0x0007c000 0x0007c000 0x002000>,      /* ap 43 */
2331                          <0x0007e000 0x0007e000 0x001000>,      /* ap 44 */
2332                          <0x0004c000 0x0004c000 0x001000>,      /* ap 45 */
2333                          <0x0004d000 0x0004d000 0x001000>,      /* ap 46 */
2334                          <0x00020000 0x00020000 0x001000>,      /* ap 47 */
2335                          <0x00021000 0x00021000 0x001000>,      /* ap 48 */
2336                          <0x00022000 0x00022000 0x001000>,      /* ap 49 */
2337                          <0x00023000 0x00023000 0x001000>,      /* ap 50 */
2338                          <0x00024000 0x00024000 0x001000>,      /* ap 51 */
2339                          <0x00025000 0x00025000 0x001000>,      /* ap 52 */
2340                          <0x00046000 0x00046000 0x001000>,      /* ap 53 */
2341                          <0x00047000 0x00047000 0x001000>,      /* ap 54 */
2342                          <0x00048000 0x00048000 0x001000>,      /* ap 55 */
2343                          <0x00049000 0x00049000 0x001000>,      /* ap 56 */
2344                          <0x00058000 0x00058000 0x002000>,      /* ap 57 */
2345                          <0x0005a000 0x0005a000 0x001000>,      /* ap 58 */
2346                          <0x0005b000 0x0005b000 0x001000>,      /* ap 59 */
2347                          <0x0005c000 0x0005c000 0x001000>,      /* ap 60 */
2348                          <0x0005d000 0x0005d000 0x001000>,      /* ap 61 */
2349                          <0x0005e000 0x0005e000 0x001000>,      /* ap 62 */
2350                          <0x45800000 0x45800000 0x400000>,      /* L3 data port */
2351                          <0x45c00000 0x45c00000 0x400000>,      /* L3 data port */
2352                          <0x46000000 0x46000000 0x400000>,      /* L3 data port */
2353                          <0x48436000 0x48436000 0x400000>,      /* L3 data port */
2354                          <0x4843a000 0x4843a000 0x400000>,      /* L3 data port */
2355                          <0x4844c000 0x4844c000 0x400000>,      /* L3 data port */
2356                          <0x48450000 0x48450000 0x400000>,      /* L3 data port */
2357                          <0x48454000 0x48454000 0x400000>;      /* L3 data port */
2358
2359                 target-module@20000 {                   /* 0x48420000, ap 47 02.0 */
2360                         compatible = "ti,sysc-omap2", "ti,sysc";
2361                         reg = <0x20050 0x4>,
2362                               <0x20054 0x4>,
2363                               <0x20058 0x4>;
2364                         reg-names = "rev", "sysc", "syss";
2365                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2366                                          SYSC_OMAP2_SOFTRESET |
2367                                          SYSC_OMAP2_AUTOIDLE)>;
2368                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2369                                         <SYSC_IDLE_NO>,
2370                                         <SYSC_IDLE_SMART>,
2371                                         <SYSC_IDLE_SMART_WKUP>;
2372                         ti,syss-mask = <1>;
2373                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2374                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2375                         clock-names = "fck";
2376                         #address-cells = <1>;
2377                         #size-cells = <1>;
2378                         ranges = <0x0 0x20000 0x1000>;
2379
2380                         uart7: serial@0 {
2381                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
2382                                 reg = <0x0 0x100>;
2383                                 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
2384                                 clock-frequency = <48000000>;
2385                                 status = "disabled";
2386                         };
2387                 };
2388
2389                 target-module@22000 {                   /* 0x48422000, ap 49 0a.0 */
2390                         compatible = "ti,sysc-omap2", "ti,sysc";
2391                         reg = <0x22050 0x4>,
2392                               <0x22054 0x4>,
2393                               <0x22058 0x4>;
2394                         reg-names = "rev", "sysc", "syss";
2395                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2396                                          SYSC_OMAP2_SOFTRESET |
2397                                          SYSC_OMAP2_AUTOIDLE)>;
2398                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2399                                         <SYSC_IDLE_NO>,
2400                                         <SYSC_IDLE_SMART>,
2401                                         <SYSC_IDLE_SMART_WKUP>;
2402                         ti,syss-mask = <1>;
2403                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2404                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2405                         clock-names = "fck";
2406                         #address-cells = <1>;
2407                         #size-cells = <1>;
2408                         ranges = <0x0 0x22000 0x1000>;
2409
2410                         uart8: serial@0 {
2411                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
2412                                 reg = <0x0 0x100>;
2413                                 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
2414                                 clock-frequency = <48000000>;
2415                                 status = "disabled";
2416                         };
2417                 };
2418
2419                 target-module@24000 {                   /* 0x48424000, ap 51 12.0 */
2420                         compatible = "ti,sysc-omap2", "ti,sysc";
2421                         reg = <0x24050 0x4>,
2422                               <0x24054 0x4>,
2423                               <0x24058 0x4>;
2424                         reg-names = "rev", "sysc", "syss";
2425                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2426                                          SYSC_OMAP2_SOFTRESET |
2427                                          SYSC_OMAP2_AUTOIDLE)>;
2428                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2429                                         <SYSC_IDLE_NO>,
2430                                         <SYSC_IDLE_SMART>,
2431                                         <SYSC_IDLE_SMART_WKUP>;
2432                         ti,syss-mask = <1>;
2433                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2434                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2435                         clock-names = "fck";
2436                         #address-cells = <1>;
2437                         #size-cells = <1>;
2438                         ranges = <0x0 0x24000 0x1000>;
2439
2440                         uart9: serial@0 {
2441                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
2442                                 reg = <0x0 0x100>;
2443                                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
2444                                 clock-frequency = <48000000>;
2445                                 status = "disabled";
2446                         };
2447                 };
2448
2449                 target-module@2c000 {                   /* 0x4842c000, ap 7 18.0 */
2450                         compatible = "ti,sysc";
2451                         status = "disabled";
2452                         #address-cells = <1>;
2453                         #size-cells = <1>;
2454                         ranges = <0x0 0x2c000 0x1000>;
2455                 };
2456
2457                 target-module@36000 {                   /* 0x48436000, ap 17 06.0 */
2458                         compatible = "ti,sysc";
2459                         status = "disabled";
2460                         #address-cells = <1>;
2461                         #size-cells = <1>;
2462                         ranges = <0x0 0x36000 0x1000>;
2463                 };
2464
2465                 target-module@3a000 {                   /* 0x4843a000, ap 21 3e.0 */
2466                         compatible = "ti,sysc";
2467                         status = "disabled";
2468                         #address-cells = <1>;
2469                         #size-cells = <1>;
2470                         ranges = <0x0 0x3a000 0x1000>;
2471                 };
2472
2473                 atl_tm: target-module@3c000 {           /* 0x4843c000, ap 23 08.0 */
2474                         compatible = "ti,sysc-omap4", "ti,sysc";
2475                         reg = <0x3c000 0x4>;
2476                         reg-names = "rev";
2477                         clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
2478                         clock-names = "fck";
2479                         #address-cells = <1>;
2480                         #size-cells = <1>;
2481                         ranges = <0x0 0x3c000 0x1000>;
2482
2483                         atl: atl@0 {
2484                                 compatible = "ti,dra7-atl";
2485                                 reg = <0x0 0x3ff>;
2486                                 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
2487                                                      <&atl_clkin2_ck>, <&atl_clkin3_ck>;
2488                                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
2489                                 clock-names = "fck";
2490                                 status = "disabled";
2491                         };
2492                 };
2493
2494                 target-module@3e000 {                   /* 0x4843e000, ap 25 30.0 */
2495                         compatible = "ti,sysc-omap4", "ti,sysc";
2496                         ti,hwmods = "epwmss0";
2497                         reg = <0x3e000 0x4>,
2498                               <0x3e004 0x4>;
2499                         reg-names = "rev", "sysc";
2500                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2501                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2502                                         <SYSC_IDLE_NO>,
2503                                         <SYSC_IDLE_SMART>;
2504                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2505                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2506                         clock-names = "fck";
2507                         #address-cells = <1>;
2508                         #size-cells = <1>;
2509                         ranges = <0x0 0x3e000 0x1000>;
2510
2511                         epwmss0: epwmss@0 {
2512                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2513                                 reg = <0x0 0x30>;
2514                                 #address-cells = <1>;
2515                                 #size-cells = <1>;
2516                                 status = "disabled";
2517                                 ranges = <0 0 0x1000>;
2518
2519                                 ecap0: ecap@100 {
2520                                         compatible = "ti,dra746-ecap",
2521                                                      "ti,am3352-ecap";
2522                                         #pwm-cells = <3>;
2523                                         reg = <0x100 0x80>;
2524                                         clocks = <&l4_root_clk_div>;
2525                                         clock-names = "fck";
2526                                         status = "disabled";
2527                                 };
2528
2529                                 ehrpwm0: pwm@200 {
2530                                         compatible = "ti,dra746-ehrpwm",
2531                                                      "ti,am3352-ehrpwm";
2532                                         #pwm-cells = <3>;
2533                                         reg = <0x200 0x80>;
2534                                         clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
2535                                         clock-names = "tbclk", "fck";
2536                                         status = "disabled";
2537                                 };
2538                         };
2539                 };
2540
2541                 target-module@40000 {                   /* 0x48440000, ap 27 38.0 */
2542                         compatible = "ti,sysc-omap4", "ti,sysc";
2543                         ti,hwmods = "epwmss1";
2544                         reg = <0x40000 0x4>,
2545                               <0x40004 0x4>;
2546                         reg-names = "rev", "sysc";
2547                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2548                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2549                                         <SYSC_IDLE_NO>,
2550                                         <SYSC_IDLE_SMART>;
2551                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2552                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2553                         clock-names = "fck";
2554                         #address-cells = <1>;
2555                         #size-cells = <1>;
2556                         ranges = <0x0 0x40000 0x1000>;
2557
2558                         epwmss1: epwmss@0 {
2559                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2560                                 reg = <0x0 0x30>;
2561                                 #address-cells = <1>;
2562                                 #size-cells = <1>;
2563                                 status = "disabled";
2564                                 ranges = <0 0 0x1000>;
2565
2566                                 ecap1: ecap@100 {
2567                                         compatible = "ti,dra746-ecap",
2568                                                      "ti,am3352-ecap";
2569                                         #pwm-cells = <3>;
2570                                         reg = <0x100 0x80>;
2571                                         clocks = <&l4_root_clk_div>;
2572                                         clock-names = "fck";
2573                                         status = "disabled";
2574                                 };
2575
2576                                 ehrpwm1: pwm@200 {
2577                                         compatible = "ti,dra746-ehrpwm",
2578                                                      "ti,am3352-ehrpwm";
2579                                         #pwm-cells = <3>;
2580                                         reg = <0x200 0x80>;
2581                                         clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
2582                                         clock-names = "tbclk", "fck";
2583                                         status = "disabled";
2584                                 };
2585                         };
2586                 };
2587
2588                 target-module@42000 {                   /* 0x48442000, ap 29 20.0 */
2589                         compatible = "ti,sysc-omap4", "ti,sysc";
2590                         ti,hwmods = "epwmss2";
2591                         reg = <0x42000 0x4>,
2592                               <0x42004 0x4>;
2593                         reg-names = "rev", "sysc";
2594                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2595                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2596                                         <SYSC_IDLE_NO>,
2597                                         <SYSC_IDLE_SMART>;
2598                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2599                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2600                         clock-names = "fck";
2601                         #address-cells = <1>;
2602                         #size-cells = <1>;
2603                         ranges = <0x0 0x42000 0x1000>;
2604
2605                         epwmss2: epwmss@0 {
2606                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2607                                 reg = <0x0 0x30>;
2608                                 #address-cells = <1>;
2609                                 #size-cells = <1>;
2610                                 status = "disabled";
2611                                 ranges = <0 0 0x1000>;
2612
2613                                 ecap2: ecap@100 {
2614                                         compatible = "ti,dra746-ecap",
2615                                                      "ti,am3352-ecap";
2616                                         #pwm-cells = <3>;
2617                                         reg = <0x100 0x80>;
2618                                         clocks = <&l4_root_clk_div>;
2619                                         clock-names = "fck";
2620                                         status = "disabled";
2621                                 };
2622
2623                                 ehrpwm2: pwm@200 {
2624                                         compatible = "ti,dra746-ehrpwm",
2625                                                      "ti,am3352-ehrpwm";
2626                                         #pwm-cells = <3>;
2627                                         reg = <0x200 0x80>;
2628                                         clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2629                                         clock-names = "tbclk", "fck";
2630                                         status = "disabled";
2631                                 };
2632                         };
2633                 };
2634
2635                 target-module@46000 {                   /* 0x48446000, ap 53 40.0 */
2636                         compatible = "ti,sysc";
2637                         status = "disabled";
2638                         #address-cells = <1>;
2639                         #size-cells = <1>;
2640                         ranges = <0x0 0x46000 0x1000>;
2641                 };
2642
2643                 target-module@48000 {                   /* 0x48448000, ap 55 48.0 */
2644                         compatible = "ti,sysc";
2645                         status = "disabled";
2646                         #address-cells = <1>;
2647                         #size-cells = <1>;
2648                         ranges = <0x0 0x48000 0x1000>;
2649                 };
2650
2651                 target-module@4a000 {                   /* 0x4844a000, ap 33 1a.0 */
2652                         compatible = "ti,sysc";
2653                         status = "disabled";
2654                         #address-cells = <1>;
2655                         #size-cells = <1>;
2656                         ranges = <0x0 0x4a000 0x1000>;
2657                 };
2658
2659                 target-module@4c000 {                   /* 0x4844c000, ap 45 1c.0 */
2660                         compatible = "ti,sysc";
2661                         status = "disabled";
2662                         #address-cells = <1>;
2663                         #size-cells = <1>;
2664                         ranges = <0x0 0x4c000 0x1000>;
2665                 };
2666
2667                 target-module@50000 {                   /* 0x48450000, ap 37 24.0 */
2668                         compatible = "ti,sysc";
2669                         status = "disabled";
2670                         #address-cells = <1>;
2671                         #size-cells = <1>;
2672                         ranges = <0x0 0x50000 0x1000>;
2673                 };
2674
2675                 target-module@54000 {                   /* 0x48454000, ap 41 2c.0 */
2676                         compatible = "ti,sysc";
2677                         status = "disabled";
2678                         #address-cells = <1>;
2679                         #size-cells = <1>;
2680                         ranges = <0x0 0x54000 0x1000>;
2681                 };
2682
2683                 target-module@58000 {                   /* 0x48458000, ap 57 28.0 */
2684                         compatible = "ti,sysc";
2685                         status = "disabled";
2686                         #address-cells = <1>;
2687                         #size-cells = <1>;
2688                         ranges = <0x0 0x58000 0x2000>;
2689                 };
2690
2691                 target-module@5b000 {                   /* 0x4845b000, ap 59 46.0 */
2692                         compatible = "ti,sysc";
2693                         status = "disabled";
2694                         #address-cells = <1>;
2695                         #size-cells = <1>;
2696                         ranges = <0x0 0x5b000 0x1000>;
2697                 };
2698
2699                 target-module@5d000 {                   /* 0x4845d000, ap 61 22.0 */
2700                         compatible = "ti,sysc";
2701                         status = "disabled";
2702                         #address-cells = <1>;
2703                         #size-cells = <1>;
2704                         ranges = <0x0 0x5d000 0x1000>;
2705                 };
2706
2707                 target-module@60000 {                   /* 0x48460000, ap 9 0e.0 */
2708                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2709                         reg = <0x60000 0x4>,
2710                               <0x60004 0x4>;
2711                         reg-names = "rev", "sysc";
2712                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2713                                         <SYSC_IDLE_NO>,
2714                                         <SYSC_IDLE_SMART>;
2715                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
2716                         clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2717                                  <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2718                                  <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2719                         clock-names = "fck", "ahclkx", "ahclkr";
2720                         #address-cells = <1>;
2721                         #size-cells = <1>;
2722                         ranges = <0x0 0x60000 0x2000>,
2723                                  <0x45800000 0x45800000 0x400000>;
2724
2725                         mcasp1: mcasp@0 {
2726                                 compatible = "ti,dra7-mcasp-audio";
2727                                 reg = <0x0 0x2000>,
2728                                       <0x45800000 0x1000>;      /* L3 data port */
2729                                 reg-names = "mpu","dat";
2730                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2731                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2732                                 interrupt-names = "tx", "rx";
2733                                 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
2734                                 dma-names = "tx", "rx";
2735                                 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>,
2736                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2737                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2738                                 clock-names = "fck", "ahclkx", "ahclkr";
2739                                 status = "disabled";
2740                         };
2741                 };
2742
2743                 target-module@64000 {                   /* 0x48464000, ap 11 1e.0 */
2744                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2745                         reg = <0x64000 0x4>,
2746                               <0x64004 0x4>;
2747                         reg-names = "rev", "sysc";
2748                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2749                                         <SYSC_IDLE_NO>,
2750                                         <SYSC_IDLE_SMART>;
2751                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2752                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2753                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2754                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2755                         clock-names = "fck", "ahclkx", "ahclkr";
2756                         #address-cells = <1>;
2757                         #size-cells = <1>;
2758                         ranges = <0x0 0x64000 0x2000>,
2759                                  <0x45c00000 0x45c00000 0x400000>;
2760
2761                         mcasp2: mcasp@0 {
2762                                 compatible = "ti,dra7-mcasp-audio";
2763                                 reg = <0x0 0x2000>,
2764                                       <0x45c00000 0x1000>;      /* L3 data port */
2765                                 reg-names = "mpu","dat";
2766                                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2767                                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2768                                 interrupt-names = "tx", "rx";
2769                                 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
2770                                 dma-names = "tx", "rx";
2771                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>,
2772                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2773                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2774                                 clock-names = "fck", "ahclkx", "ahclkr";
2775                                 status = "disabled";
2776                         };
2777                 };
2778
2779                 target-module@68000 {                   /* 0x48468000, ap 13 26.0 */
2780                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2781                         reg = <0x68000 0x4>,
2782                               <0x68004 0x4>;
2783                         reg-names = "rev", "sysc";
2784                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2785                                         <SYSC_IDLE_NO>,
2786                                         <SYSC_IDLE_SMART>;
2787                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2788                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2789                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>,
2790                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 28>;
2791                         clock-names = "fck", "ahclkx", "ahclkr";
2792                         #address-cells = <1>;
2793                         #size-cells = <1>;
2794                         ranges = <0x0 0x68000 0x2000>,
2795                                  <0x46000000 0x46000000 0x400000>;
2796
2797                         mcasp3: mcasp@0 {
2798                                 compatible = "ti,dra7-mcasp-audio";
2799                                 reg = <0x0 0x2000>,
2800                                       <0x46000000 0x1000>;      /* L3 data port */
2801                                 reg-names = "mpu","dat";
2802                                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
2803                                              <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2804                                 interrupt-names = "tx", "rx";
2805                                 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
2806                                 dma-names = "tx", "rx";
2807                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>,
2808                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2809                                 clock-names = "fck", "ahclkx";
2810                                 status = "disabled";
2811                         };
2812                 };
2813
2814                 target-module@6c000 {                   /* 0x4846c000, ap 15 2e.0 */
2815                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2816                         reg = <0x6c000 0x4>,
2817                               <0x6c004 0x4>;
2818                         reg-names = "rev", "sysc";
2819                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2820                                         <SYSC_IDLE_NO>,
2821                                         <SYSC_IDLE_SMART>;
2822                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2823                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2824                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>,
2825                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 28>;
2826                         clock-names = "fck", "ahclkx", "ahclkr";
2827                         #address-cells = <1>;
2828                         #size-cells = <1>;
2829                         ranges = <0x0 0x6c000 0x2000>,
2830                                  <0x48436000 0x48436000 0x400000>;
2831
2832                         mcasp4: mcasp@0 {
2833                                 compatible = "ti,dra7-mcasp-audio";
2834                                 reg = <0x0 0x2000>,
2835                                       <0x48436000 0x1000>;      /* L3 data port */
2836                                 reg-names = "mpu","dat";
2837                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
2838                                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
2839                                 interrupt-names = "tx", "rx";
2840                                 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
2841                                 dma-names = "tx", "rx";
2842                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>,
2843                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2844                                 clock-names = "fck", "ahclkx";
2845                                 status = "disabled";
2846                         };
2847                 };
2848
2849                 target-module@70000 {                   /* 0x48470000, ap 19 36.0 */
2850                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2851                         reg = <0x70000 0x4>,
2852                               <0x70004 0x4>;
2853                         reg-names = "rev", "sysc";
2854                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2855                                         <SYSC_IDLE_NO>,
2856                                         <SYSC_IDLE_SMART>;
2857                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2858                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2859                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>,
2860                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 28>;
2861                         clock-names = "fck", "ahclkx", "ahclkr";
2862                         #address-cells = <1>;
2863                         #size-cells = <1>;
2864                         ranges = <0x0 0x70000 0x2000>,
2865                                  <0x4843a000 0x4843a000 0x400000>;
2866
2867                         mcasp5: mcasp@0 {
2868                                 compatible = "ti,dra7-mcasp-audio";
2869                                 reg = <0x0 0x2000>,
2870                                       <0x4843a000 0x1000>;      /* L3 data port */
2871                                 reg-names = "mpu","dat";
2872                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
2873                                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
2874                                 interrupt-names = "tx", "rx";
2875                                 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
2876                                 dma-names = "tx", "rx";
2877                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>,
2878                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2879                                 clock-names = "fck", "ahclkx";
2880                                 status = "disabled";
2881                         };
2882                 };
2883
2884                 target-module@74000 {                   /* 0x48474000, ap 35 14.0 */
2885                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2886                         reg = <0x74000 0x4>,
2887                               <0x74004 0x4>;
2888                         reg-names = "rev", "sysc";
2889                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2890                                         <SYSC_IDLE_NO>,
2891                                         <SYSC_IDLE_SMART>;
2892                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2893                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2894                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>,
2895                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 28>;
2896                         clock-names = "fck", "ahclkx", "ahclkr";
2897                         #address-cells = <1>;
2898                         #size-cells = <1>;
2899                         ranges = <0x0 0x74000 0x2000>,
2900                                  <0x4844c000 0x4844c000 0x400000>;
2901
2902                         mcasp6: mcasp@0 {
2903                                 compatible = "ti,dra7-mcasp-audio";
2904                                 reg = <0x0 0x2000>,
2905                                       <0x4844c000 0x1000>;      /* L3 data port */
2906                                 reg-names = "mpu","dat";
2907                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
2908                                              <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
2909                                 interrupt-names = "tx", "rx";
2910                                 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
2911                                 dma-names = "tx", "rx";
2912                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>,
2913                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2914                                 clock-names = "fck", "ahclkx";
2915                                 status = "disabled";
2916                         };
2917                 };
2918
2919                 target-module@78000 {                   /* 0x48478000, ap 39 0c.0 */
2920                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2921                         reg = <0x78000 0x4>,
2922                               <0x78004 0x4>;
2923                         reg-names = "rev", "sysc";
2924                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2925                                         <SYSC_IDLE_NO>,
2926                                         <SYSC_IDLE_SMART>;
2927                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2928                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2929                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>,
2930                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>;
2931                         clock-names = "fck", "ahclkx", "ahclkr";
2932                         #address-cells = <1>;
2933                         #size-cells = <1>;
2934                         ranges = <0x0 0x78000 0x2000>,
2935                                  <0x48450000 0x48450000 0x400000>;
2936
2937                         mcasp7: mcasp@0 {
2938                                 compatible = "ti,dra7-mcasp-audio";
2939                                 reg = <0x0 0x2000>,
2940                                       <0x48450000 0x1000>;      /* L3 data port */
2941                                 reg-names = "mpu","dat";
2942                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
2943                                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2944                                 interrupt-names = "tx", "rx";
2945                                 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
2946                                 dma-names = "tx", "rx";
2947                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>,
2948                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2949                                 clock-names = "fck", "ahclkx";
2950                                 status = "disabled";
2951                         };
2952                 };
2953
2954                 target-module@7c000 {                   /* 0x4847c000, ap 43 04.0 */
2955                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2956                         reg = <0x7c000 0x4>,
2957                               <0x7c004 0x4>;
2958                         reg-names = "rev", "sysc";
2959                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2960                                         <SYSC_IDLE_NO>,
2961                                         <SYSC_IDLE_SMART>;
2962                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2963                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2964                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>,
2965                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 28>;
2966                         clock-names = "fck", "ahclkx", "ahclkr";
2967                         #address-cells = <1>;
2968                         #size-cells = <1>;
2969                         ranges = <0x0 0x7c000 0x2000>,
2970                                  <0x48454000 0x48454000 0x400000>;
2971
2972                         mcasp8: mcasp@0 {
2973                                 compatible = "ti,dra7-mcasp-audio";
2974                                 reg = <0x0 0x2000>,
2975                                       <0x48454000 0x1000>;      /* L3 data port */
2976                                 reg-names = "mpu","dat";
2977                                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2978                                              <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2979                                 interrupt-names = "tx", "rx";
2980                                 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
2981                                 dma-names = "tx", "rx";
2982                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>,
2983                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2984                                 clock-names = "fck", "ahclkx";
2985                                 status = "disabled";
2986                         };
2987                 };
2988
2989                 target-module@80000 {                   /* 0x48480000, ap 31 16.0 */
2990                         compatible = "ti,sysc-omap4", "ti,sysc";
2991                         reg = <0x80020 0x4>;
2992                         reg-names = "rev";
2993                         clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
2994                         clock-names = "fck";
2995                         #address-cells = <1>;
2996                         #size-cells = <1>;
2997                         ranges = <0x0 0x80000 0x2000>;
2998
2999                         dcan2: can@0 {
3000                                 compatible = "ti,dra7-d_can";
3001                                 reg = <0x0 0x2000>;
3002                                 syscon-raminit = <&scm_conf 0x558 1>;
3003                                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
3004                                 clocks = <&sys_clkin1>;
3005                                 status = "disabled";
3006                         };
3007                 };
3008
3009                 target-module@84000 {                   /* 0x48484000, ap 3 10.0 */
3010                         compatible = "ti,sysc-omap4-simple", "ti,sysc";
3011                         reg = <0x85200 0x4>,
3012                               <0x85208 0x4>,
3013                               <0x85204 0x4>;
3014                         reg-names = "rev", "sysc", "syss";
3015                         ti,sysc-mask = <0>;
3016                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
3017                                         <SYSC_IDLE_NO>;
3018                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3019                                         <SYSC_IDLE_NO>;
3020                         ti,syss-mask = <1>;
3021                         clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3022                         clock-names = "fck";
3023                         #address-cells = <1>;
3024                         #size-cells = <1>;
3025                         ranges = <0x0 0x84000 0x4000>;
3026                         /*
3027                          * Do not allow gating of cpsw clock as workaround
3028                          * for errata i877. Keeping internal clock disabled
3029                          * causes the device switching characteristics
3030                          * to degrade over time and eventually fail to meet
3031                          * the data manual delay time/skew specs.
3032                          */
3033                         ti,no-idle;
3034
3035                         mac: ethernet@0 {
3036                                 compatible = "ti,dra7-cpsw","ti,cpsw";
3037                                 clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3038                                 clock-names = "fck", "cpts";
3039                                 cpdma_channels = <8>;
3040                                 ale_entries = <1024>;
3041                                 bd_ram_size = <0x2000>;
3042                                 mac_control = <0x20>;
3043                                 slaves = <2>;
3044                                 active_slave = <0>;
3045                                 cpts_clock_mult = <0x784CFE14>;
3046                                 cpts_clock_shift = <29>;
3047                                 reg = <0x0 0x1000
3048                                        0x1200 0x2e00>;
3049                                 #address-cells = <1>;
3050                                 #size-cells = <1>;
3051
3052                                 /*
3053                                  * rx_thresh_pend
3054                                  * rx_pend
3055                                  * tx_pend
3056                                  * misc_pend
3057                                  */
3058                                 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3059                                              <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3060                                              <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3061                                              <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3062                                 ranges = <0 0 0x4000>;
3063                                 syscon = <&scm_conf>;
3064                                 status = "disabled";
3065
3066                                 davinci_mdio: mdio@1000 {
3067                                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3068                                         clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3069                                         clock-names = "fck";
3070                                         #address-cells = <1>;
3071                                         #size-cells = <0>;
3072                                         bus_freq = <1000000>;
3073                                         reg = <0x1000 0x100>;
3074                                 };
3075
3076                                 cpsw_emac0: slave@200 {
3077                                         /* Filled in by U-Boot */
3078                                         mac-address = [ 00 00 00 00 00 00 ];
3079                                         phys = <&phy_gmii_sel 1>;
3080                                 };
3081
3082                                 cpsw_emac1: slave@300 {
3083                                         /* Filled in by U-Boot */
3084                                         mac-address = [ 00 00 00 00 00 00 ];
3085                                         phys = <&phy_gmii_sel 2>;
3086                                 };
3087                         };
3088                 };
3089         };
3090 };
3091
3092 &l4_per3 {                                              /* 0x48800000 */
3093         compatible = "ti,dra7-l4-per3", "simple-bus";
3094         reg = <0x48800000 0x800>,
3095               <0x48800800 0x800>,
3096               <0x48801000 0x400>,
3097               <0x48801400 0x400>,
3098               <0x48801800 0x400>;
3099         reg-names = "ap", "la", "ia0", "ia1", "ia2";
3100         #address-cells = <1>;
3101         #size-cells = <1>;
3102         ranges = <0x00000000 0x48800000 0x200000>;      /* segment 0 */
3103
3104         segment@0 {                                     /* 0x48800000 */
3105                 compatible = "simple-bus";
3106                 #address-cells = <1>;
3107                 #size-cells = <1>;
3108                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
3109                          <0x00000800 0x00000800 0x000800>,      /* ap 1 */
3110                          <0x00001000 0x00001000 0x000400>,      /* ap 2 */
3111                          <0x00001400 0x00001400 0x000400>,      /* ap 3 */
3112                          <0x00001800 0x00001800 0x000400>,      /* ap 4 */
3113                          <0x00020000 0x00020000 0x001000>,      /* ap 5 */
3114                          <0x00021000 0x00021000 0x001000>,      /* ap 6 */
3115                          <0x00022000 0x00022000 0x001000>,      /* ap 7 */
3116                          <0x00023000 0x00023000 0x001000>,      /* ap 8 */
3117                          <0x00024000 0x00024000 0x001000>,      /* ap 9 */
3118                          <0x00025000 0x00025000 0x001000>,      /* ap 10 */
3119                          <0x00026000 0x00026000 0x001000>,      /* ap 11 */
3120                          <0x00027000 0x00027000 0x001000>,      /* ap 12 */
3121                          <0x00028000 0x00028000 0x001000>,      /* ap 13 */
3122                          <0x00029000 0x00029000 0x001000>,      /* ap 14 */
3123                          <0x0002a000 0x0002a000 0x001000>,      /* ap 15 */
3124                          <0x0002b000 0x0002b000 0x001000>,      /* ap 16 */
3125                          <0x0002c000 0x0002c000 0x001000>,      /* ap 17 */
3126                          <0x0002d000 0x0002d000 0x001000>,      /* ap 18 */
3127                          <0x0002e000 0x0002e000 0x001000>,      /* ap 19 */
3128                          <0x0002f000 0x0002f000 0x001000>,      /* ap 20 */
3129                          <0x00170000 0x00170000 0x010000>,      /* ap 21 */
3130                          <0x00180000 0x00180000 0x001000>,      /* ap 22 */
3131                          <0x00190000 0x00190000 0x010000>,      /* ap 23 */
3132                          <0x001a0000 0x001a0000 0x001000>,      /* ap 24 */
3133                          <0x001b0000 0x001b0000 0x010000>,      /* ap 25 */
3134                          <0x001c0000 0x001c0000 0x001000>,      /* ap 26 */
3135                          <0x001d0000 0x001d0000 0x010000>,      /* ap 27 */
3136                          <0x001e0000 0x001e0000 0x001000>,      /* ap 28 */
3137                          <0x00038000 0x00038000 0x001000>,      /* ap 29 */
3138                          <0x00039000 0x00039000 0x001000>,      /* ap 30 */
3139                          <0x0005c000 0x0005c000 0x001000>,      /* ap 31 */
3140                          <0x0005d000 0x0005d000 0x001000>,      /* ap 32 */
3141                          <0x0003a000 0x0003a000 0x001000>,      /* ap 33 */
3142                          <0x0003b000 0x0003b000 0x001000>,      /* ap 34 */
3143                          <0x0003c000 0x0003c000 0x001000>,      /* ap 35 */
3144                          <0x0003d000 0x0003d000 0x001000>,      /* ap 36 */
3145                          <0x0003e000 0x0003e000 0x001000>,      /* ap 37 */
3146                          <0x0003f000 0x0003f000 0x001000>,      /* ap 38 */
3147                          <0x00040000 0x00040000 0x001000>,      /* ap 39 */
3148                          <0x00041000 0x00041000 0x001000>,      /* ap 40 */
3149                          <0x00042000 0x00042000 0x001000>,      /* ap 41 */
3150                          <0x00043000 0x00043000 0x001000>,      /* ap 42 */
3151                          <0x00044000 0x00044000 0x001000>,      /* ap 43 */
3152                          <0x00045000 0x00045000 0x001000>,      /* ap 44 */
3153                          <0x00046000 0x00046000 0x001000>,      /* ap 45 */
3154                          <0x00047000 0x00047000 0x001000>,      /* ap 46 */
3155                          <0x00048000 0x00048000 0x001000>,      /* ap 47 */
3156                          <0x00049000 0x00049000 0x001000>,      /* ap 48 */
3157                          <0x0004a000 0x0004a000 0x001000>,      /* ap 49 */
3158                          <0x0004b000 0x0004b000 0x001000>,      /* ap 50 */
3159                          <0x0004c000 0x0004c000 0x001000>,      /* ap 51 */
3160                          <0x0004d000 0x0004d000 0x001000>,      /* ap 52 */
3161                          <0x0004e000 0x0004e000 0x001000>,      /* ap 53 */
3162                          <0x0004f000 0x0004f000 0x001000>,      /* ap 54 */
3163                          <0x00050000 0x00050000 0x001000>,      /* ap 55 */
3164                          <0x00051000 0x00051000 0x001000>,      /* ap 56 */
3165                          <0x00052000 0x00052000 0x001000>,      /* ap 57 */
3166                          <0x00053000 0x00053000 0x001000>,      /* ap 58 */
3167                          <0x00054000 0x00054000 0x001000>,      /* ap 59 */
3168                          <0x00055000 0x00055000 0x001000>,      /* ap 60 */
3169                          <0x00056000 0x00056000 0x001000>,      /* ap 61 */
3170                          <0x00057000 0x00057000 0x001000>,      /* ap 62 */
3171                          <0x00058000 0x00058000 0x001000>,      /* ap 63 */
3172                          <0x00059000 0x00059000 0x001000>,      /* ap 64 */
3173                          <0x0005a000 0x0005a000 0x001000>,      /* ap 65 */
3174                          <0x0005b000 0x0005b000 0x001000>,      /* ap 66 */
3175                          <0x00064000 0x00064000 0x001000>,      /* ap 67 */
3176                          <0x00065000 0x00065000 0x001000>,      /* ap 68 */
3177                          <0x0005e000 0x0005e000 0x001000>,      /* ap 69 */
3178                          <0x0005f000 0x0005f000 0x001000>,      /* ap 70 */
3179                          <0x00060000 0x00060000 0x001000>,      /* ap 71 */
3180                          <0x00061000 0x00061000 0x001000>,      /* ap 72 */
3181                          <0x00062000 0x00062000 0x001000>,      /* ap 73 */
3182                          <0x00063000 0x00063000 0x001000>,      /* ap 74 */
3183                          <0x00140000 0x00140000 0x020000>,      /* ap 75 */
3184                          <0x00160000 0x00160000 0x001000>,      /* ap 76 */
3185                          <0x00016000 0x00016000 0x001000>,      /* ap 77 */
3186                          <0x00017000 0x00017000 0x001000>,      /* ap 78 */
3187                          <0x000c0000 0x000c0000 0x020000>,      /* ap 79 */
3188                          <0x000e0000 0x000e0000 0x001000>,      /* ap 80 */
3189                          <0x00004000 0x00004000 0x001000>,      /* ap 81 */
3190                          <0x00005000 0x00005000 0x001000>,      /* ap 82 */
3191                          <0x00080000 0x00080000 0x020000>,      /* ap 83 */
3192                          <0x000a0000 0x000a0000 0x001000>,      /* ap 84 */
3193                          <0x00100000 0x00100000 0x020000>,      /* ap 85 */
3194                          <0x00120000 0x00120000 0x001000>,      /* ap 86 */
3195                          <0x00010000 0x00010000 0x001000>,      /* ap 87 */
3196                          <0x00011000 0x00011000 0x001000>,      /* ap 88 */
3197                          <0x0000a000 0x0000a000 0x001000>,      /* ap 89 */
3198                          <0x0000b000 0x0000b000 0x001000>,      /* ap 90 */
3199                          <0x0001c000 0x0001c000 0x001000>,      /* ap 91 */
3200                          <0x0001d000 0x0001d000 0x001000>,      /* ap 92 */
3201                          <0x0001e000 0x0001e000 0x001000>,      /* ap 93 */
3202                          <0x0001f000 0x0001f000 0x001000>,      /* ap 94 */
3203                          <0x00002000 0x00002000 0x001000>,      /* ap 95 */
3204                          <0x00003000 0x00003000 0x001000>;      /* ap 96 */
3205
3206                 target-module@2000 {                    /* 0x48802000, ap 95 7c.0 */
3207                         compatible = "ti,sysc-omap4", "ti,sysc";
3208                         ti,hwmods = "mailbox13";
3209                         reg = <0x2000 0x4>,
3210                               <0x2010 0x4>;
3211                         reg-names = "rev", "sysc";
3212                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3213                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3214                                         <SYSC_IDLE_NO>,
3215                                         <SYSC_IDLE_SMART>;
3216                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3217                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
3218                         clock-names = "fck";
3219                         #address-cells = <1>;
3220                         #size-cells = <1>;
3221                         ranges = <0x0 0x2000 0x1000>;
3222
3223                         mailbox13: mailbox@0 {
3224                                 compatible = "ti,omap4-mailbox";
3225                                 reg = <0x0 0x200>;
3226                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
3227                                              <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
3228                                              <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
3229                                              <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
3230                                 #mbox-cells = <1>;
3231                                 ti,mbox-num-users = <4>;
3232                                 ti,mbox-num-fifos = <12>;
3233                                 status = "disabled";
3234                         };
3235                 };
3236
3237                 target-module@4000 {                    /* 0x48804000, ap 81 20.0 */
3238                         compatible = "ti,sysc";
3239                         status = "disabled";
3240                         #address-cells = <1>;
3241                         #size-cells = <1>;
3242                         ranges = <0x0 0x4000 0x1000>;
3243                 };
3244
3245                 target-module@a000 {                    /* 0x4880a000, ap 89 18.0 */
3246                         compatible = "ti,sysc";
3247                         status = "disabled";
3248                         #address-cells = <1>;
3249                         #size-cells = <1>;
3250                         ranges = <0x0 0xa000 0x1000>;
3251                 };
3252
3253                 target-module@10000 {                   /* 0x48810000, ap 87 28.0 */
3254                         compatible = "ti,sysc";
3255                         status = "disabled";
3256                         #address-cells = <1>;
3257                         #size-cells = <1>;
3258                         ranges = <0x0 0x10000 0x1000>;
3259                 };
3260
3261                 target-module@16000 {                   /* 0x48816000, ap 77 1e.0 */
3262                         compatible = "ti,sysc";
3263                         status = "disabled";
3264                         #address-cells = <1>;
3265                         #size-cells = <1>;
3266                         ranges = <0x0 0x16000 0x1000>;
3267                 };
3268
3269                 target-module@1c000 {                   /* 0x4881c000, ap 91 1c.0 */
3270                         compatible = "ti,sysc";
3271                         status = "disabled";
3272                         #address-cells = <1>;
3273                         #size-cells = <1>;
3274                         ranges = <0x0 0x1c000 0x1000>;
3275                 };
3276
3277                 target-module@1e000 {                   /* 0x4881e000, ap 93 2c.0 */
3278                         compatible = "ti,sysc";
3279                         status = "disabled";
3280                         #address-cells = <1>;
3281                         #size-cells = <1>;
3282                         ranges = <0x0 0x1e000 0x1000>;
3283                 };
3284
3285                 target-module@20000 {                   /* 0x48820000, ap 5 08.0 */
3286                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3287                         ti,hwmods = "timer5";
3288                         reg = <0x20000 0x4>,
3289                               <0x20010 0x4>;
3290                         reg-names = "rev", "sysc";
3291                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3292                                          SYSC_OMAP4_SOFTRESET)>;
3293                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3294                                         <SYSC_IDLE_NO>,
3295                                         <SYSC_IDLE_SMART>,
3296                                         <SYSC_IDLE_SMART_WKUP>;
3297                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3298                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3299                         clock-names = "fck";
3300                         #address-cells = <1>;
3301                         #size-cells = <1>;
3302                         ranges = <0x0 0x20000 0x1000>;
3303
3304                         timer5: timer@0 {
3305                                 compatible = "ti,omap5430-timer";
3306                                 reg = <0x0 0x80>;
3307                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>;
3308                                 clock-names = "fck";
3309                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3310                         };
3311                 };
3312
3313                 target-module@22000 {                   /* 0x48822000, ap 7 24.0 */
3314                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3315                         ti,hwmods = "timer6";
3316                         reg = <0x22000 0x4>,
3317                               <0x22010 0x4>;
3318                         reg-names = "rev", "sysc";
3319                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3320                                          SYSC_OMAP4_SOFTRESET)>;
3321                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3322                                         <SYSC_IDLE_NO>,
3323                                         <SYSC_IDLE_SMART>,
3324                                         <SYSC_IDLE_SMART_WKUP>;
3325                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3326                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3327                         clock-names = "fck";
3328                         #address-cells = <1>;
3329                         #size-cells = <1>;
3330                         ranges = <0x0 0x22000 0x1000>;
3331
3332                         timer6: timer@0 {
3333                                 compatible = "ti,omap5430-timer";
3334                                 reg = <0x0 0x80>;
3335                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>;
3336                                 clock-names = "fck";
3337                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3338                         };
3339                 };
3340
3341                 target-module@24000 {                   /* 0x48824000, ap 9 26.0 */
3342                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3343                         ti,hwmods = "timer7";
3344                         reg = <0x24000 0x4>,
3345                               <0x24010 0x4>;
3346                         reg-names = "rev", "sysc";
3347                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3348                                          SYSC_OMAP4_SOFTRESET)>;
3349                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3350                                         <SYSC_IDLE_NO>,
3351                                         <SYSC_IDLE_SMART>,
3352                                         <SYSC_IDLE_SMART_WKUP>;
3353                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3354                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
3355                         clock-names = "fck";
3356                         #address-cells = <1>;
3357                         #size-cells = <1>;
3358                         ranges = <0x0 0x24000 0x1000>;
3359
3360                         timer7: timer@0 {
3361                                 compatible = "ti,omap5430-timer";
3362                                 reg = <0x0 0x80>;
3363                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>;
3364                                 clock-names = "fck";
3365                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3366                         };
3367                 };
3368
3369                 target-module@26000 {                   /* 0x48826000, ap 11 0c.0 */
3370                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3371                         ti,hwmods = "timer8";
3372                         reg = <0x26000 0x4>,
3373                               <0x26010 0x4>;
3374                         reg-names = "rev", "sysc";
3375                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3376                                          SYSC_OMAP4_SOFTRESET)>;
3377                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3378                                         <SYSC_IDLE_NO>,
3379                                         <SYSC_IDLE_SMART>,
3380                                         <SYSC_IDLE_SMART_WKUP>;
3381                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3382                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
3383                         clock-names = "fck";
3384                         #address-cells = <1>;
3385                         #size-cells = <1>;
3386                         ranges = <0x0 0x26000 0x1000>;
3387
3388                         timer8: timer@0 {
3389                                 compatible = "ti,omap5430-timer";
3390                                 reg = <0x0 0x80>;
3391                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>;
3392                                 clock-names = "fck";
3393                                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
3394                         };
3395                 };
3396
3397                 target-module@28000 {                   /* 0x48828000, ap 13 16.0 */
3398                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3399                         ti,hwmods = "timer13";
3400                         reg = <0x28000 0x4>,
3401                               <0x28010 0x4>;
3402                         reg-names = "rev", "sysc";
3403                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3404                                          SYSC_OMAP4_SOFTRESET)>;
3405                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3406                                         <SYSC_IDLE_NO>,
3407                                         <SYSC_IDLE_SMART>,
3408                                         <SYSC_IDLE_SMART_WKUP>;
3409                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3410                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
3411                         clock-names = "fck";
3412                         #address-cells = <1>;
3413                         #size-cells = <1>;
3414                         ranges = <0x0 0x28000 0x1000>;
3415
3416                         timer13: timer@0 {
3417                                 compatible = "ti,omap5430-timer";
3418                                 reg = <0x0 0x80>;
3419                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;
3420                                 clock-names = "fck";
3421                                 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
3422                         };
3423                 };
3424
3425                 target-module@2a000 {                   /* 0x4882a000, ap 15 10.0 */
3426                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3427                         ti,hwmods = "timer14";
3428                         reg = <0x2a000 0x4>,
3429                               <0x2a010 0x4>;
3430                         reg-names = "rev", "sysc";
3431                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3432                                          SYSC_OMAP4_SOFTRESET)>;
3433                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3434                                         <SYSC_IDLE_NO>,
3435                                         <SYSC_IDLE_SMART>,
3436                                         <SYSC_IDLE_SMART_WKUP>;
3437                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3438                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
3439                         clock-names = "fck";
3440                         #address-cells = <1>;
3441                         #size-cells = <1>;
3442                         ranges = <0x0 0x2a000 0x1000>;
3443
3444                         timer14: timer@0 {
3445                                 compatible = "ti,omap5430-timer";
3446                                 reg = <0x0 0x80>;
3447                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
3448                                 clock-names = "fck";
3449                                 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
3450                         };
3451                 };
3452
3453                 target-module@2c000 {                   /* 0x4882c000, ap 17 02.0 */
3454                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3455                         ti,hwmods = "timer15";
3456                         reg = <0x2c000 0x4>,
3457                               <0x2c010 0x4>;
3458                         reg-names = "rev", "sysc";
3459                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3460                                          SYSC_OMAP4_SOFTRESET)>;
3461                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3462                                         <SYSC_IDLE_NO>,
3463                                         <SYSC_IDLE_SMART>,
3464                                         <SYSC_IDLE_SMART_WKUP>;
3465                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3466                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
3467                         clock-names = "fck";
3468                         #address-cells = <1>;
3469                         #size-cells = <1>;
3470                         ranges = <0x0 0x2c000 0x1000>;
3471
3472                         timer15: timer@0 {
3473                                 compatible = "ti,omap5430-timer";
3474                                 reg = <0x0 0x80>;
3475                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
3476                                 clock-names = "fck";
3477                                 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
3478                         };
3479                 };
3480
3481                 target-module@2e000 {                   /* 0x4882e000, ap 19 14.0 */
3482                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3483                         ti,hwmods = "timer16";
3484                         reg = <0x2e000 0x4>,
3485                               <0x2e010 0x4>;
3486                         reg-names = "rev", "sysc";
3487                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3488                                          SYSC_OMAP4_SOFTRESET)>;
3489                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3490                                         <SYSC_IDLE_NO>,
3491                                         <SYSC_IDLE_SMART>,
3492                                         <SYSC_IDLE_SMART_WKUP>;
3493                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3494                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
3495                         clock-names = "fck";
3496                         #address-cells = <1>;
3497                         #size-cells = <1>;
3498                         ranges = <0x0 0x2e000 0x1000>;
3499
3500                         timer16: timer@0 {
3501                                 compatible = "ti,omap5430-timer";
3502                                 reg = <0x0 0x80>;
3503                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
3504                                 clock-names = "fck";
3505                                 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
3506                         };
3507                 };
3508
3509                 rtctarget: target-module@38000 {                        /* 0x48838000, ap 29 12.0 */
3510                         compatible = "ti,sysc-omap4-simple", "ti,sysc";
3511                         ti,hwmods = "rtcss";
3512                         reg = <0x38074 0x4>,
3513                               <0x38078 0x4>;
3514                         reg-names = "rev", "sysc";
3515                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3516                                         <SYSC_IDLE_NO>,
3517                                         <SYSC_IDLE_SMART>,
3518                                         <SYSC_IDLE_SMART_WKUP>;
3519                         /* Domains (P, C): rtc_pwrdm, rtc_clkdm */
3520                         clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
3521                         clock-names = "fck";
3522                         #address-cells = <1>;
3523                         #size-cells = <1>;
3524                         ranges = <0x0 0x38000 0x1000>;
3525
3526                         rtc: rtc@0 {
3527                                 compatible = "ti,am3352-rtc";
3528                                 reg = <0x0 0x100>;
3529                                 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
3530                                              <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
3531                                 clocks = <&sys_32k_ck>;
3532                         };
3533                 };
3534
3535                 target-module@3a000 {                   /* 0x4883a000, ap 33 3e.0 */
3536                         compatible = "ti,sysc-omap4", "ti,sysc";
3537                         ti,hwmods = "mailbox2";
3538                         reg = <0x3a000 0x4>,
3539                               <0x3a010 0x4>;
3540                         reg-names = "rev", "sysc";
3541                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3542                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3543                                         <SYSC_IDLE_NO>,
3544                                         <SYSC_IDLE_SMART>;
3545                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3546                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
3547                         clock-names = "fck";
3548                         #address-cells = <1>;
3549                         #size-cells = <1>;
3550                         ranges = <0x0 0x3a000 0x1000>;
3551
3552                         mailbox2: mailbox@0 {
3553                                 compatible = "ti,omap4-mailbox";
3554                                 reg = <0x0 0x200>;
3555                                 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
3556                                              <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3557                                              <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
3558                                              <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
3559                                 #mbox-cells = <1>;
3560                                 ti,mbox-num-users = <4>;
3561                                 ti,mbox-num-fifos = <12>;
3562                                 status = "disabled";
3563                         };
3564                 };
3565
3566                 target-module@3c000 {                   /* 0x4883c000, ap 35 3a.0 */
3567                         compatible = "ti,sysc-omap4", "ti,sysc";
3568                         ti,hwmods = "mailbox3";
3569                         reg = <0x3c000 0x4>,
3570                               <0x3c010 0x4>;
3571                         reg-names = "rev", "sysc";
3572                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3573                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3574                                         <SYSC_IDLE_NO>,
3575                                         <SYSC_IDLE_SMART>;
3576                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3577                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
3578                         clock-names = "fck";
3579                         #address-cells = <1>;
3580                         #size-cells = <1>;
3581                         ranges = <0x0 0x3c000 0x1000>;
3582
3583                         mailbox3: mailbox@0 {
3584                                 compatible = "ti,omap4-mailbox";
3585                                 reg = <0x0 0x200>;
3586                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3587                                              <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
3588                                              <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
3589                                              <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
3590                                 #mbox-cells = <1>;
3591                                 ti,mbox-num-users = <4>;
3592                                 ti,mbox-num-fifos = <12>;
3593                                 status = "disabled";
3594                         };
3595                 };
3596
3597                 target-module@3e000 {                   /* 0x4883e000, ap 37 46.0 */
3598                         compatible = "ti,sysc-omap4", "ti,sysc";
3599                         ti,hwmods = "mailbox4";
3600                         reg = <0x3e000 0x4>,
3601                               <0x3e010 0x4>;
3602                         reg-names = "rev", "sysc";
3603                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3604                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3605                                         <SYSC_IDLE_NO>,
3606                                         <SYSC_IDLE_SMART>;
3607                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3608                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
3609                         clock-names = "fck";
3610                         #address-cells = <1>;
3611                         #size-cells = <1>;
3612                         ranges = <0x0 0x3e000 0x1000>;
3613
3614                         mailbox4: mailbox@0 {
3615                                 compatible = "ti,omap4-mailbox";
3616                                 reg = <0x0 0x200>;
3617                                 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3618                                              <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
3619                                              <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3620                                              <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
3621                                 #mbox-cells = <1>;
3622                                 ti,mbox-num-users = <4>;
3623                                 ti,mbox-num-fifos = <12>;
3624                                 status = "disabled";
3625                         };
3626                 };
3627
3628                 target-module@40000 {                   /* 0x48840000, ap 39 64.0 */
3629                         compatible = "ti,sysc-omap4", "ti,sysc";
3630                         ti,hwmods = "mailbox5";
3631                         reg = <0x40000 0x4>,
3632                               <0x40010 0x4>;
3633                         reg-names = "rev", "sysc";
3634                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3635                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3636                                         <SYSC_IDLE_NO>,
3637                                         <SYSC_IDLE_SMART>;
3638                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3639                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
3640                         clock-names = "fck";
3641                         #address-cells = <1>;
3642                         #size-cells = <1>;
3643                         ranges = <0x0 0x40000 0x1000>;
3644
3645                         mailbox5: mailbox@0 {
3646                                 compatible = "ti,omap4-mailbox";
3647                                 reg = <0x0 0x200>;
3648                                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3649                                              <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3650                                              <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3651                                              <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
3652                                 #mbox-cells = <1>;
3653                                 ti,mbox-num-users = <4>;
3654                                 ti,mbox-num-fifos = <12>;
3655                                 status = "disabled";
3656                         };
3657                 };
3658
3659                 target-module@42000 {                   /* 0x48842000, ap 41 4e.0 */
3660                         compatible = "ti,sysc-omap4", "ti,sysc";
3661                         ti,hwmods = "mailbox6";
3662                         reg = <0x42000 0x4>,
3663                               <0x42010 0x4>;
3664                         reg-names = "rev", "sysc";
3665                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3666                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3667                                         <SYSC_IDLE_NO>,
3668                                         <SYSC_IDLE_SMART>;
3669                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3670                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
3671                         clock-names = "fck";
3672                         #address-cells = <1>;
3673                         #size-cells = <1>;
3674                         ranges = <0x0 0x42000 0x1000>;
3675
3676                         mailbox6: mailbox@0 {
3677                                 compatible = "ti,omap4-mailbox";
3678                                 reg = <0x0 0x200>;
3679                                 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3680                                              <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3681                                              <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3682                                              <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
3683                                 #mbox-cells = <1>;
3684                                 ti,mbox-num-users = <4>;
3685                                 ti,mbox-num-fifos = <12>;
3686                                 status = "disabled";
3687                         };
3688                 };
3689
3690                 target-module@44000 {                   /* 0x48844000, ap 43 42.0 */
3691                         compatible = "ti,sysc-omap4", "ti,sysc";
3692                         ti,hwmods = "mailbox7";
3693                         reg = <0x44000 0x4>,
3694                               <0x44010 0x4>;
3695                         reg-names = "rev", "sysc";
3696                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3697                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3698                                         <SYSC_IDLE_NO>,
3699                                         <SYSC_IDLE_SMART>;
3700                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3701                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
3702                         clock-names = "fck";
3703                         #address-cells = <1>;
3704                         #size-cells = <1>;
3705                         ranges = <0x0 0x44000 0x1000>;
3706
3707                         mailbox7: mailbox@0 {
3708                                 compatible = "ti,omap4-mailbox";
3709                                 reg = <0x0 0x200>;
3710                                 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
3711                                              <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
3712                                              <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
3713                                              <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
3714                                 #mbox-cells = <1>;
3715                                 ti,mbox-num-users = <4>;
3716                                 ti,mbox-num-fifos = <12>;
3717                                 status = "disabled";
3718                         };
3719                 };
3720
3721                 target-module@46000 {                   /* 0x48846000, ap 45 48.0 */
3722                         compatible = "ti,sysc-omap4", "ti,sysc";
3723                         ti,hwmods = "mailbox8";
3724                         reg = <0x46000 0x4>,
3725                               <0x46010 0x4>;
3726                         reg-names = "rev", "sysc";
3727                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3728                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3729                                         <SYSC_IDLE_NO>,
3730                                         <SYSC_IDLE_SMART>;
3731                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3732                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
3733                         clock-names = "fck";
3734                         #address-cells = <1>;
3735                         #size-cells = <1>;
3736                         ranges = <0x0 0x46000 0x1000>;
3737
3738                         mailbox8: mailbox@0 {
3739                                 compatible = "ti,omap4-mailbox";
3740                                 reg = <0x0 0x200>;
3741                                 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3742                                              <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3743                                              <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3744                                              <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
3745                                 #mbox-cells = <1>;
3746                                 ti,mbox-num-users = <4>;
3747                                 ti,mbox-num-fifos = <12>;
3748                                 status = "disabled";
3749                         };
3750                 };
3751
3752                 target-module@48000 {                   /* 0x48848000, ap 47 36.0 */
3753                         compatible = "ti,sysc";
3754                         status = "disabled";
3755                         #address-cells = <1>;
3756                         #size-cells = <1>;
3757                         ranges = <0x0 0x48000 0x1000>;
3758                 };
3759
3760                 target-module@4a000 {                   /* 0x4884a000, ap 49 38.0 */
3761                         compatible = "ti,sysc";
3762                         status = "disabled";
3763                         #address-cells = <1>;
3764                         #size-cells = <1>;
3765                         ranges = <0x0 0x4a000 0x1000>;
3766                 };
3767
3768                 target-module@4c000 {                   /* 0x4884c000, ap 51 44.0 */
3769                         compatible = "ti,sysc";
3770                         status = "disabled";
3771                         #address-cells = <1>;
3772                         #size-cells = <1>;
3773                         ranges = <0x0 0x4c000 0x1000>;
3774                 };
3775
3776                 target-module@4e000 {                   /* 0x4884e000, ap 53 4c.0 */
3777                         compatible = "ti,sysc";
3778                         status = "disabled";
3779                         #address-cells = <1>;
3780                         #size-cells = <1>;
3781                         ranges = <0x0 0x4e000 0x1000>;
3782                 };
3783
3784                 target-module@50000 {                   /* 0x48850000, ap 55 40.0 */
3785                         compatible = "ti,sysc";
3786                         status = "disabled";
3787                         #address-cells = <1>;
3788                         #size-cells = <1>;
3789                         ranges = <0x0 0x50000 0x1000>;
3790                 };
3791
3792                 target-module@52000 {                   /* 0x48852000, ap 57 54.0 */
3793                         compatible = "ti,sysc";
3794                         status = "disabled";
3795                         #address-cells = <1>;
3796                         #size-cells = <1>;
3797                         ranges = <0x0 0x52000 0x1000>;
3798                 };
3799
3800                 target-module@54000 {                   /* 0x48854000, ap 59 1a.0 */
3801                         compatible = "ti,sysc";
3802                         status = "disabled";
3803                         #address-cells = <1>;
3804                         #size-cells = <1>;
3805                         ranges = <0x0 0x54000 0x1000>;
3806                 };
3807
3808                 target-module@56000 {                   /* 0x48856000, ap 61 22.0 */
3809                         compatible = "ti,sysc";
3810                         status = "disabled";
3811                         #address-cells = <1>;
3812                         #size-cells = <1>;
3813                         ranges = <0x0 0x56000 0x1000>;
3814                 };
3815
3816                 target-module@58000 {                   /* 0x48858000, ap 63 2a.0 */
3817                         compatible = "ti,sysc";
3818                         status = "disabled";
3819                         #address-cells = <1>;
3820                         #size-cells = <1>;
3821                         ranges = <0x0 0x58000 0x1000>;
3822                 };
3823
3824                 target-module@5a000 {                   /* 0x4885a000, ap 65 5c.0 */
3825                         compatible = "ti,sysc";
3826                         status = "disabled";
3827                         #address-cells = <1>;
3828                         #size-cells = <1>;
3829                         ranges = <0x0 0x5a000 0x1000>;
3830                 };
3831
3832                 target-module@5c000 {                   /* 0x4885c000, ap 31 32.0 */
3833                         compatible = "ti,sysc";
3834                         status = "disabled";
3835                         #address-cells = <1>;
3836                         #size-cells = <1>;
3837                         ranges = <0x0 0x5c000 0x1000>;
3838                 };
3839
3840                 target-module@5e000 {                   /* 0x4885e000, ap 69 6c.0 */
3841                         compatible = "ti,sysc-omap4", "ti,sysc";
3842                         ti,hwmods = "mailbox9";
3843                         reg = <0x5e000 0x4>,
3844                               <0x5e010 0x4>;
3845                         reg-names = "rev", "sysc";
3846                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3847                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3848                                         <SYSC_IDLE_NO>,
3849                                         <SYSC_IDLE_SMART>;
3850                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3851                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
3852                         clock-names = "fck";
3853                         #address-cells = <1>;
3854                         #size-cells = <1>;
3855                         ranges = <0x0 0x5e000 0x1000>;
3856
3857                         mailbox9: mailbox@0 {
3858                                 compatible = "ti,omap4-mailbox";
3859                                 reg = <0x0 0x200>;
3860                                 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
3861                                              <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3862                                              <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3863                                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3864                                 #mbox-cells = <1>;
3865                                 ti,mbox-num-users = <4>;
3866                                 ti,mbox-num-fifos = <12>;
3867                                 status = "disabled";
3868                         };
3869                 };
3870
3871                 target-module@60000 {                   /* 0x48860000, ap 71 4a.0 */
3872                         compatible = "ti,sysc-omap4", "ti,sysc";
3873                         ti,hwmods = "mailbox10";
3874                         reg = <0x60000 0x4>,
3875                               <0x60010 0x4>;
3876                         reg-names = "rev", "sysc";
3877                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3878                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3879                                         <SYSC_IDLE_NO>,
3880                                         <SYSC_IDLE_SMART>;
3881                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3882                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
3883                         clock-names = "fck";
3884                         #address-cells = <1>;
3885                         #size-cells = <1>;
3886                         ranges = <0x0 0x60000 0x1000>;
3887
3888                         mailbox10: mailbox@0 {
3889                                 compatible = "ti,omap4-mailbox";
3890                                 reg = <0x0 0x200>;
3891                                 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
3892                                              <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
3893                                              <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
3894                                              <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3895                                 #mbox-cells = <1>;
3896                                 ti,mbox-num-users = <4>;
3897                                 ti,mbox-num-fifos = <12>;
3898                                 status = "disabled";
3899                         };
3900                 };
3901
3902                 target-module@62000 {                   /* 0x48862000, ap 73 74.0 */
3903                         compatible = "ti,sysc-omap4", "ti,sysc";
3904                         ti,hwmods = "mailbox11";
3905                         reg = <0x62000 0x4>,
3906                               <0x62010 0x4>;
3907                         reg-names = "rev", "sysc";
3908                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3909                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3910                                         <SYSC_IDLE_NO>,
3911                                         <SYSC_IDLE_SMART>;
3912                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3913                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
3914                         clock-names = "fck";
3915                         #address-cells = <1>;
3916                         #size-cells = <1>;
3917                         ranges = <0x0 0x62000 0x1000>;
3918
3919                         mailbox11: mailbox@0 {
3920                                 compatible = "ti,omap4-mailbox";
3921                                 reg = <0x0 0x200>;
3922                                 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
3923                                              <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
3924                                              <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
3925                                              <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
3926                                 #mbox-cells = <1>;
3927                                 ti,mbox-num-users = <4>;
3928                                 ti,mbox-num-fifos = <12>;
3929                                 status = "disabled";
3930                         };
3931                 };
3932
3933                 target-module@64000 {                   /* 0x48864000, ap 67 52.0 */
3934                         compatible = "ti,sysc-omap4", "ti,sysc";
3935                         ti,hwmods = "mailbox12";
3936                         reg = <0x64000 0x4>,
3937                               <0x64010 0x4>;
3938                         reg-names = "rev", "sysc";
3939                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3940                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3941                                         <SYSC_IDLE_NO>,
3942                                         <SYSC_IDLE_SMART>;
3943                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3944                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
3945                         clock-names = "fck";
3946                         #address-cells = <1>;
3947                         #size-cells = <1>;
3948                         ranges = <0x0 0x64000 0x1000>;
3949
3950                         mailbox12: mailbox@0 {
3951                                 compatible = "ti,omap4-mailbox";
3952                                 reg = <0x0 0x200>;
3953                                 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
3954                                              <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
3955                                              <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
3956                                              <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
3957                                 #mbox-cells = <1>;
3958                                 ti,mbox-num-users = <4>;
3959                                 ti,mbox-num-fifos = <12>;
3960                                 status = "disabled";
3961                         };
3962                 };
3963
3964                 target-module@80000 {                   /* 0x48880000, ap 83 0e.1 */
3965                         compatible = "ti,sysc-omap4", "ti,sysc";
3966                         ti,hwmods = "usb_otg_ss1";
3967                         reg = <0x80000 0x4>,
3968                               <0x80010 0x4>;
3969                         reg-names = "rev", "sysc";
3970                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
3971                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
3972                                         <SYSC_IDLE_NO>,
3973                                         <SYSC_IDLE_SMART>,
3974                                         <SYSC_IDLE_SMART_WKUP>;
3975                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3976                                         <SYSC_IDLE_NO>,
3977                                         <SYSC_IDLE_SMART>,
3978                                         <SYSC_IDLE_SMART_WKUP>;
3979                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
3980                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
3981                         clock-names = "fck";
3982                         #address-cells = <1>;
3983                         #size-cells = <1>;
3984                         ranges = <0x0 0x80000 0x20000>;
3985
3986                         omap_dwc3_1: omap_dwc3_1@0 {
3987                                 compatible = "ti,dwc3";
3988                                 reg = <0x0 0x10000>;
3989                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
3990                                 #address-cells = <1>;
3991                                 #size-cells = <1>;
3992                                 utmi-mode = <2>;
3993                                 ranges = <0 0 0x20000>;
3994
3995                                 usb1: usb@10000 {
3996                                         compatible = "snps,dwc3";
3997                                         reg = <0x10000 0x17000>;
3998                                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
3999                                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
4000                                                      <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4001                                         interrupt-names = "peripheral",
4002                                                           "host",
4003                                                           "otg";
4004                                         phys = <&usb2_phy1>, <&usb3_phy1>;
4005                                         phy-names = "usb2-phy", "usb3-phy";
4006                                         maximum-speed = "super-speed";
4007                                         dr_mode = "otg";
4008                                         snps,dis_u3_susphy_quirk;
4009                                         snps,dis_u2_susphy_quirk;
4010                                 };
4011                         };
4012                 };
4013
4014                 target-module@c0000 {                   /* 0x488c0000, ap 79 06.0 */
4015                         compatible = "ti,sysc-omap4", "ti,sysc";
4016                         ti,hwmods = "usb_otg_ss2";
4017                         reg = <0xc0000 0x4>,
4018                               <0xc0010 0x4>;
4019                         reg-names = "rev", "sysc";
4020                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4021                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4022                                         <SYSC_IDLE_NO>,
4023                                         <SYSC_IDLE_SMART>,
4024                                         <SYSC_IDLE_SMART_WKUP>;
4025                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4026                                         <SYSC_IDLE_NO>,
4027                                         <SYSC_IDLE_SMART>,
4028                                         <SYSC_IDLE_SMART_WKUP>;
4029                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4030                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
4031                         clock-names = "fck";
4032                         #address-cells = <1>;
4033                         #size-cells = <1>;
4034                         ranges = <0x0 0xc0000 0x20000>;
4035
4036                         omap_dwc3_2: omap_dwc3_2@0 {
4037                                 compatible = "ti,dwc3";
4038                                 reg = <0x0 0x10000>;
4039                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4040                                 #address-cells = <1>;
4041                                 #size-cells = <1>;
4042                                 utmi-mode = <2>;
4043                                 ranges = <0 0 0x20000>;
4044
4045                                 usb2: usb@10000 {
4046                                         compatible = "snps,dwc3";
4047                                         reg = <0x10000 0x17000>;
4048                                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4049                                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4050                                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4051                                         interrupt-names = "peripheral",
4052                                                           "host",
4053                                                           "otg";
4054                                         phys = <&usb2_phy2>;
4055                                         phy-names = "usb2-phy";
4056                                         maximum-speed = "high-speed";
4057                                         dr_mode = "otg";
4058                                         snps,dis_u3_susphy_quirk;
4059                                         snps,dis_u2_susphy_quirk;
4060                                         snps,dis_metastability_quirk;
4061                                 };
4062                         };
4063                 };
4064
4065                 usb3_tm: target-module@100000 {         /* 0x48900000, ap 85 04.0 */
4066                         compatible = "ti,sysc-omap4", "ti,sysc";
4067                         ti,hwmods = "usb_otg_ss3";
4068                         reg = <0x100000 0x4>,
4069                               <0x100010 0x4>;
4070                         reg-names = "rev", "sysc";
4071                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4072                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4073                                         <SYSC_IDLE_NO>,
4074                                         <SYSC_IDLE_SMART>,
4075                                         <SYSC_IDLE_SMART_WKUP>;
4076                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4077                                         <SYSC_IDLE_NO>,
4078                                         <SYSC_IDLE_SMART>,
4079                                         <SYSC_IDLE_SMART_WKUP>;
4080                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4081                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
4082                         clock-names = "fck";
4083                         #address-cells = <1>;
4084                         #size-cells = <1>;
4085                         ranges = <0x0 0x100000 0x20000>;
4086
4087                         omap_dwc3_3: omap_dwc3_3@0 {
4088                                 compatible = "ti,dwc3";
4089                                 reg = <0x0 0x10000>;
4090                                 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4091                                 #address-cells = <1>;
4092                                 #size-cells = <1>;
4093                                 utmi-mode = <2>;
4094                                 ranges = <0 0 0x20000>;
4095                                 status = "disabled";
4096
4097                                 usb3: usb@10000 {
4098                                         compatible = "snps,dwc3";
4099                                         reg = <0x10000 0x17000>;
4100                                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4101                                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4102                                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4103                                         interrupt-names = "peripheral",
4104                                                           "host",
4105                                                           "otg";
4106                                         maximum-speed = "high-speed";
4107                                         dr_mode = "otg";
4108                                         snps,dis_u3_susphy_quirk;
4109                                         snps,dis_u2_susphy_quirk;
4110                                 };
4111                         };
4112                 };
4113
4114                 usb4_tm: target-module@140000 {         /* 0x48940000, ap 75 3c.0 */
4115                         compatible = "ti,sysc-omap4", "ti,sysc";
4116                         ti,hwmods = "usb_otg_ss4";
4117                         reg = <0x140000 0x4>,
4118                               <0x140010 0x4>;
4119                         reg-names = "rev", "sysc";
4120                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4121                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4122                                         <SYSC_IDLE_NO>,
4123                                         <SYSC_IDLE_SMART>,
4124                                         <SYSC_IDLE_SMART_WKUP>;
4125                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4126                                         <SYSC_IDLE_NO>,
4127                                         <SYSC_IDLE_SMART>,
4128                                         <SYSC_IDLE_SMART_WKUP>;
4129                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4130                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
4131                         clock-names = "fck";
4132                         #address-cells = <1>;
4133                         #size-cells = <1>;
4134                         ranges = <0x0 0x140000 0x20000>;
4135                 };
4136
4137                 target-module@170000 {                  /* 0x48970000, ap 21 0a.0 */
4138                         compatible = "ti,sysc";
4139                         status = "disabled";
4140                         #address-cells = <1>;
4141                         #size-cells = <1>;
4142                         ranges = <0x0 0x170000 0x10000>;
4143                 };
4144
4145                 target-module@190000 {                  /* 0x48990000, ap 23 2e.0 */
4146                         compatible = "ti,sysc";
4147                         status = "disabled";
4148                         #address-cells = <1>;
4149                         #size-cells = <1>;
4150                         ranges = <0x0 0x190000 0x10000>;
4151                 };
4152
4153                 target-module@1b0000 {                  /* 0x489b0000, ap 25 34.0 */
4154                         compatible = "ti,sysc";
4155                         status = "disabled";
4156                         #address-cells = <1>;
4157                         #size-cells = <1>;
4158                         ranges = <0x0 0x1b0000 0x10000>;
4159                 };
4160
4161                 target-module@1d0000 {                  /* 0x489d0000, ap 27 30.0 */
4162                         compatible = "ti,sysc";
4163                         status = "disabled";
4164                         #address-cells = <1>;
4165                         #size-cells = <1>;
4166                         ranges = <0x0 0x1d0000 0x10000>;
4167                 };
4168         };
4169 };
4170
4171 &l4_wkup {                                              /* 0x4ae00000 */
4172         compatible = "ti,dra7-l4-wkup", "simple-bus";
4173         reg = <0x4ae00000 0x800>,
4174               <0x4ae00800 0x800>,
4175               <0x4ae01000 0x1000>;
4176         reg-names = "ap", "la", "ia0";
4177         #address-cells = <1>;
4178         #size-cells = <1>;
4179         ranges = <0x00000000 0x4ae00000 0x010000>,      /* segment 0 */
4180                  <0x00010000 0x4ae10000 0x010000>,      /* segment 1 */
4181                  <0x00020000 0x4ae20000 0x010000>,      /* segment 2 */
4182                  <0x00030000 0x4ae30000 0x010000>;      /* segment 3 */
4183
4184         segment@0 {                                     /* 0x4ae00000 */
4185                 compatible = "simple-bus";
4186                 #address-cells = <1>;
4187                 #size-cells = <1>;
4188                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
4189                          <0x00001000 0x00001000 0x001000>,      /* ap 1 */
4190                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
4191                          <0x00006000 0x00006000 0x002000>,      /* ap 3 */
4192                          <0x00008000 0x00008000 0x001000>,      /* ap 4 */
4193                          <0x00004000 0x00004000 0x001000>,      /* ap 15 */
4194                          <0x00005000 0x00005000 0x001000>,      /* ap 16 */
4195                          <0x0000c000 0x0000c000 0x001000>,      /* ap 17 */
4196                          <0x0000d000 0x0000d000 0x001000>;      /* ap 18 */
4197
4198                 target-module@4000 {                    /* 0x4ae04000, ap 15 40.0 */
4199                         compatible = "ti,sysc-omap2", "ti,sysc";
4200                         ti,hwmods = "counter_32k";
4201                         reg = <0x4000 0x4>,
4202                               <0x4010 0x4>;
4203                         reg-names = "rev", "sysc";
4204                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4205                                         <SYSC_IDLE_NO>,
4206                                         <SYSC_IDLE_SMART>,
4207                                         <SYSC_IDLE_SMART_WKUP>;
4208                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4209                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
4210                         clock-names = "fck";
4211                         #address-cells = <1>;
4212                         #size-cells = <1>;
4213                         ranges = <0x0 0x4000 0x1000>;
4214
4215                         counter32k: counter@0 {
4216                                 compatible = "ti,omap-counter32k";
4217                                 reg = <0x0 0x40>;
4218                         };
4219                 };
4220
4221                 target-module@6000 {                    /* 0x4ae06000, ap 3 10.0 */
4222                         compatible = "ti,sysc-omap4", "ti,sysc";
4223                         reg = <0x6000 0x4>;
4224                         reg-names = "rev";
4225                         #address-cells = <1>;
4226                         #size-cells = <1>;
4227                         ranges = <0x0 0x6000 0x2000>;
4228
4229                         prm: prm@0 {
4230                                 compatible = "ti,dra7-prm", "simple-bus";
4231                                 reg = <0 0x3000>;
4232                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4233                                 #address-cells = <1>;
4234                                 #size-cells = <1>;
4235                                 ranges = <0 0 0x3000>;
4236
4237                                 prm_clocks: clocks {
4238                                         #address-cells = <1>;
4239                                         #size-cells = <0>;
4240                                 };
4241
4242                                 prm_clockdomains: clockdomains {
4243                                 };
4244                         };
4245                 };
4246
4247                 target-module@c000 {                    /* 0x4ae0c000, ap 17 50.0 */
4248                         compatible = "ti,sysc-omap4", "ti,sysc";
4249                         reg = <0xc000 0x4>;
4250                         reg-names = "rev";
4251                         #address-cells = <1>;
4252                         #size-cells = <1>;
4253                         ranges = <0x0 0xc000 0x1000>;
4254
4255                         scm_wkup: scm_conf@0 {
4256                                 compatible = "syscon";
4257                                 reg = <0 0x1000>;
4258                         };
4259                 };
4260         };
4261
4262         segment@10000 {                                 /* 0x4ae10000 */
4263                 compatible = "simple-bus";
4264                 #address-cells = <1>;
4265                 #size-cells = <1>;
4266                 ranges = <0x00000000 0x00010000 0x001000>,      /* ap 5 */
4267                          <0x00001000 0x00011000 0x001000>,      /* ap 6 */
4268                          <0x00004000 0x00014000 0x001000>,      /* ap 7 */
4269                          <0x00005000 0x00015000 0x001000>,      /* ap 8 */
4270                          <0x00008000 0x00018000 0x001000>,      /* ap 9 */
4271                          <0x00009000 0x00019000 0x001000>,      /* ap 10 */
4272                          <0x0000c000 0x0001c000 0x001000>,      /* ap 11 */
4273                          <0x0000d000 0x0001d000 0x001000>;      /* ap 12 */
4274
4275                 target-module@0 {                       /* 0x4ae10000, ap 5 20.0 */
4276                         compatible = "ti,sysc-omap2", "ti,sysc";
4277                         reg = <0x0 0x4>,
4278                               <0x10 0x4>,
4279                               <0x114 0x4>;
4280                         reg-names = "rev", "sysc", "syss";
4281                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4282                                          SYSC_OMAP2_SOFTRESET |
4283                                          SYSC_OMAP2_AUTOIDLE)>;
4284                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4285                                         <SYSC_IDLE_NO>,
4286                                         <SYSC_IDLE_SMART>,
4287                                         <SYSC_IDLE_SMART_WKUP>;
4288                         ti,syss-mask = <1>;
4289                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4290                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
4291                                  <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>;
4292                         clock-names = "fck", "dbclk";
4293                         #address-cells = <1>;
4294                         #size-cells = <1>;
4295                         ranges = <0x0 0x0 0x1000>;
4296
4297                         gpio1: gpio@0 {
4298                                 compatible = "ti,omap4-gpio";
4299                                 reg = <0x0 0x200>;
4300                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
4301                                 gpio-controller;
4302                                 #gpio-cells = <2>;
4303                                 interrupt-controller;
4304                                 #interrupt-cells = <2>;
4305                         };
4306                 };
4307
4308                 target-module@4000 {                    /* 0x4ae14000, ap 7 28.0 */
4309                         compatible = "ti,sysc-omap2", "ti,sysc";
4310                         ti,hwmods = "wd_timer2";
4311                         reg = <0x4000 0x4>,
4312                               <0x4010 0x4>,
4313                               <0x4014 0x4>;
4314                         reg-names = "rev", "sysc", "syss";
4315                         ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
4316                                          SYSC_OMAP2_SOFTRESET)>;
4317                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4318                                         <SYSC_IDLE_NO>,
4319                                         <SYSC_IDLE_SMART>,
4320                                         <SYSC_IDLE_SMART_WKUP>;
4321                         ti,syss-mask = <1>;
4322                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4323                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
4324                         clock-names = "fck";
4325                         #address-cells = <1>;
4326                         #size-cells = <1>;
4327                         ranges = <0x0 0x4000 0x1000>;
4328
4329                         wdt2: wdt@0 {
4330                                 compatible = "ti,omap3-wdt";
4331                                 reg = <0x0 0x80>;
4332                                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4333                         };
4334                 };
4335
4336                 target-module@8000 {                    /* 0x4ae18000, ap 9 30.0 */
4337                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
4338                         ti,hwmods = "timer1";
4339                         reg = <0x8000 0x4>,
4340                               <0x8010 0x4>;
4341                         reg-names = "rev", "sysc";
4342                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4343                                          SYSC_OMAP4_SOFTRESET)>;
4344                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4345                                         <SYSC_IDLE_NO>,
4346                                         <SYSC_IDLE_SMART>,
4347                                         <SYSC_IDLE_SMART_WKUP>;
4348                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4349                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
4350                         clock-names = "fck";
4351                         #address-cells = <1>;
4352                         #size-cells = <1>;
4353                         ranges = <0x0 0x8000 0x1000>;
4354
4355                         timer1: timer@0 {
4356                                 compatible = "ti,omap5430-timer";
4357                                 reg = <0x0 0x80>;
4358                                 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
4359                                 clock-names = "fck";
4360                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4361                                 ti,timer-alwon;
4362                         };
4363                 };
4364
4365                 target-module@c000 {                    /* 0x4ae1c000, ap 11 38.0 */
4366                         compatible = "ti,sysc";
4367                         status = "disabled";
4368                         #address-cells = <1>;
4369                         #size-cells = <1>;
4370                         ranges = <0x0 0xc000 0x1000>;
4371                 };
4372         };
4373
4374         segment@20000 {                                 /* 0x4ae20000 */
4375                 compatible = "simple-bus";
4376                 #address-cells = <1>;
4377                 #size-cells = <1>;
4378                 ranges = <0x00006000 0x00026000 0x001000>,      /* ap 13 */
4379                          <0x0000a000 0x0002a000 0x001000>,      /* ap 14 */
4380                          <0x00000000 0x00020000 0x001000>,      /* ap 19 */
4381                          <0x00001000 0x00021000 0x001000>,      /* ap 20 */
4382                          <0x00002000 0x00022000 0x001000>,      /* ap 21 */
4383                          <0x00003000 0x00023000 0x001000>,      /* ap 22 */
4384                          <0x00007000 0x00027000 0x000400>,      /* ap 23 */
4385                          <0x00008000 0x00028000 0x000800>,      /* ap 24 */
4386                          <0x00009000 0x00029000 0x000100>,      /* ap 25 */
4387                          <0x00008800 0x00028800 0x000200>,      /* ap 26 */
4388                          <0x00008a00 0x00028a00 0x000100>,      /* ap 27 */
4389                          <0x0000b000 0x0002b000 0x001000>,      /* ap 28 */
4390                          <0x0000c000 0x0002c000 0x001000>,      /* ap 29 */
4391                          <0x0000f000 0x0002f000 0x001000>;      /* ap 32 */
4392
4393                 target-module@0 {                       /* 0x4ae20000, ap 19 08.0 */
4394                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
4395                         ti,hwmods = "timer12";
4396                         reg = <0x0 0x4>,
4397                               <0x10 0x4>;
4398                         reg-names = "rev", "sysc";
4399                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4400                                          SYSC_OMAP4_SOFTRESET)>;
4401                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4402                                         <SYSC_IDLE_NO>,
4403                                         <SYSC_IDLE_SMART>,
4404                                         <SYSC_IDLE_SMART_WKUP>;
4405                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4406                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
4407                         clock-names = "fck";
4408                         #address-cells = <1>;
4409                         #size-cells = <1>;
4410                         ranges = <0x0 0x0 0x1000>;
4411
4412                         timer12: timer@0 {
4413                                 compatible = "ti,omap5430-timer";
4414                                 reg = <0x0 0x80>;
4415                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
4416                                 ti,timer-alwon;
4417                                 ti,timer-secure;
4418                         };
4419                 };
4420
4421                 target-module@2000 {                    /* 0x4ae22000, ap 21 18.0 */
4422                         compatible = "ti,sysc";
4423                         status = "disabled";
4424                         #address-cells = <1>;
4425                         #size-cells = <1>;
4426                         ranges = <0x0 0x2000 0x1000>;
4427                 };
4428
4429                 target-module@6000 {                    /* 0x4ae26000, ap 13 48.0 */
4430                         compatible = "ti,sysc";
4431                         status = "disabled";
4432                         #address-cells = <1>;
4433                         #size-cells = <1>;
4434                         ranges = <0x00000000 0x00006000 0x00001000>,
4435                                  <0x00001000 0x00007000 0x00000400>,
4436                                  <0x00002000 0x00008000 0x00000800>,
4437                                  <0x00002800 0x00008800 0x00000200>,
4438                                  <0x00002a00 0x00008a00 0x00000100>,
4439                                  <0x00003000 0x00009000 0x00000100>;
4440                 };
4441
4442                 target-module@b000 {                    /* 0x4ae2b000, ap 28 02.0 */
4443                         compatible = "ti,sysc-omap2", "ti,sysc";
4444                         reg = <0xb050 0x4>,
4445                               <0xb054 0x4>,
4446                               <0xb058 0x4>;
4447                         reg-names = "rev", "sysc", "syss";
4448                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4449                                          SYSC_OMAP2_SOFTRESET |
4450                                          SYSC_OMAP2_AUTOIDLE)>;
4451                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4452                                         <SYSC_IDLE_NO>,
4453                                         <SYSC_IDLE_SMART>,
4454                                         <SYSC_IDLE_SMART_WKUP>;
4455                         ti,syss-mask = <1>;
4456                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4457                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
4458                         clock-names = "fck";
4459                         #address-cells = <1>;
4460                         #size-cells = <1>;
4461                         ranges = <0x0 0xb000 0x1000>;
4462
4463                         uart10: serial@0 {
4464                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
4465                                 reg = <0x0 0x100>;
4466                                 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
4467                                 clock-frequency = <48000000>;
4468                                 status = "disabled";
4469                         };
4470                 };
4471
4472                 target-module@f000 {                    /* 0x4ae2f000, ap 32 58.0 */
4473                         compatible = "ti,sysc";
4474                         status = "disabled";
4475                         #address-cells = <1>;
4476                         #size-cells = <1>;
4477                         ranges = <0x0 0xf000 0x1000>;
4478                 };
4479         };
4480
4481         segment@30000 {                                 /* 0x4ae30000 */
4482                 compatible = "simple-bus";
4483                 #address-cells = <1>;
4484                 #size-cells = <1>;
4485                 ranges = <0x0000c000 0x0003c000 0x002000>,      /* ap 30 */
4486                          <0x0000e000 0x0003e000 0x001000>,      /* ap 31 */
4487                          <0x00000000 0x00030000 0x001000>,      /* ap 33 */
4488                          <0x00001000 0x00031000 0x001000>,      /* ap 34 */
4489                          <0x00002000 0x00032000 0x001000>,      /* ap 35 */
4490                          <0x00003000 0x00033000 0x001000>,      /* ap 36 */
4491                          <0x00004000 0x00034000 0x001000>,      /* ap 37 */
4492                          <0x00005000 0x00035000 0x001000>,      /* ap 38 */
4493                          <0x00006000 0x00036000 0x001000>,      /* ap 39 */
4494                          <0x00007000 0x00037000 0x001000>,      /* ap 40 */
4495                          <0x00008000 0x00038000 0x001000>,      /* ap 41 */
4496                          <0x00009000 0x00039000 0x001000>,      /* ap 42 */
4497                          <0x0000a000 0x0003a000 0x001000>;      /* ap 43 */
4498
4499                 target-module@1000 {                    /* 0x4ae31000, ap 34 60.0 */
4500                         compatible = "ti,sysc";
4501                         status = "disabled";
4502                         #address-cells = <1>;
4503                         #size-cells = <1>;
4504                         ranges = <0x0 0x1000 0x1000>;
4505                 };
4506
4507                 target-module@3000 {                    /* 0x4ae33000, ap 36 0a.0 */
4508                         compatible = "ti,sysc";
4509                         status = "disabled";
4510                         #address-cells = <1>;
4511                         #size-cells = <1>;
4512                         ranges = <0x0 0x3000 0x1000>;
4513                 };
4514
4515                 target-module@5000 {                    /* 0x4ae35000, ap 38 0c.0 */
4516                         compatible = "ti,sysc";
4517                         status = "disabled";
4518                         #address-cells = <1>;
4519                         #size-cells = <1>;
4520                         ranges = <0x0 0x5000 0x1000>;
4521                 };
4522
4523                 target-module@7000 {                    /* 0x4ae37000, ap 40 68.0 */
4524                         compatible = "ti,sysc";
4525                         status = "disabled";
4526                         #address-cells = <1>;
4527                         #size-cells = <1>;
4528                         ranges = <0x0 0x7000 0x1000>;
4529                 };
4530
4531                 target-module@9000 {                    /* 0x4ae39000, ap 42 70.0 */
4532                         compatible = "ti,sysc";
4533                         status = "disabled";
4534                         #address-cells = <1>;
4535                         #size-cells = <1>;
4536                         ranges = <0x0 0x9000 0x1000>;
4537                 };
4538
4539                 target-module@c000 {                    /* 0x4ae3c000, ap 30 04.0 */
4540                         compatible = "ti,sysc-omap4", "ti,sysc";
4541                         reg = <0xc020 0x4>;
4542                         reg-names = "rev";
4543                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
4544                         clock-names = "fck";
4545                         #address-cells = <1>;
4546                         #size-cells = <1>;
4547                         ranges = <0x0 0xc000 0x2000>;
4548
4549                         dcan1: can@0 {
4550                                 compatible = "ti,dra7-d_can";
4551                                 reg = <0x0 0x2000>;
4552                                 syscon-raminit = <&scm_conf 0x558 0>;
4553                                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
4554                                 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>;
4555                                 status = "disabled";
4556                         };
4557                 };
4558         };
4559 };
4560