arch/arm/boot/dts/dra7-l4.dtsi

   1 &l4_cfg {                                               /* 0x4a000000 */
   2         compatible = "ti,dra7-l4-cfg", "simple-bus";
   3         reg = <0x4a000000 0x800>,
   4               <0x4a000800 0x800>,
   5               <0x4a001000 0x1000>;
   6         reg-names = "ap", "la", "ia0";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         ranges = <0x00000000 0x4a000000 0x100000>,      /* segment 0 */
  10                  <0x00100000 0x4a100000 0x100000>,      /* segment 1 */
  11                  <0x00200000 0x4a200000 0x100000>;      /* segment 2 */
  12
  13         segment@0 {                                     /* 0x4a000000 */
  14                 compatible = "simple-bus";
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
  18                          <0x00000800 0x00000800 0x000800>,      /* ap 1 */
  19                          <0x00001000 0x00001000 0x001000>,      /* ap 2 */
  20                          <0x00002000 0x00002000 0x002000>,      /* ap 3 */
  21                          <0x00004000 0x00004000 0x001000>,      /* ap 4 */
  22                          <0x00005000 0x00005000 0x001000>,      /* ap 5 */
  23                          <0x00006000 0x00006000 0x001000>,      /* ap 6 */
  24                          <0x00008000 0x00008000 0x002000>,      /* ap 7 */
  25                          <0x0000a000 0x0000a000 0x001000>,      /* ap 8 */
  26                          <0x00056000 0x00056000 0x001000>,      /* ap 9 */
  27                          <0x00057000 0x00057000 0x001000>,      /* ap 10 */
  28                          <0x0005e000 0x0005e000 0x002000>,      /* ap 11 */
  29                          <0x00060000 0x00060000 0x001000>,      /* ap 12 */
  30                          <0x00080000 0x00080000 0x008000>,      /* ap 13 */
  31                          <0x00088000 0x00088000 0x001000>,      /* ap 14 */
  32                          <0x000a0000 0x000a0000 0x008000>,      /* ap 15 */
  33                          <0x000a8000 0x000a8000 0x001000>,      /* ap 16 */
  34                          <0x000d9000 0x000d9000 0x001000>,      /* ap 17 */
  35                          <0x000da000 0x000da000 0x001000>,      /* ap 18 */
  36                          <0x000dd000 0x000dd000 0x001000>,      /* ap 19 */
  37                          <0x000de000 0x000de000 0x001000>,      /* ap 20 */
  38                          <0x000e0000 0x000e0000 0x001000>,      /* ap 21 */
  39                          <0x000e1000 0x000e1000 0x001000>,      /* ap 22 */
  40                          <0x000f4000 0x000f4000 0x001000>,      /* ap 23 */
  41                          <0x000f5000 0x000f5000 0x001000>,      /* ap 24 */
  42                          <0x000f6000 0x000f6000 0x001000>,      /* ap 25 */
  43                          <0x000f7000 0x000f7000 0x001000>,      /* ap 26 */
  44                          <0x00090000 0x00090000 0x008000>,      /* ap 59 */
  45                          <0x00098000 0x00098000 0x001000>;      /* ap 60 */
  46
  47                 target-module@2000 {                    /* 0x4a002000, ap 3 08.0 */
  48                         compatible = "ti,sysc-omap4", "ti,sysc";
  49                         reg = <0x2000 0x4>;
  50                         reg-names = "rev";
  51                         #address-cells = <1>;
  52                         #size-cells = <1>;
  53                         ranges = <0x0 0x2000 0x2000>;
  54
  55                         scm: scm@0 {
  56                                 compatible = "ti,dra7-scm-core", "simple-bus";
  57                                 reg = <0 0x2000>;
  58                                 #address-cells = <1>;
  59                                 #size-cells = <1>;
  60                                 ranges = <0 0 0x2000>;
  61
  62                                 scm_conf: scm_conf@0 {
  63                                         compatible = "syscon", "simple-bus";
  64                                         reg = <0x0 0x1400>;
  65                                         #address-cells = <1>;
  66                                         #size-cells = <1>;
  67                                         ranges = <0 0x0 0x1400>;
  68
  69                                         pbias_regulator: pbias_regulator@e00 {
  70                                                 compatible = "ti,pbias-dra7", "ti,pbias-omap";
  71                                                 reg = <0xe00 0x4>;
  72                                                 syscon = <&scm_conf>;
  73                                                 pbias_mmc_reg: pbias_mmc_omap5 {
  74                                                         regulator-name = "pbias_mmc_omap5";
  75                                                         regulator-min-microvolt = <1800000>;
  76                                                         regulator-max-microvolt = <3300000>;
  77                                                 };
  78                                         };
  79
  80                                         phy_gmii_sel: phy-gmii-sel {
  81                                                 compatible = "ti,dra7xx-phy-gmii-sel";
  82                                                 reg = <0x554 0x4>;
  83                                                 #phy-cells = <1>;
  84                                         };
  85
  86                                         scm_conf_clocks: clocks {
  87                                                 #address-cells = <1>;
  88                                                 #size-cells = <0>;
  89                                         };
  90                                 };
  91
  92                                 dra7_pmx_core: pinmux@1400 {
  93                                         compatible = "ti,dra7-padconf",
  94                                                      "pinctrl-single";
  95                                         reg = <0x1400 0x0468>;
  96                                         #address-cells = <1>;
  97                                         #size-cells = <0>;
  98                                         #pinctrl-cells = <1>;
  99                                         #interrupt-cells = <1>;
 100                                         interrupt-controller;
 101                                         pinctrl-single,register-width = <32>;
 102                                         pinctrl-single,function-mask = <0x3fffffff>;
 103                                 };
 104
 105                                 scm_conf1: scm_conf@1c04 {
 106                                         compatible = "syscon";
 107                                         reg = <0x1c04 0x0020>;
 108                                         #syscon-cells = <2>;
 109                                 };
 110
 111                                 scm_conf_pcie: scm_conf@1c24 {
 112                                         compatible = "syscon";
 113                                         reg = <0x1c24 0x0024>;
 114                                 };
 115
 116                                 sdma_xbar: dma-router@b78 {
 117                                         compatible = "ti,dra7-dma-crossbar";
 118                                         reg = <0xb78 0xfc>;
 119                                         #dma-cells = <1>;
 120                                         dma-requests = <205>;
 121                                         ti,dma-safe-map = <0>;
 122                                         dma-masters = <&sdma>;
 123                                 };
 124
 125                                 edma_xbar: dma-router@c78 {
 126                                         compatible = "ti,dra7-dma-crossbar";
 127                                         reg = <0xc78 0x7c>;
 128                                         #dma-cells = <2>;
 129                                         dma-requests = <204>;
 130                                         ti,dma-safe-map = <0>;
 131                                         dma-masters = <&edma>;
 132                                 };
 133                         };
 134                 };
 135
 136                 target-module@5000 {                    /* 0x4a005000, ap 5 10.0 */
 137                         compatible = "ti,sysc-omap4", "ti,sysc";
 138                         reg = <0x5000 0x4>;
 139                         reg-names = "rev";
 140                         #address-cells = <1>;
 141                         #size-cells = <1>;
 142                         ranges = <0x0 0x5000 0x1000>;
 143
 144                         cm_core_aon: cm_core_aon@0 {
 145                                 compatible = "ti,dra7-cm-core-aon",
 146                                               "simple-bus";
 147                                 #address-cells = <1>;
 148                                 #size-cells = <1>;
 149                                 reg = <0 0x2000>;
 150                                 ranges = <0 0 0x2000>;
 151
 152                                 cm_core_aon_clocks: clocks {
 153                                         #address-cells = <1>;
 154                                         #size-cells = <0>;
 155                                 };
 156
 157                                 cm_core_aon_clockdomains: clockdomains {
 158                                 };
 159                         };
 160                 };
 161
 162                 target-module@8000 {                    /* 0x4a008000, ap 7 0e.0 */
 163                         compatible = "ti,sysc-omap4", "ti,sysc";
 164                         reg = <0x8000 0x4>;
 165                         reg-names = "rev";
 166                         #address-cells = <1>;
 167                         #size-cells = <1>;
 168                         ranges = <0x0 0x8000 0x2000>;
 169
 170                         cm_core: cm_core@0 {
 171                                 compatible = "ti,dra7-cm-core", "simple-bus";
 172                                 #address-cells = <1>;
 173                                 #size-cells = <1>;
 174                                 reg = <0 0x3000>;
 175                                 ranges = <0 0 0x3000>;
 176
 177                                 cm_core_clocks: clocks {
 178                                         #address-cells = <1>;
 179                                         #size-cells = <0>;
 180                                 };
 181
 182                                 cm_core_clockdomains: clockdomains {
 183                                 };
 184                         };
 185                 };
 186
 187                 target-module@56000 {                   /* 0x4a056000, ap 9 02.0 */
 188                         compatible = "ti,sysc-omap2", "ti,sysc";
 189                         ti,hwmods = "dma_system";
 190                         reg = <0x56000 0x4>,
 191                               <0x5602c 0x4>,
 192                               <0x56028 0x4>;
 193                         reg-names = "rev", "sysc", "syss";
 194                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
 195                                          SYSC_OMAP2_EMUFREE |
 196                                          SYSC_OMAP2_SOFTRESET |
 197                                          SYSC_OMAP2_AUTOIDLE)>;
 198                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
 199                                         <SYSC_IDLE_NO>,
 200                                         <SYSC_IDLE_SMART>,
 201                                         <SYSC_IDLE_SMART_WKUP>;
 202                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 203                                         <SYSC_IDLE_NO>,
 204                                         <SYSC_IDLE_SMART>,
 205                                         <SYSC_IDLE_SMART_WKUP>;
 206                         ti,syss-mask = <1>;
 207                         /* Domains (P, C): core_pwrdm, dma_clkdm */
 208                         clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
 209                         clock-names = "fck";
 210                         #address-cells = <1>;
 211                         #size-cells = <1>;
 212                         ranges = <0x0 0x56000 0x1000>;
 213
 214                         sdma: dma-controller@0 {
 215                                 compatible = "ti,omap4430-sdma";
 216                                 reg = <0x0 0x1000>;
 217                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 218                                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 219                                              <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 220                                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 221                                 #dma-cells = <1>;
 222                                 dma-channels = <32>;
 223                                 dma-requests = <127>;
 224                         };
 225                 };
 226
 227                 target-module@5e000 {                   /* 0x4a05e000, ap 11 1a.0 */
 228                         compatible = "ti,sysc";
 229                         status = "disabled";
 230                         #address-cells = <1>;
 231                         #size-cells = <1>;
 232                         ranges = <0x0 0x5e000 0x2000>;
 233                 };
 234
 235                 target-module@80000 {                   /* 0x4a080000, ap 13 20.0 */
 236                         compatible = "ti,sysc-omap2", "ti,sysc";
 237                         ti,hwmods = "ocp2scp1";
 238                         reg = <0x80000 0x4>,
 239                               <0x80010 0x4>,
 240                               <0x80014 0x4>;
 241                         reg-names = "rev", "sysc", "syss";
 242                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 243                                          SYSC_OMAP2_AUTOIDLE)>;
 244                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 245                                         <SYSC_IDLE_NO>,
 246                                         <SYSC_IDLE_SMART>;
 247                         ti,syss-mask = <1>;
 248                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
 249                         clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
 250                         clock-names = "fck";
 251                         #address-cells = <1>;
 252                         #size-cells = <1>;
 253                         ranges = <0x0 0x80000 0x8000>;
 254
 255                         ocp2scp@0 {
 256                                 compatible = "ti,omap-ocp2scp";
 257                                 #address-cells = <1>;
 258                                 #size-cells = <1>;
 259                                 ranges = <0 0 0x8000>;
 260                                 reg = <0x0 0x20>;
 261
 262                                 usb2_phy1: phy@4000 {
 263                                         compatible = "ti,dra7x-usb2", "ti,omap-usb2";
 264                                         reg = <0x4000 0x400>;
 265                                         syscon-phy-power = <&scm_conf 0x300>;
 266                                         clocks = <&usb_phy1_always_on_clk32k>,
 267                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
 268                                         clock-names =   "wkupclk",
 269                                                         "refclk";
 270                                         #phy-cells = <0>;
 271                                 };
 272
 273                                 usb2_phy2: phy@5000 {
 274                                         compatible = "ti,dra7x-usb2-phy2",
 275                                                      "ti,omap-usb2";
 276                                         reg = <0x5000 0x400>;
 277                                         syscon-phy-power = <&scm_conf 0xe74>;
 278                                         clocks = <&usb_phy2_always_on_clk32k>,
 279                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
 280                                         clock-names =   "wkupclk",
 281                                                         "refclk";
 282                                         #phy-cells = <0>;
 283                                 };
 284
 285                                 usb3_phy1: phy@4400 {
 286                                         compatible = "ti,omap-usb3";
 287                                         reg = <0x4400 0x80>,
 288                                               <0x4800 0x64>,
 289                                               <0x4c00 0x40>;
 290                                         reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 291                                         syscon-phy-power = <&scm_conf 0x370>;
 292                                         clocks = <&usb_phy3_always_on_clk32k>,
 293                                                  <&sys_clkin1>,
 294                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
 295                                         clock-names =   "wkupclk",
 296                                                         "sysclk",
 297                                                         "refclk";
 298                                         #phy-cells = <0>;
 299                                 };
 300                         };
 301                 };
 302
 303                 target-module@90000 {                   /* 0x4a090000, ap 59 42.0 */
 304                         compatible = "ti,sysc-omap2", "ti,sysc";
 305                         ti,hwmods = "ocp2scp3";
 306                         reg = <0x90000 0x4>,
 307                               <0x90010 0x4>,
 308                               <0x90014 0x4>;
 309                         reg-names = "rev", "sysc", "syss";
 310                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
 311                                          SYSC_OMAP2_AUTOIDLE)>;
 312                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 313                                         <SYSC_IDLE_NO>,
 314                                         <SYSC_IDLE_SMART>;
 315                         ti,syss-mask = <1>;
 316                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
 317                         clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
 318                         clock-names = "fck";
 319                         #address-cells = <1>;
 320                         #size-cells = <1>;
 321                         ranges = <0x0 0x90000 0x8000>;
 322
 323                         ocp2scp@0 {
 324                                 compatible = "ti,omap-ocp2scp";
 325                                 #address-cells = <1>;
 326                                 #size-cells = <1>;
 327                                 ranges = <0 0 0x8000>;
 328                                 reg = <0x0 0x20>;
 329
 330                                 pcie1_phy: pciephy@4000 {
 331                                         compatible = "ti,phy-pipe3-pcie";
 332                                         reg = <0x4000 0x80>, /* phy_rx */
 333                                               <0x4400 0x64>; /* phy_tx */
 334                                         reg-names = "phy_rx", "phy_tx";
 335                                         syscon-phy-power = <&scm_conf_pcie 0x1c>;
 336                                         syscon-pcs = <&scm_conf_pcie 0x10>;
 337                                         clocks = <&dpll_pcie_ref_ck>,
 338                                                  <&dpll_pcie_ref_m2ldo_ck>,
 339                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
 340                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
 341                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
 342                                                  <&optfclk_pciephy_div>,
 343                                                  <&sys_clkin1>;
 344                                         clock-names = "dpll_ref", "dpll_ref_m2",
 345                                                       "wkupclk", "refclk",
 346                                                       "div-clk", "phy-div", "sysclk";
 347                                         #phy-cells = <0>;
 348                                 };
 349
 350                                 pcie2_phy: pciephy@5000 {
 351                                         compatible = "ti,phy-pipe3-pcie";
 352                                         reg = <0x5000 0x80>, /* phy_rx */
 353                                               <0x5400 0x64>; /* phy_tx */
 354                                         reg-names = "phy_rx", "phy_tx";
 355                                         syscon-phy-power = <&scm_conf_pcie 0x20>;
 356                                         syscon-pcs = <&scm_conf_pcie 0x10>;
 357                                         clocks = <&dpll_pcie_ref_ck>,
 358                                                  <&dpll_pcie_ref_m2ldo_ck>,
 359                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
 360                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
 361                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
 362                                                  <&optfclk_pciephy_div>,
 363                                                  <&sys_clkin1>;
 364                                         clock-names = "dpll_ref", "dpll_ref_m2",
 365                                                       "wkupclk", "refclk",
 366                                                       "div-clk", "phy-div", "sysclk";
 367                                         #phy-cells = <0>;
 368                                         status = "disabled";
 369                                 };
 370
 371                                 sata_phy: phy@6000 {
 372                                         compatible = "ti,phy-pipe3-sata";
 373                                         reg = <0x6000 0x80>, /* phy_rx */
 374                                               <0x6400 0x64>, /* phy_tx */
 375                                               <0x6800 0x40>; /* pll_ctrl */
 376                                         reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 377                                         syscon-phy-power = <&scm_conf 0x374>;
 378                                         clocks = <&sys_clkin1>,
 379                                                  <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
 380                                         clock-names = "sysclk", "refclk";
 381                                         syscon-pllreset = <&scm_conf 0x3fc>;
 382                                         #phy-cells = <0>;
 383                                 };
 384                         };
 385                 };
 386
 387                 target-module@a0000 {                   /* 0x4a0a0000, ap 15 40.0 */
 388                         compatible = "ti,sysc";
 389                         status = "disabled";
 390                         #address-cells = <1>;
 391                         #size-cells = <1>;
 392                         ranges = <0x0 0xa0000 0x8000>;
 393                 };
 394
 395                 target-module@d9000 {                   /* 0x4a0d9000, ap 17 72.0 */
 396                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
 397                         ti,hwmods = "smartreflex_mpu";
 398                         reg = <0xd9038 0x4>;
 399                         reg-names = "sysc";
 400                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 401                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 402                                         <SYSC_IDLE_NO>,
 403                                         <SYSC_IDLE_SMART>,
 404                                         <SYSC_IDLE_SMART_WKUP>;
 405                         /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
 406                         clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
 407                         clock-names = "fck";
 408                         #address-cells = <1>;
 409                         #size-cells = <1>;
 410                         ranges = <0x0 0xd9000 0x1000>;
 411
 412                         /* SmartReflex child device marked reserved in TRM */
 413                 };
 414
 415                 target-module@dd000 {                   /* 0x4a0dd000, ap 19 18.0 */
 416                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
 417                         ti,hwmods = "smartreflex_core";
 418                         reg = <0xdd038 0x4>;
 419                         reg-names = "sysc";
 420                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
 421                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 422                                         <SYSC_IDLE_NO>,
 423                                         <SYSC_IDLE_SMART>,
 424                                         <SYSC_IDLE_SMART_WKUP>;
 425                         /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
 426                         clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
 427                         clock-names = "fck";
 428                         #address-cells = <1>;
 429                         #size-cells = <1>;
 430                         ranges = <0x0 0xdd000 0x1000>;
 431
 432                         /* SmartReflex child device marked reserved in TRM */
 433                 };
 434
 435                 target-module@e0000 {                   /* 0x4a0e0000, ap 21 28.0 */
 436                         compatible = "ti,sysc";
 437                         status = "disabled";
 438                         #address-cells = <1>;
 439                         #size-cells = <1>;
 440                         ranges = <0x0 0xe0000 0x1000>;
 441                 };
 442
 443                 target-module@f4000 {                   /* 0x4a0f4000, ap 23 04.0 */
 444                         compatible = "ti,sysc-omap4", "ti,sysc";
 445                         reg = <0xf4000 0x4>,
 446                               <0xf4010 0x4>;
 447                         reg-names = "rev", "sysc";
 448                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
 449                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 450                                         <SYSC_IDLE_NO>,
 451                                         <SYSC_IDLE_SMART>;
 452                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 453                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
 454                         clock-names = "fck";
 455                         #address-cells = <1>;
 456                         #size-cells = <1>;
 457                         ranges = <0x0 0xf4000 0x1000>;
 458
 459                         mailbox1: mailbox@0 {
 460                                 compatible = "ti,omap4-mailbox";
 461                                 reg = <0x0 0x200>;
 462                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 463                                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 464                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 465                                 #mbox-cells = <1>;
 466                                 ti,mbox-num-users = <3>;
 467                                 ti,mbox-num-fifos = <8>;
 468                                 status = "disabled";
 469                         };
 470                 };
 471
 472                 target-module@f6000 {                   /* 0x4a0f6000, ap 25 78.0 */
 473                         compatible = "ti,sysc-omap2", "ti,sysc";
 474                         ti,hwmods = "spinlock";
 475                         reg = <0xf6000 0x4>,
 476                               <0xf6010 0x4>,
 477                               <0xf6014 0x4>;
 478                         reg-names = "rev", "sysc", "syss";
 479                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
 480                                          SYSC_OMAP2_SOFTRESET |
 481                                          SYSC_OMAP2_AUTOIDLE)>;
 482                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
 483                                         <SYSC_IDLE_NO>,
 484                                         <SYSC_IDLE_SMART>;
 485                         ti,syss-mask = <1>;
 486                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
 487                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
 488                         clock-names = "fck";
 489                         #address-cells = <1>;
 490                         #size-cells = <1>;
 491                         ranges = <0x0 0xf6000 0x1000>;
 492
 493                         hwspinlock: spinlock@0 {
 494                                 compatible = "ti,omap4-hwspinlock";
 495                                 reg = <0x0 0x1000>;
 496                                 #hwlock-cells = <1>;
 497                         };
 498                 };
 499         };
 500
 501         segment@100000 {                                        /* 0x4a100000 */
 502                 compatible = "simple-bus";
 503                 #address-cells = <1>;
 504                 #size-cells = <1>;
 505                 ranges = <0x00002000 0x00102000 0x001000>,      /* ap 27 */
 506                          <0x00003000 0x00103000 0x001000>,      /* ap 28 */
 507                          <0x00008000 0x00108000 0x001000>,      /* ap 29 */
 508                          <0x00009000 0x00109000 0x001000>,      /* ap 30 */
 509                          <0x00040000 0x00140000 0x010000>,      /* ap 31 */
 510                          <0x00050000 0x00150000 0x001000>,      /* ap 32 */
 511                          <0x00051000 0x00151000 0x001000>,      /* ap 33 */
 512                          <0x00052000 0x00152000 0x001000>,      /* ap 34 */
 513                          <0x00053000 0x00153000 0x001000>,      /* ap 35 */
 514                          <0x00054000 0x00154000 0x001000>,      /* ap 36 */
 515                          <0x00055000 0x00155000 0x001000>,      /* ap 37 */
 516                          <0x00056000 0x00156000 0x001000>,      /* ap 38 */
 517                          <0x00057000 0x00157000 0x001000>,      /* ap 39 */
 518                          <0x00058000 0x00158000 0x001000>,      /* ap 40 */
 519                          <0x0005b000 0x0015b000 0x001000>,      /* ap 41 */
 520                          <0x0005c000 0x0015c000 0x001000>,      /* ap 42 */
 521                          <0x0005d000 0x0015d000 0x001000>,      /* ap 45 */
 522                          <0x0005e000 0x0015e000 0x001000>,      /* ap 46 */
 523                          <0x0005f000 0x0015f000 0x001000>,      /* ap 47 */
 524                          <0x00060000 0x00160000 0x001000>,      /* ap 48 */
 525                          <0x00061000 0x00161000 0x001000>,      /* ap 49 */
 526                          <0x00062000 0x00162000 0x001000>,      /* ap 50 */
 527                          <0x00063000 0x00163000 0x001000>,      /* ap 51 */
 528                          <0x00064000 0x00164000 0x001000>,      /* ap 52 */
 529                          <0x00065000 0x00165000 0x001000>,      /* ap 53 */
 530                          <0x00066000 0x00166000 0x001000>,      /* ap 54 */
 531                          <0x00067000 0x00167000 0x001000>,      /* ap 55 */
 532                          <0x00068000 0x00168000 0x001000>,      /* ap 56 */
 533                          <0x0006d000 0x0016d000 0x001000>,      /* ap 57 */
 534                          <0x0006e000 0x0016e000 0x001000>,      /* ap 58 */
 535                          <0x00071000 0x00171000 0x001000>,      /* ap 61 */
 536                          <0x00072000 0x00172000 0x001000>,      /* ap 62 */
 537                          <0x00073000 0x00173000 0x001000>,      /* ap 63 */
 538                          <0x00074000 0x00174000 0x001000>,      /* ap 64 */
 539                          <0x00075000 0x00175000 0x001000>,      /* ap 65 */
 540                          <0x00076000 0x00176000 0x001000>,      /* ap 66 */
 541                          <0x00077000 0x00177000 0x001000>,      /* ap 67 */
 542                          <0x00078000 0x00178000 0x001000>,      /* ap 68 */
 543                          <0x00081000 0x00181000 0x001000>,      /* ap 69 */
 544                          <0x00082000 0x00182000 0x001000>,      /* ap 70 */
 545                          <0x00083000 0x00183000 0x001000>,      /* ap 71 */
 546                          <0x00084000 0x00184000 0x001000>,      /* ap 72 */
 547                          <0x00085000 0x00185000 0x001000>,      /* ap 73 */
 548                          <0x00086000 0x00186000 0x001000>,      /* ap 74 */
 549                          <0x00087000 0x00187000 0x001000>,      /* ap 75 */
 550                          <0x00088000 0x00188000 0x001000>,      /* ap 76 */
 551                          <0x00069000 0x00169000 0x001000>,      /* ap 103 */
 552                          <0x0006a000 0x0016a000 0x001000>,      /* ap 104 */
 553                          <0x00079000 0x00179000 0x001000>,      /* ap 105 */
 554                          <0x0007a000 0x0017a000 0x001000>,      /* ap 106 */
 555                          <0x0006b000 0x0016b000 0x001000>,      /* ap 107 */
 556                          <0x0006c000 0x0016c000 0x001000>,      /* ap 108 */
 557                          <0x0007b000 0x0017b000 0x001000>,      /* ap 121 */
 558                          <0x0007c000 0x0017c000 0x001000>,      /* ap 122 */
 559                          <0x0007d000 0x0017d000 0x001000>,      /* ap 123 */
 560                          <0x0007e000 0x0017e000 0x001000>,      /* ap 124 */
 561                          <0x00059000 0x00159000 0x001000>,      /* ap 125 */
 562                          <0x0005a000 0x0015a000 0x001000>;      /* ap 126 */
 563
 564                 target-module@2000 {                    /* 0x4a102000, ap 27 3c.0 */
 565                         compatible = "ti,sysc";
 566                         status = "disabled";
 567                         #address-cells = <1>;
 568                         #size-cells = <1>;
 569                         ranges = <0x0 0x2000 0x1000>;
 570                 };
 571
 572                 target-module@8000 {                    /* 0x4a108000, ap 29 1e.0 */
 573                         compatible = "ti,sysc";
 574                         status = "disabled";
 575                         #address-cells = <1>;
 576                         #size-cells = <1>;
 577                         ranges = <0x0 0x8000 0x1000>;
 578                 };
 579
 580                 target-module@40000 {                   /* 0x4a140000, ap 31 06.0 */
 581                         compatible = "ti,sysc";
 582                         status = "disabled";
 583                         #address-cells = <1>;
 584                         #size-cells = <1>;
 585                         ranges = <0x0 0x40000 0x10000>;
 586                 };
 587
 588                 target-module@51000 {                   /* 0x4a151000, ap 33 50.0 */
 589                         compatible = "ti,sysc";
 590                         status = "disabled";
 591                         #address-cells = <1>;
 592                         #size-cells = <1>;
 593                         ranges = <0x0 0x51000 0x1000>;
 594                 };
 595
 596                 target-module@53000 {                   /* 0x4a153000, ap 35 54.0 */
 597                         compatible = "ti,sysc";
 598                         status = "disabled";
 599                         #address-cells = <1>;
 600                         #size-cells = <1>;
 601                         ranges = <0x0 0x53000 0x1000>;
 602                 };
 603
 604                 target-module@55000 {                   /* 0x4a155000, ap 37 46.0 */
 605                         compatible = "ti,sysc";
 606                         status = "disabled";
 607                         #address-cells = <1>;
 608                         #size-cells = <1>;
 609                         ranges = <0x0 0x55000 0x1000>;
 610                 };
 611
 612                 target-module@57000 {                   /* 0x4a157000, ap 39 58.0 */
 613                         compatible = "ti,sysc";
 614                         status = "disabled";
 615                         #address-cells = <1>;
 616                         #size-cells = <1>;
 617                         ranges = <0x0 0x57000 0x1000>;
 618                 };
 619
 620                 target-module@59000 {                   /* 0x4a159000, ap 125 6a.0 */
 621                         compatible = "ti,sysc";
 622                         status = "disabled";
 623                         #address-cells = <1>;
 624                         #size-cells = <1>;
 625                         ranges = <0x0 0x59000 0x1000>;
 626                 };
 627
 628                 target-module@5b000 {                   /* 0x4a15b000, ap 41 60.0 */
 629                         compatible = "ti,sysc";
 630                         status = "disabled";
 631                         #address-cells = <1>;
 632                         #size-cells = <1>;
 633                         ranges = <0x0 0x5b000 0x1000>;
 634                 };
 635
 636                 target-module@5d000 {                   /* 0x4a15d000, ap 45 3a.0 */
 637                         compatible = "ti,sysc";
 638                         status = "disabled";
 639                         #address-cells = <1>;
 640                         #size-cells = <1>;
 641                         ranges = <0x0 0x5d000 0x1000>;
 642                 };
 643
 644                 target-module@5f000 {                   /* 0x4a15f000, ap 47 56.0 */
 645                         compatible = "ti,sysc";
 646                         status = "disabled";
 647                         #address-cells = <1>;
 648                         #size-cells = <1>;
 649                         ranges = <0x0 0x5f000 0x1000>;
 650                 };
 651
 652                 target-module@61000 {                   /* 0x4a161000, ap 49 32.0 */
 653                         compatible = "ti,sysc";
 654                         status = "disabled";
 655                         #address-cells = <1>;
 656                         #size-cells = <1>;
 657                         ranges = <0x0 0x61000 0x1000>;
 658                 };
 659
 660                 target-module@63000 {                   /* 0x4a163000, ap 51 5c.0 */
 661                         compatible = "ti,sysc";
 662                         status = "disabled";
 663                         #address-cells = <1>;
 664                         #size-cells = <1>;
 665                         ranges = <0x0 0x63000 0x1000>;
 666                 };
 667
 668                 target-module@65000 {                   /* 0x4a165000, ap 53 4e.0 */
 669                         compatible = "ti,sysc";
 670                         status = "disabled";
 671                         #address-cells = <1>;
 672                         #size-cells = <1>;
 673                         ranges = <0x0 0x65000 0x1000>;
 674                 };
 675
 676                 target-module@67000 {                   /* 0x4a167000, ap 55 5e.0 */
 677                         compatible = "ti,sysc";
 678                         status = "disabled";
 679                         #address-cells = <1>;
 680                         #size-cells = <1>;
 681                         ranges = <0x0 0x67000 0x1000>;
 682                 };
 683
 684                 target-module@69000 {                   /* 0x4a169000, ap 103 4a.0 */
 685                         compatible = "ti,sysc";
 686                         status = "disabled";
 687                         #address-cells = <1>;
 688                         #size-cells = <1>;
 689                         ranges = <0x0 0x69000 0x1000>;
 690                 };
 691
 692                 target-module@6b000 {                   /* 0x4a16b000, ap 107 52.0 */
 693                         compatible = "ti,sysc";
 694                         status = "disabled";
 695                         #address-cells = <1>;
 696                         #size-cells = <1>;
 697                         ranges = <0x0 0x6b000 0x1000>;
 698                 };
 699
 700                 target-module@6d000 {                   /* 0x4a16d000, ap 57 68.0 */
 701                         compatible = "ti,sysc";
 702                         status = "disabled";
 703                         #address-cells = <1>;
 704                         #size-cells = <1>;
 705                         ranges = <0x0 0x6d000 0x1000>;
 706                 };
 707
 708                 target-module@71000 {                   /* 0x4a171000, ap 61 48.0 */
 709                         compatible = "ti,sysc";
 710                         status = "disabled";
 711                         #address-cells = <1>;
 712                         #size-cells = <1>;
 713                         ranges = <0x0 0x71000 0x1000>;
 714                 };
 715
 716                 target-module@73000 {                   /* 0x4a173000, ap 63 2a.0 */
 717                         compatible = "ti,sysc";
 718                         status = "disabled";
 719                         #address-cells = <1>;
 720                         #size-cells = <1>;
 721                         ranges = <0x0 0x73000 0x1000>;
 722                 };
 723
 724                 target-module@75000 {                   /* 0x4a175000, ap 65 64.0 */
 725                         compatible = "ti,sysc";
 726                         status = "disabled";
 727                         #address-cells = <1>;
 728                         #size-cells = <1>;
 729                         ranges = <0x0 0x75000 0x1000>;
 730                 };
 731
 732                 target-module@77000 {                   /* 0x4a177000, ap 67 66.0 */
 733                         compatible = "ti,sysc";
 734                         status = "disabled";
 735                         #address-cells = <1>;
 736                         #size-cells = <1>;
 737                         ranges = <0x0 0x77000 0x1000>;
 738                 };
 739
 740                 target-module@79000 {                   /* 0x4a179000, ap 105 34.0 */
 741                         compatible = "ti,sysc";
 742                         status = "disabled";
 743                         #address-cells = <1>;
 744                         #size-cells = <1>;
 745                         ranges = <0x0 0x79000 0x1000>;
 746                 };
 747
 748                 target-module@7b000 {                   /* 0x4a17b000, ap 121 7c.0 */
 749                         compatible = "ti,sysc";
 750                         status = "disabled";
 751                         #address-cells = <1>;
 752                         #size-cells = <1>;
 753                         ranges = <0x0 0x7b000 0x1000>;
 754                 };
 755
 756                 target-module@7d000 {                   /* 0x4a17d000, ap 123 7e.0 */
 757                         compatible = "ti,sysc";
 758                         status = "disabled";
 759                         #address-cells = <1>;
 760                         #size-cells = <1>;
 761                         ranges = <0x0 0x7d000 0x1000>;
 762                 };
 763
 764                 target-module@81000 {                   /* 0x4a181000, ap 69 26.0 */
 765                         compatible = "ti,sysc";
 766                         status = "disabled";
 767                         #address-cells = <1>;
 768                         #size-cells = <1>;
 769                         ranges = <0x0 0x81000 0x1000>;
 770                 };
 771
 772                 target-module@83000 {                   /* 0x4a183000, ap 71 2e.0 */
 773                         compatible = "ti,sysc";
 774                         status = "disabled";
 775                         #address-cells = <1>;
 776                         #size-cells = <1>;
 777                         ranges = <0x0 0x83000 0x1000>;
 778                 };
 779
 780                 target-module@85000 {                   /* 0x4a185000, ap 73 36.0 */
 781                         compatible = "ti,sysc";
 782                         status = "disabled";
 783                         #address-cells = <1>;
 784                         #size-cells = <1>;
 785                         ranges = <0x0 0x85000 0x1000>;
 786                 };
 787
 788                 target-module@87000 {                   /* 0x4a187000, ap 75 74.0 */
 789                         compatible = "ti,sysc";
 790                         status = "disabled";
 791                         #address-cells = <1>;
 792                         #size-cells = <1>;
 793                         ranges = <0x0 0x87000 0x1000>;
 794                 };
 795         };
 796
 797         segment@200000 {                                        /* 0x4a200000 */
 798                 compatible = "simple-bus";
 799                 #address-cells = <1>;
 800                 #size-cells = <1>;
 801                 ranges = <0x00018000 0x00218000 0x001000>,      /* ap 43 */
 802                          <0x00019000 0x00219000 0x001000>,      /* ap 44 */
 803                          <0x00000000 0x00200000 0x001000>,      /* ap 77 */
 804                          <0x00001000 0x00201000 0x001000>,      /* ap 78 */
 805                          <0x0000a000 0x0020a000 0x001000>,      /* ap 79 */
 806                          <0x0000b000 0x0020b000 0x001000>,      /* ap 80 */
 807                          <0x0000c000 0x0020c000 0x001000>,      /* ap 81 */
 808                          <0x0000d000 0x0020d000 0x001000>,      /* ap 82 */
 809                          <0x0000e000 0x0020e000 0x001000>,      /* ap 83 */
 810                          <0x0000f000 0x0020f000 0x001000>,      /* ap 84 */
 811                          <0x00010000 0x00210000 0x001000>,      /* ap 85 */
 812                          <0x00011000 0x00211000 0x001000>,      /* ap 86 */
 813                          <0x00012000 0x00212000 0x001000>,      /* ap 87 */
 814                          <0x00013000 0x00213000 0x001000>,      /* ap 88 */
 815                          <0x00014000 0x00214000 0x001000>,      /* ap 89 */
 816                          <0x00015000 0x00215000 0x001000>,      /* ap 90 */
 817                          <0x0002a000 0x0022a000 0x001000>,      /* ap 91 */
 818                          <0x0002b000 0x0022b000 0x001000>,      /* ap 92 */
 819                          <0x0001c000 0x0021c000 0x001000>,      /* ap 93 */
 820                          <0x0001d000 0x0021d000 0x001000>,      /* ap 94 */
 821                          <0x0001e000 0x0021e000 0x001000>,      /* ap 95 */
 822                          <0x0001f000 0x0021f000 0x001000>,      /* ap 96 */
 823                          <0x00020000 0x00220000 0x001000>,      /* ap 97 */
 824                          <0x00021000 0x00221000 0x001000>,      /* ap 98 */
 825                          <0x00024000 0x00224000 0x001000>,      /* ap 99 */
 826                          <0x00025000 0x00225000 0x001000>,      /* ap 100 */
 827                          <0x00026000 0x00226000 0x001000>,      /* ap 101 */
 828                          <0x00027000 0x00227000 0x001000>,      /* ap 102 */
 829                          <0x0002c000 0x0022c000 0x001000>,      /* ap 109 */
 830                          <0x0002d000 0x0022d000 0x001000>,      /* ap 110 */
 831                          <0x0002e000 0x0022e000 0x001000>,      /* ap 111 */
 832                          <0x0002f000 0x0022f000 0x001000>,      /* ap 112 */
 833                          <0x00030000 0x00230000 0x001000>,      /* ap 113 */
 834                          <0x00031000 0x00231000 0x001000>,      /* ap 114 */
 835                          <0x00032000 0x00232000 0x001000>,      /* ap 115 */
 836                          <0x00033000 0x00233000 0x001000>,      /* ap 116 */
 837                          <0x00034000 0x00234000 0x001000>,      /* ap 117 */
 838                          <0x00035000 0x00235000 0x001000>,      /* ap 118 */
 839                          <0x00036000 0x00236000 0x001000>,      /* ap 119 */
 840                          <0x00037000 0x00237000 0x001000>,      /* ap 120 */
 841                          <0x0001a000 0x0021a000 0x001000>,      /* ap 127 */
 842                          <0x0001b000 0x0021b000 0x001000>;      /* ap 128 */
 843
 844                 target-module@0 {                       /* 0x4a200000, ap 77 3e.0 */
 845                         compatible = "ti,sysc";
 846                         status = "disabled";
 847                         #address-cells = <1>;
 848                         #size-cells = <1>;
 849                         ranges = <0x0 0x0 0x1000>;
 850                 };
 851
 852                 target-module@a000 {                    /* 0x4a20a000, ap 79 30.0 */
 853                         compatible = "ti,sysc";
 854                         status = "disabled";
 855                         #address-cells = <1>;
 856                         #size-cells = <1>;
 857                         ranges = <0x0 0xa000 0x1000>;
 858                 };
 859
 860                 target-module@c000 {                    /* 0x4a20c000, ap 81 0c.0 */
 861                         compatible = "ti,sysc";
 862                         status = "disabled";
 863                         #address-cells = <1>;
 864                         #size-cells = <1>;
 865                         ranges = <0x0 0xc000 0x1000>;
 866                 };
 867
 868                 target-module@e000 {                    /* 0x4a20e000, ap 83 22.0 */
 869                         compatible = "ti,sysc";
 870                         status = "disabled";
 871                         #address-cells = <1>;
 872                         #size-cells = <1>;
 873                         ranges = <0x0 0xe000 0x1000>;
 874                 };
 875
 876                 target-module@10000 {                   /* 0x4a210000, ap 85 14.0 */
 877                         compatible = "ti,sysc";
 878                         status = "disabled";
 879                         #address-cells = <1>;
 880                         #size-cells = <1>;
 881                         ranges = <0x0 0x10000 0x1000>;
 882                 };
 883
 884                 target-module@12000 {                   /* 0x4a212000, ap 87 16.0 */
 885                         compatible = "ti,sysc";
 886                         status = "disabled";
 887                         #address-cells = <1>;
 888                         #size-cells = <1>;
 889                         ranges = <0x0 0x12000 0x1000>;
 890                 };
 891
 892                 target-module@14000 {                   /* 0x4a214000, ap 89 1c.0 */
 893                         compatible = "ti,sysc";
 894                         status = "disabled";
 895                         #address-cells = <1>;
 896                         #size-cells = <1>;
 897                         ranges = <0x0 0x14000 0x1000>;
 898                 };
 899
 900                 target-module@18000 {                   /* 0x4a218000, ap 43 12.0 */
 901                         compatible = "ti,sysc";
 902                         status = "disabled";
 903                         #address-cells = <1>;
 904                         #size-cells = <1>;
 905                         ranges = <0x0 0x18000 0x1000>;
 906                 };
 907
 908                 target-module@1a000 {                   /* 0x4a21a000, ap 127 7a.0 */
 909                         compatible = "ti,sysc";
 910                         status = "disabled";
 911                         #address-cells = <1>;
 912                         #size-cells = <1>;
 913                         ranges = <0x0 0x1a000 0x1000>;
 914                 };
 915
 916                 target-module@1c000 {                   /* 0x4a21c000, ap 93 38.0 */
 917                         compatible = "ti,sysc";
 918                         status = "disabled";
 919                         #address-cells = <1>;
 920                         #size-cells = <1>;
 921                         ranges = <0x0 0x1c000 0x1000>;
 922                 };
 923
 924                 target-module@1e000 {                   /* 0x4a21e000, ap 95 0a.0 */
 925                         compatible = "ti,sysc";
 926                         status = "disabled";
 927                         #address-cells = <1>;
 928                         #size-cells = <1>;
 929                         ranges = <0x0 0x1e000 0x1000>;
 930                 };
 931
 932                 target-module@20000 {                   /* 0x4a220000, ap 97 24.0 */
 933                         compatible = "ti,sysc";
 934                         status = "disabled";
 935                         #address-cells = <1>;
 936                         #size-cells = <1>;
 937                         ranges = <0x0 0x20000 0x1000>;
 938                 };
 939
 940                 target-module@24000 {                   /* 0x4a224000, ap 99 44.0 */
 941                         compatible = "ti,sysc";
 942                         status = "disabled";
 943                         #address-cells = <1>;
 944                         #size-cells = <1>;
 945                         ranges = <0x0 0x24000 0x1000>;
 946                 };
 947
 948                 target-module@26000 {                   /* 0x4a226000, ap 101 2c.0 */
 949                         compatible = "ti,sysc";
 950                         status = "disabled";
 951                         #address-cells = <1>;
 952                         #size-cells = <1>;
 953                         ranges = <0x0 0x26000 0x1000>;
 954                 };
 955
 956                 target-module@2a000 {                   /* 0x4a22a000, ap 91 4c.0 */
 957                         compatible = "ti,sysc";
 958                         status = "disabled";
 959                         #address-cells = <1>;
 960                         #size-cells = <1>;
 961                         ranges = <0x0 0x2a000 0x1000>;
 962                 };
 963
 964                 target-module@2c000 {                   /* 0x4a22c000, ap 109 6c.0 */
 965                         compatible = "ti,sysc";
 966                         status = "disabled";
 967                         #address-cells = <1>;
 968                         #size-cells = <1>;
 969                         ranges = <0x0 0x2c000 0x1000>;
 970                 };
 971
 972                 target-module@2e000 {                   /* 0x4a22e000, ap 111 6e.0 */
 973                         compatible = "ti,sysc";
 974                         status = "disabled";
 975                         #address-cells = <1>;
 976                         #size-cells = <1>;
 977                         ranges = <0x0 0x2e000 0x1000>;
 978                 };
 979
 980                 target-module@30000 {                   /* 0x4a230000, ap 113 70.0 */
 981                         compatible = "ti,sysc";
 982                         status = "disabled";
 983                         #address-cells = <1>;
 984                         #size-cells = <1>;
 985                         ranges = <0x0 0x30000 0x1000>;
 986                 };
 987
 988                 target-module@32000 {                   /* 0x4a232000, ap 115 5a.0 */
 989                         compatible = "ti,sysc";
 990                         status = "disabled";
 991                         #address-cells = <1>;
 992                         #size-cells = <1>;
 993                         ranges = <0x0 0x32000 0x1000>;
 994                 };
 995
 996                 target-module@34000 {                   /* 0x4a234000, ap 117 76.1 */
 997                         compatible = "ti,sysc";
 998                         status = "disabled";
 999                         #address-cells = <1>;
1000                         #size-cells = <1>;
1001                         ranges = <0x0 0x34000 0x1000>;
1002                 };
1003
1004                 target-module@36000 {                   /* 0x4a236000, ap 119 62.0 */
1005                         compatible = "ti,sysc";
1006                         status = "disabled";
1007                         #address-cells = <1>;
1008                         #size-cells = <1>;
1009                         ranges = <0x0 0x36000 0x1000>;
1010                 };
1011         };
1012 };
1013
1014 &l4_per1 {                                              /* 0x48000000 */
1015         compatible = "ti,dra7-l4-per1", "simple-bus";
1016         reg = <0x48000000 0x800>,
1017               <0x48000800 0x800>,
1018               <0x48001000 0x400>,
1019               <0x48001400 0x400>,
1020               <0x48001800 0x400>,
1021               <0x48001c00 0x400>;
1022         reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
1023         #address-cells = <1>;
1024         #size-cells = <1>;
1025         ranges = <0x00000000 0x48000000 0x200000>,      /* segment 0 */
1026                  <0x00200000 0x48200000 0x200000>;      /* segment 1 */
1027
1028         segment@0 {                                     /* 0x48000000 */
1029                 compatible = "simple-bus";
1030                 #address-cells = <1>;
1031                 #size-cells = <1>;
1032                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
1033                          <0x00001000 0x00001000 0x000400>,      /* ap 1 */
1034                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
1035                          <0x00020000 0x00020000 0x001000>,      /* ap 3 */
1036                          <0x00021000 0x00021000 0x001000>,      /* ap 4 */
1037                          <0x00032000 0x00032000 0x001000>,      /* ap 5 */
1038                          <0x00033000 0x00033000 0x001000>,      /* ap 6 */
1039                          <0x00034000 0x00034000 0x001000>,      /* ap 7 */
1040                          <0x00035000 0x00035000 0x001000>,      /* ap 8 */
1041                          <0x00036000 0x00036000 0x001000>,      /* ap 9 */
1042                          <0x00037000 0x00037000 0x001000>,      /* ap 10 */
1043                          <0x0003e000 0x0003e000 0x001000>,      /* ap 11 */
1044                          <0x0003f000 0x0003f000 0x001000>,      /* ap 12 */
1045                          <0x00055000 0x00055000 0x001000>,      /* ap 13 */
1046                          <0x00056000 0x00056000 0x001000>,      /* ap 14 */
1047                          <0x00057000 0x00057000 0x001000>,      /* ap 15 */
1048                          <0x00058000 0x00058000 0x001000>,      /* ap 16 */
1049                          <0x00059000 0x00059000 0x001000>,      /* ap 17 */
1050                          <0x0005a000 0x0005a000 0x001000>,      /* ap 18 */
1051                          <0x0005b000 0x0005b000 0x001000>,      /* ap 19 */
1052                          <0x0005c000 0x0005c000 0x001000>,      /* ap 20 */
1053                          <0x0005d000 0x0005d000 0x001000>,      /* ap 21 */
1054                          <0x0005e000 0x0005e000 0x001000>,      /* ap 22 */
1055                          <0x00060000 0x00060000 0x001000>,      /* ap 23 */
1056                          <0x0006a000 0x0006a000 0x001000>,      /* ap 24 */
1057                          <0x0006b000 0x0006b000 0x001000>,      /* ap 25 */
1058                          <0x0006c000 0x0006c000 0x001000>,      /* ap 26 */
1059                          <0x0006d000 0x0006d000 0x001000>,      /* ap 27 */
1060                          <0x0006e000 0x0006e000 0x001000>,      /* ap 28 */
1061                          <0x0006f000 0x0006f000 0x001000>,      /* ap 29 */
1062                          <0x00070000 0x00070000 0x001000>,      /* ap 30 */
1063                          <0x00071000 0x00071000 0x001000>,      /* ap 31 */
1064                          <0x00072000 0x00072000 0x001000>,      /* ap 32 */
1065                          <0x00073000 0x00073000 0x001000>,      /* ap 33 */
1066                          <0x00061000 0x00061000 0x001000>,      /* ap 34 */
1067                          <0x00053000 0x00053000 0x001000>,      /* ap 35 */
1068                          <0x00054000 0x00054000 0x001000>,      /* ap 36 */
1069                          <0x000b2000 0x000b2000 0x001000>,      /* ap 37 */
1070                          <0x000b3000 0x000b3000 0x001000>,      /* ap 38 */
1071                          <0x00078000 0x00078000 0x001000>,      /* ap 39 */
1072                          <0x00079000 0x00079000 0x001000>,      /* ap 40 */
1073                          <0x00086000 0x00086000 0x001000>,      /* ap 41 */
1074                          <0x00087000 0x00087000 0x001000>,      /* ap 42 */
1075                          <0x00088000 0x00088000 0x001000>,      /* ap 43 */
1076                          <0x00089000 0x00089000 0x001000>,      /* ap 44 */
1077                          <0x00051000 0x00051000 0x001000>,      /* ap 45 */
1078                          <0x00052000 0x00052000 0x001000>,      /* ap 46 */
1079                          <0x00098000 0x00098000 0x001000>,      /* ap 47 */
1080                          <0x00099000 0x00099000 0x001000>,      /* ap 48 */
1081                          <0x0009a000 0x0009a000 0x001000>,      /* ap 49 */
1082                          <0x0009b000 0x0009b000 0x001000>,      /* ap 50 */
1083                          <0x0009c000 0x0009c000 0x001000>,      /* ap 51 */
1084                          <0x0009d000 0x0009d000 0x001000>,      /* ap 52 */
1085                          <0x00068000 0x00068000 0x001000>,      /* ap 53 */
1086                          <0x00069000 0x00069000 0x001000>,      /* ap 54 */
1087                          <0x00090000 0x00090000 0x002000>,      /* ap 55 */
1088                          <0x00092000 0x00092000 0x001000>,      /* ap 56 */
1089                          <0x000a4000 0x000a4000 0x001000>,      /* ap 57 */
1090                          <0x000a6000 0x000a6000 0x001000>,      /* ap 58 */
1091                          <0x000a8000 0x000a8000 0x004000>,      /* ap 59 */
1092                          <0x000ac000 0x000ac000 0x001000>,      /* ap 60 */
1093                          <0x000ad000 0x000ad000 0x001000>,      /* ap 61 */
1094                          <0x000ae000 0x000ae000 0x001000>,      /* ap 62 */
1095                          <0x00066000 0x00066000 0x001000>,      /* ap 63 */
1096                          <0x00067000 0x00067000 0x001000>,      /* ap 64 */
1097                          <0x000b4000 0x000b4000 0x001000>,      /* ap 65 */
1098                          <0x000b5000 0x000b5000 0x001000>,      /* ap 66 */
1099                          <0x000b8000 0x000b8000 0x001000>,      /* ap 67 */
1100                          <0x000b9000 0x000b9000 0x001000>,      /* ap 68 */
1101                          <0x000ba000 0x000ba000 0x001000>,      /* ap 69 */
1102                          <0x000bb000 0x000bb000 0x001000>,      /* ap 70 */
1103                          <0x000d1000 0x000d1000 0x001000>,      /* ap 71 */
1104                          <0x000d2000 0x000d2000 0x001000>,      /* ap 72 */
1105                          <0x000d5000 0x000d5000 0x001000>,      /* ap 73 */
1106                          <0x000d6000 0x000d6000 0x001000>,      /* ap 74 */
1107                          <0x000a2000 0x000a2000 0x001000>,      /* ap 75 */
1108                          <0x000a3000 0x000a3000 0x001000>,      /* ap 76 */
1109                          <0x00001400 0x00001400 0x000400>,      /* ap 77 */
1110                          <0x00001800 0x00001800 0x000400>,      /* ap 78 */
1111                          <0x00001c00 0x00001c00 0x000400>,      /* ap 79 */
1112                          <0x000a5000 0x000a5000 0x001000>,      /* ap 80 */
1113                          <0x0007a000 0x0007a000 0x001000>,      /* ap 81 */
1114                          <0x0007b000 0x0007b000 0x001000>,      /* ap 82 */
1115                          <0x0007c000 0x0007c000 0x001000>,      /* ap 83 */
1116                          <0x0007d000 0x0007d000 0x001000>;      /* ap 84 */
1117
1118                 target-module@20000 {                   /* 0x48020000, ap 3 04.0 */
1119                         compatible = "ti,sysc-omap2", "ti,sysc";
1120                         reg = <0x20050 0x4>,
1121                               <0x20054 0x4>,
1122                               <0x20058 0x4>;
1123                         reg-names = "rev", "sysc", "syss";
1124                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1125                                          SYSC_OMAP2_SOFTRESET |
1126                                          SYSC_OMAP2_AUTOIDLE)>;
1127                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1128                                         <SYSC_IDLE_NO>,
1129                                         <SYSC_IDLE_SMART>,
1130                                         <SYSC_IDLE_SMART_WKUP>;
1131                         ti,syss-mask = <1>;
1132                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1133                         clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1134                         clock-names = "fck";
1135                         #address-cells = <1>;
1136                         #size-cells = <1>;
1137                         ranges = <0x0 0x20000 0x1000>;
1138
1139                         uart3: serial@0 {
1140                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1141                                 reg = <0x0 0x100>;
1142                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1143                                 clock-frequency = <48000000>;
1144                                 status = "disabled";
1145                                 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
1146                                 dma-names = "tx", "rx";
1147                         };
1148                 };
1149
1150                 target-module@32000 {                   /* 0x48032000, ap 5 3e.0 */
1151                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1152                         ti,hwmods = "timer2";
1153                         reg = <0x32000 0x4>,
1154                               <0x32010 0x4>;
1155                         reg-names = "rev", "sysc";
1156                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1157                                          SYSC_OMAP4_SOFTRESET)>;
1158                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1159                                         <SYSC_IDLE_NO>,
1160                                         <SYSC_IDLE_SMART>,
1161                                         <SYSC_IDLE_SMART_WKUP>;
1162                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1163                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1164                         clock-names = "fck";
1165                         #address-cells = <1>;
1166                         #size-cells = <1>;
1167                         ranges = <0x0 0x32000 0x1000>;
1168
1169                         timer2: timer@0 {
1170                                 compatible = "ti,omap5430-timer";
1171                                 reg = <0x0 0x80>;
1172                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>;
1173                                 clock-names = "fck";
1174                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1175                         };
1176                 };
1177
1178                 target-module@34000 {                   /* 0x48034000, ap 7 46.0 */
1179                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1180                         ti,hwmods = "timer3";
1181                         reg = <0x34000 0x4>,
1182                               <0x34010 0x4>;
1183                         reg-names = "rev", "sysc";
1184                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1185                                          SYSC_OMAP4_SOFTRESET)>;
1186                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1187                                         <SYSC_IDLE_NO>,
1188                                         <SYSC_IDLE_SMART>,
1189                                         <SYSC_IDLE_SMART_WKUP>;
1190                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1191                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1192                         clock-names = "fck";
1193                         #address-cells = <1>;
1194                         #size-cells = <1>;
1195                         ranges = <0x0 0x34000 0x1000>;
1196
1197                         timer3: timer@0 {
1198                                 compatible = "ti,omap5430-timer";
1199                                 reg = <0x0 0x80>;
1200                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
1201                                 clock-names = "fck";
1202                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1203                         };
1204                 };
1205
1206                 target-module@36000 {                   /* 0x48036000, ap 9 4e.0 */
1207                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1208                         ti,hwmods = "timer4";
1209                         reg = <0x36000 0x4>,
1210                               <0x36010 0x4>;
1211                         reg-names = "rev", "sysc";
1212                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1213                                          SYSC_OMAP4_SOFTRESET)>;
1214                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1215                                         <SYSC_IDLE_NO>,
1216                                         <SYSC_IDLE_SMART>,
1217                                         <SYSC_IDLE_SMART_WKUP>;
1218                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1219                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1220                         clock-names = "fck";
1221                         #address-cells = <1>;
1222                         #size-cells = <1>;
1223                         ranges = <0x0 0x36000 0x1000>;
1224
1225                         timer4: timer@0 {
1226                                 compatible = "ti,omap5430-timer";
1227                                 reg = <0x0 0x80>;
1228                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
1229                                 clock-names = "fck";
1230                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1231                         };
1232                 };
1233
1234                 target-module@3e000 {                   /* 0x4803e000, ap 11 56.0 */
1235                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1236                         ti,hwmods = "timer9";
1237                         reg = <0x3e000 0x4>,
1238                               <0x3e010 0x4>;
1239                         reg-names = "rev", "sysc";
1240                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1241                                          SYSC_OMAP4_SOFTRESET)>;
1242                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1243                                         <SYSC_IDLE_NO>,
1244                                         <SYSC_IDLE_SMART>,
1245                                         <SYSC_IDLE_SMART_WKUP>;
1246                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1247                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1248                         clock-names = "fck";
1249                         #address-cells = <1>;
1250                         #size-cells = <1>;
1251                         ranges = <0x0 0x3e000 0x1000>;
1252
1253                         timer9: timer@0 {
1254                                 compatible = "ti,omap5430-timer";
1255                                 reg = <0x0 0x80>;
1256                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>;
1257                                 clock-names = "fck";
1258                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1259                         };
1260                 };
1261
1262                 gpio7_target: target-module@51000 {             /* 0x48051000, ap 45 2e.0 */
1263                         compatible = "ti,sysc-omap2", "ti,sysc";
1264                         reg = <0x51000 0x4>,
1265                               <0x51010 0x4>,
1266                               <0x51114 0x4>;
1267                         reg-names = "rev", "sysc", "syss";
1268                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1269                                          SYSC_OMAP2_SOFTRESET |
1270                                          SYSC_OMAP2_AUTOIDLE)>;
1271                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1272                                         <SYSC_IDLE_NO>,
1273                                         <SYSC_IDLE_SMART>,
1274                                         <SYSC_IDLE_SMART_WKUP>;
1275                         ti,syss-mask = <1>;
1276                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1277                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1278                                  <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
1279                         clock-names = "fck", "dbclk";
1280                         #address-cells = <1>;
1281                         #size-cells = <1>;
1282                         ranges = <0x0 0x51000 0x1000>;
1283
1284                         gpio7: gpio@0 {
1285                                 compatible = "ti,omap4-gpio";
1286                                 reg = <0x0 0x200>;
1287                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1288                                 gpio-controller;
1289                                 #gpio-cells = <2>;
1290                                 interrupt-controller;
1291                                 #interrupt-cells = <2>;
1292                         };
1293                 };
1294
1295                 target-module@53000 {                   /* 0x48053000, ap 35 36.0 */
1296                         compatible = "ti,sysc-omap2", "ti,sysc";
1297                         reg = <0x53000 0x4>,
1298                               <0x53010 0x4>,
1299                               <0x53114 0x4>;
1300                         reg-names = "rev", "sysc", "syss";
1301                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1302                                          SYSC_OMAP2_SOFTRESET |
1303                                          SYSC_OMAP2_AUTOIDLE)>;
1304                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1305                                         <SYSC_IDLE_NO>,
1306                                         <SYSC_IDLE_SMART>,
1307                                         <SYSC_IDLE_SMART_WKUP>;
1308                         ti,syss-mask = <1>;
1309                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1310                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1311                                  <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
1312                         clock-names = "fck", "dbclk";
1313                         #address-cells = <1>;
1314                         #size-cells = <1>;
1315                         ranges = <0x0 0x53000 0x1000>;
1316
1317                         gpio8: gpio@0 {
1318                                 compatible = "ti,omap4-gpio";
1319                                 reg = <0x0 0x200>;
1320                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1321                                 gpio-controller;
1322                                 #gpio-cells = <2>;
1323                                 interrupt-controller;
1324                                 #interrupt-cells = <2>;
1325                         };
1326                 };
1327
1328                 target-module@55000 {                   /* 0x48055000, ap 13 0e.0 */
1329                         compatible = "ti,sysc-omap2", "ti,sysc";
1330                         reg = <0x55000 0x4>,
1331                               <0x55010 0x4>,
1332                               <0x55114 0x4>;
1333                         reg-names = "rev", "sysc", "syss";
1334                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1335                                          SYSC_OMAP2_SOFTRESET |
1336                                          SYSC_OMAP2_AUTOIDLE)>;
1337                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1338                                         <SYSC_IDLE_NO>,
1339                                         <SYSC_IDLE_SMART>,
1340                                         <SYSC_IDLE_SMART_WKUP>;
1341                         ti,syss-mask = <1>;
1342                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1343                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1344                                  <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
1345                         clock-names = "fck", "dbclk";
1346                         #address-cells = <1>;
1347                         #size-cells = <1>;
1348                         ranges = <0x0 0x55000 0x1000>;
1349
1350                         gpio2: gpio@0 {
1351                                 compatible = "ti,omap4-gpio";
1352                                 reg = <0x0 0x200>;
1353                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1354                                 gpio-controller;
1355                                 #gpio-cells = <2>;
1356                                 interrupt-controller;
1357                                 #interrupt-cells = <2>;
1358                         };
1359                 };
1360
1361                 target-module@57000 {                   /* 0x48057000, ap 15 06.0 */
1362                         compatible = "ti,sysc-omap2", "ti,sysc";
1363                         reg = <0x57000 0x4>,
1364                               <0x57010 0x4>,
1365                               <0x57114 0x4>;
1366                         reg-names = "rev", "sysc", "syss";
1367                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1368                                          SYSC_OMAP2_SOFTRESET |
1369                                          SYSC_OMAP2_AUTOIDLE)>;
1370                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1371                                         <SYSC_IDLE_NO>,
1372                                         <SYSC_IDLE_SMART>,
1373                                         <SYSC_IDLE_SMART_WKUP>;
1374                         ti,syss-mask = <1>;
1375                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1376                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1377                                  <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
1378                         clock-names = "fck", "dbclk";
1379                         #address-cells = <1>;
1380                         #size-cells = <1>;
1381                         ranges = <0x0 0x57000 0x1000>;
1382
1383                         gpio3: gpio@0 {
1384                                 compatible = "ti,omap4-gpio";
1385                                 reg = <0x0 0x200>;
1386                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1387                                 gpio-controller;
1388                                 #gpio-cells = <2>;
1389                                 interrupt-controller;
1390                                 #interrupt-cells = <2>;
1391                         };
1392                 };
1393
1394                 target-module@59000 {                   /* 0x48059000, ap 17 16.0 */
1395                         compatible = "ti,sysc-omap2", "ti,sysc";
1396                         reg = <0x59000 0x4>,
1397                               <0x59010 0x4>,
1398                               <0x59114 0x4>;
1399                         reg-names = "rev", "sysc", "syss";
1400                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1401                                          SYSC_OMAP2_SOFTRESET |
1402                                          SYSC_OMAP2_AUTOIDLE)>;
1403                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1404                                         <SYSC_IDLE_NO>,
1405                                         <SYSC_IDLE_SMART>,
1406                                         <SYSC_IDLE_SMART_WKUP>;
1407                         ti,syss-mask = <1>;
1408                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1409                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1410                                  <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
1411                         clock-names = "fck", "dbclk";
1412                         #address-cells = <1>;
1413                         #size-cells = <1>;
1414                         ranges = <0x0 0x59000 0x1000>;
1415
1416                         gpio4: gpio@0 {
1417                                 compatible = "ti,omap4-gpio";
1418                                 reg = <0x0 0x200>;
1419                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1420                                 gpio-controller;
1421                                 #gpio-cells = <2>;
1422                                 interrupt-controller;
1423                                 #interrupt-cells = <2>;
1424                         };
1425                 };
1426
1427                 target-module@5b000 {                   /* 0x4805b000, ap 19 1e.0 */
1428                         compatible = "ti,sysc-omap2", "ti,sysc";
1429                         reg = <0x5b000 0x4>,
1430                               <0x5b010 0x4>,
1431                               <0x5b114 0x4>;
1432                         reg-names = "rev", "sysc", "syss";
1433                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1434                                          SYSC_OMAP2_SOFTRESET |
1435                                          SYSC_OMAP2_AUTOIDLE)>;
1436                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1437                                         <SYSC_IDLE_NO>,
1438                                         <SYSC_IDLE_SMART>,
1439                                         <SYSC_IDLE_SMART_WKUP>;
1440                         ti,syss-mask = <1>;
1441                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1442                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1443                                  <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
1444                         clock-names = "fck", "dbclk";
1445                         #address-cells = <1>;
1446                         #size-cells = <1>;
1447                         ranges = <0x0 0x5b000 0x1000>;
1448
1449                         gpio5: gpio@0 {
1450                                 compatible = "ti,omap4-gpio";
1451                                 reg = <0x0 0x200>;
1452                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1453                                 gpio-controller;
1454                                 #gpio-cells = <2>;
1455                                 interrupt-controller;
1456                                 #interrupt-cells = <2>;
1457                         };
1458                 };
1459
1460                 target-module@5d000 {                   /* 0x4805d000, ap 21 26.0 */
1461                         compatible = "ti,sysc-omap2", "ti,sysc";
1462                         reg = <0x5d000 0x4>,
1463                               <0x5d010 0x4>,
1464                               <0x5d114 0x4>;
1465                         reg-names = "rev", "sysc", "syss";
1466                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1467                                          SYSC_OMAP2_SOFTRESET |
1468                                          SYSC_OMAP2_AUTOIDLE)>;
1469                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1470                                         <SYSC_IDLE_NO>,
1471                                         <SYSC_IDLE_SMART>,
1472                                         <SYSC_IDLE_SMART_WKUP>;
1473                         ti,syss-mask = <1>;
1474                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1475                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1476                                  <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
1477                         clock-names = "fck", "dbclk";
1478                         #address-cells = <1>;
1479                         #size-cells = <1>;
1480                         ranges = <0x0 0x5d000 0x1000>;
1481
1482                         gpio6: gpio@0 {
1483                                 compatible = "ti,omap4-gpio";
1484                                 reg = <0x0 0x200>;
1485                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1486                                 gpio-controller;
1487                                 #gpio-cells = <2>;
1488                                 interrupt-controller;
1489                                 #interrupt-cells = <2>;
1490                         };
1491                 };
1492
1493                 target-module@60000 {                   /* 0x48060000, ap 23 32.0 */
1494                         compatible = "ti,sysc-omap2", "ti,sysc";
1495                         reg = <0x60000 0x8>,
1496                               <0x60010 0x8>,
1497                               <0x60090 0x8>;
1498                         reg-names = "rev", "sysc", "syss";
1499                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1500                                          SYSC_OMAP2_ENAWAKEUP |
1501                                          SYSC_OMAP2_SOFTRESET |
1502                                          SYSC_OMAP2_AUTOIDLE)>;
1503                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1504                                         <SYSC_IDLE_NO>,
1505                                         <SYSC_IDLE_SMART>,
1506                                         <SYSC_IDLE_SMART_WKUP>;
1507                         ti,syss-mask = <1>;
1508                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1509                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1510                         clock-names = "fck";
1511                         #address-cells = <1>;
1512                         #size-cells = <1>;
1513                         ranges = <0x0 0x60000 0x1000>;
1514
1515                         i2c3: i2c@0 {
1516                                 compatible = "ti,omap4-i2c";
1517                                 reg = <0x0 0x100>;
1518                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1519                                 #address-cells = <1>;
1520                                 #size-cells = <0>;
1521                                 status = "disabled";
1522                         };
1523                 };
1524
1525                 target-module@66000 {                   /* 0x48066000, ap 63 14.0 */
1526                         compatible = "ti,sysc-omap2", "ti,sysc";
1527                         reg = <0x66050 0x4>,
1528                               <0x66054 0x4>,
1529                               <0x66058 0x4>;
1530                         reg-names = "rev", "sysc", "syss";
1531                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1532                                          SYSC_OMAP2_SOFTRESET |
1533                                          SYSC_OMAP2_AUTOIDLE)>;
1534                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1535                                         <SYSC_IDLE_NO>,
1536                                         <SYSC_IDLE_SMART>,
1537                                         <SYSC_IDLE_SMART_WKUP>;
1538                         ti,syss-mask = <1>;
1539                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1540                         clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1541                         clock-names = "fck";
1542                         #address-cells = <1>;
1543                         #size-cells = <1>;
1544                         ranges = <0x0 0x66000 0x1000>;
1545
1546                         uart5: serial@0 {
1547                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1548                                 reg = <0x0 0x100>;
1549                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1550                                 clock-frequency = <48000000>;
1551                                 status = "disabled";
1552                                 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
1553                                 dma-names = "tx", "rx";
1554                         };
1555                 };
1556
1557                 target-module@68000 {                   /* 0x48068000, ap 53 1c.0 */
1558                         compatible = "ti,sysc-omap2", "ti,sysc";
1559                         reg = <0x68050 0x4>,
1560                               <0x68054 0x4>,
1561                               <0x68058 0x4>;
1562                         reg-names = "rev", "sysc", "syss";
1563                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1564                                          SYSC_OMAP2_SOFTRESET |
1565                                          SYSC_OMAP2_AUTOIDLE)>;
1566                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1567                                         <SYSC_IDLE_NO>,
1568                                         <SYSC_IDLE_SMART>,
1569                                         <SYSC_IDLE_SMART_WKUP>;
1570                         ti,syss-mask = <1>;
1571                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1572                         clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1573                         clock-names = "fck";
1574                         #address-cells = <1>;
1575                         #size-cells = <1>;
1576                         ranges = <0x0 0x68000 0x1000>;
1577
1578                         uart6: serial@0 {
1579                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1580                                 reg = <0x0 0x100>;
1581                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1582                                 clock-frequency = <48000000>;
1583                                 status = "disabled";
1584                                 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
1585                                 dma-names = "tx", "rx";
1586                         };
1587                 };
1588
1589                 target-module@6a000 {                   /* 0x4806a000, ap 24 24.0 */
1590                         compatible = "ti,sysc-omap2", "ti,sysc";
1591                         reg = <0x6a050 0x4>,
1592                               <0x6a054 0x4>,
1593                               <0x6a058 0x4>;
1594                         reg-names = "rev", "sysc", "syss";
1595                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1596                                          SYSC_OMAP2_SOFTRESET |
1597                                          SYSC_OMAP2_AUTOIDLE)>;
1598                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1599                                         <SYSC_IDLE_NO>,
1600                                         <SYSC_IDLE_SMART>,
1601                                         <SYSC_IDLE_SMART_WKUP>;
1602                         ti,syss-mask = <1>;
1603                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1604                         clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1605                         clock-names = "fck";
1606                         #address-cells = <1>;
1607                         #size-cells = <1>;
1608                         ranges = <0x0 0x6a000 0x1000>;
1609
1610                         uart1: serial@0 {
1611                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1612                                 reg = <0x0 0x100>;
1613                                 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1614                                 clock-frequency = <48000000>;
1615                                 status = "disabled";
1616                                 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
1617                                 dma-names = "tx", "rx";
1618                         };
1619                 };
1620
1621                 target-module@6c000 {                   /* 0x4806c000, ap 26 2c.0 */
1622                         compatible = "ti,sysc-omap2", "ti,sysc";
1623                         reg = <0x6c050 0x4>,
1624                               <0x6c054 0x4>,
1625                               <0x6c058 0x4>;
1626                         reg-names = "rev", "sysc", "syss";
1627                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1628                                          SYSC_OMAP2_SOFTRESET |
1629                                          SYSC_OMAP2_AUTOIDLE)>;
1630                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1631                                         <SYSC_IDLE_NO>,
1632                                         <SYSC_IDLE_SMART>,
1633                                         <SYSC_IDLE_SMART_WKUP>;
1634                         ti,syss-mask = <1>;
1635                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1636                         clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1637                         clock-names = "fck";
1638                         #address-cells = <1>;
1639                         #size-cells = <1>;
1640                         ranges = <0x0 0x6c000 0x1000>;
1641
1642                         uart2: serial@0 {
1643                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1644                                 reg = <0x0 0x100>;
1645                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1646                                 clock-frequency = <48000000>;
1647                                 status = "disabled";
1648                                 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
1649                                 dma-names = "tx", "rx";
1650                         };
1651                 };
1652
1653                 target-module@6e000 {                   /* 0x4806e000, ap 28 0c.1 */
1654                         compatible = "ti,sysc-omap2", "ti,sysc";
1655                         reg = <0x6e050 0x4>,
1656                               <0x6e054 0x4>,
1657                               <0x6e058 0x4>;
1658                         reg-names = "rev", "sysc", "syss";
1659                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1660                                          SYSC_OMAP2_SOFTRESET |
1661                                          SYSC_OMAP2_AUTOIDLE)>;
1662                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1663                                         <SYSC_IDLE_NO>,
1664                                         <SYSC_IDLE_SMART>,
1665                                         <SYSC_IDLE_SMART_WKUP>;
1666                         ti,syss-mask = <1>;
1667                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1668                         clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1669                         clock-names = "fck";
1670                         #address-cells = <1>;
1671                         #size-cells = <1>;
1672                         ranges = <0x0 0x6e000 0x1000>;
1673
1674                         uart4: serial@0 {
1675                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1676                                 reg = <0x0 0x100>;
1677                                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1678                                 clock-frequency = <48000000>;
1679                                                 status = "disabled";
1680                                 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
1681                                 dma-names = "tx", "rx";
1682                         };
1683                 };
1684
1685                 target-module@70000 {                   /* 0x48070000, ap 30 22.0 */
1686                         compatible = "ti,sysc-omap2", "ti,sysc";
1687                         reg = <0x70000 0x8>,
1688                               <0x70010 0x8>,
1689                               <0x70090 0x8>;
1690                         reg-names = "rev", "sysc", "syss";
1691                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1692                                          SYSC_OMAP2_ENAWAKEUP |
1693                                          SYSC_OMAP2_SOFTRESET |
1694                                          SYSC_OMAP2_AUTOIDLE)>;
1695                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1696                                         <SYSC_IDLE_NO>,
1697                                         <SYSC_IDLE_SMART>,
1698                                         <SYSC_IDLE_SMART_WKUP>;
1699                         ti,syss-mask = <1>;
1700                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1701                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1702                         clock-names = "fck";
1703                         #address-cells = <1>;
1704                         #size-cells = <1>;
1705                         ranges = <0x0 0x70000 0x1000>;
1706
1707                         i2c1: i2c@0 {
1708                                 compatible = "ti,omap4-i2c";
1709                                 reg = <0x0 0x100>;
1710                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1711                                 #address-cells = <1>;
1712                                 #size-cells = <0>;
1713                                 status = "disabled";
1714                         };
1715                 };
1716
1717                 target-module@72000 {                   /* 0x48072000, ap 32 2a.0 */
1718                         compatible = "ti,sysc-omap2", "ti,sysc";
1719                         reg = <0x72000 0x8>,
1720                               <0x72010 0x8>,
1721                               <0x72090 0x8>;
1722                         reg-names = "rev", "sysc", "syss";
1723                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1724                                          SYSC_OMAP2_ENAWAKEUP |
1725                                          SYSC_OMAP2_SOFTRESET |
1726                                          SYSC_OMAP2_AUTOIDLE)>;
1727                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1728                                         <SYSC_IDLE_NO>,
1729                                         <SYSC_IDLE_SMART>,
1730                                         <SYSC_IDLE_SMART_WKUP>;
1731                         ti,syss-mask = <1>;
1732                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1733                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1734                         clock-names = "fck";
1735                         #address-cells = <1>;
1736                         #size-cells = <1>;
1737                         ranges = <0x0 0x72000 0x1000>;
1738
1739                         i2c2: i2c@0 {
1740                                 compatible = "ti,omap4-i2c";
1741                                 reg = <0x0 0x100>;
1742                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1743                                 #address-cells = <1>;
1744                                 #size-cells = <0>;
1745                                 status = "disabled";
1746                         };
1747                 };
1748
1749                 target-module@78000 {                   /* 0x48078000, ap 39 0a.0 */
1750                         compatible = "ti,sysc-omap2", "ti,sysc";
1751                         ti,hwmods = "elm";
1752                         reg = <0x78000 0x4>,
1753                               <0x78010 0x4>,
1754                               <0x78014 0x4>;
1755                         reg-names = "rev", "sysc", "syss";
1756                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1757                                          SYSC_OMAP2_SOFTRESET |
1758                                          SYSC_OMAP2_AUTOIDLE)>;
1759                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1760                                         <SYSC_IDLE_NO>,
1761                                         <SYSC_IDLE_SMART>,
1762                                         <SYSC_IDLE_SMART_WKUP>;
1763                         ti,syss-mask = <1>;
1764                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1765                         clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1766                         clock-names = "fck";
1767                         #address-cells = <1>;
1768                         #size-cells = <1>;
1769                         ranges = <0x0 0x78000 0x1000>;
1770
1771                         elm: elm@0 {
1772                                 compatible = "ti,am3352-elm";
1773                                 reg = <0x0 0xfc0>;      /* device IO registers */
1774                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1775                                 status = "disabled";
1776                         };
1777                 };
1778
1779                 target-module@7a000 {                   /* 0x4807a000, ap 81 3a.0 */
1780                         compatible = "ti,sysc-omap2", "ti,sysc";
1781                         reg = <0x7a000 0x8>,
1782                               <0x7a010 0x8>,
1783                               <0x7a090 0x8>;
1784                         reg-names = "rev", "sysc", "syss";
1785                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1786                                          SYSC_OMAP2_ENAWAKEUP |
1787                                          SYSC_OMAP2_SOFTRESET |
1788                                          SYSC_OMAP2_AUTOIDLE)>;
1789                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1790                                         <SYSC_IDLE_NO>,
1791                                         <SYSC_IDLE_SMART>,
1792                                         <SYSC_IDLE_SMART_WKUP>;
1793                         ti,syss-mask = <1>;
1794                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1795                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1796                         clock-names = "fck";
1797                         #address-cells = <1>;
1798                         #size-cells = <1>;
1799                         ranges = <0x0 0x7a000 0x1000>;
1800
1801                         i2c4: i2c@0 {
1802                                 compatible = "ti,omap4-i2c";
1803                                 reg = <0x0 0x100>;
1804                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1805                                 #address-cells = <1>;
1806                                 #size-cells = <0>;
1807                                 status = "disabled";
1808                         };
1809                 };
1810
1811                 target-module@7c000 {                   /* 0x4807c000, ap 83 4a.0 */
1812                         compatible = "ti,sysc-omap2", "ti,sysc";
1813                         reg = <0x7c000 0x8>,
1814                               <0x7c010 0x8>,
1815                               <0x7c090 0x8>;
1816                         reg-names = "rev", "sysc", "syss";
1817                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1818                                          SYSC_OMAP2_ENAWAKEUP |
1819                                          SYSC_OMAP2_SOFTRESET |
1820                                          SYSC_OMAP2_AUTOIDLE)>;
1821                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1822                                         <SYSC_IDLE_NO>,
1823                                         <SYSC_IDLE_SMART>,
1824                                         <SYSC_IDLE_SMART_WKUP>;
1825                         ti,syss-mask = <1>;
1826                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1827                         clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1828                         clock-names = "fck";
1829                         #address-cells = <1>;
1830                         #size-cells = <1>;
1831                         ranges = <0x0 0x7c000 0x1000>;
1832
1833                         i2c5: i2c@0 {
1834                                 compatible = "ti,omap4-i2c";
1835                                 reg = <0x0 0x100>;
1836                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1837                                 #address-cells = <1>;
1838                                 #size-cells = <0>;
1839                                 status = "disabled";
1840                         };
1841                 };
1842
1843                 target-module@86000 {                   /* 0x48086000, ap 41 5e.0 */
1844                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1845                         ti,hwmods = "timer10";
1846                         reg = <0x86000 0x4>,
1847                               <0x86010 0x4>;
1848                         reg-names = "rev", "sysc";
1849                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1850                                          SYSC_OMAP4_SOFTRESET)>;
1851                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1852                                         <SYSC_IDLE_NO>,
1853                                         <SYSC_IDLE_SMART>,
1854                                         <SYSC_IDLE_SMART_WKUP>;
1855                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1856                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1857                         clock-names = "fck";
1858                         #address-cells = <1>;
1859                         #size-cells = <1>;
1860                         ranges = <0x0 0x86000 0x1000>;
1861
1862                         timer10: timer@0 {
1863                                 compatible = "ti,omap5430-timer";
1864                                 reg = <0x0 0x80>;
1865                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>;
1866                                 clock-names = "fck";
1867                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1868                         };
1869                 };
1870
1871                 target-module@88000 {                   /* 0x48088000, ap 43 66.0 */
1872                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1873                         ti,hwmods = "timer11";
1874                         reg = <0x88000 0x4>,
1875                               <0x88010 0x4>;
1876                         reg-names = "rev", "sysc";
1877                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1878                                          SYSC_OMAP4_SOFTRESET)>;
1879                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1880                                         <SYSC_IDLE_NO>,
1881                                         <SYSC_IDLE_SMART>,
1882                                         <SYSC_IDLE_SMART_WKUP>;
1883                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1884                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1885                         clock-names = "fck";
1886                         #address-cells = <1>;
1887                         #size-cells = <1>;
1888                         ranges = <0x0 0x88000 0x1000>;
1889
1890                         timer11: timer@0 {
1891                                 compatible = "ti,omap5430-timer";
1892                                 reg = <0x0 0x80>;
1893                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>;
1894                                 clock-names = "fck";
1895                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1896                         };
1897                 };
1898
1899                 target-module@90000 {                   /* 0x48090000, ap 55 12.0 */
1900                         compatible = "ti,sysc-omap2", "ti,sysc";
1901                         reg = <0x91fe0 0x4>,
1902                               <0x91fe4 0x4>;
1903                         reg-names = "rev", "sysc";
1904                         ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
1905                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1906                                         <SYSC_IDLE_NO>;
1907                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1908                         clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1909                         clock-names = "fck";
1910                         #address-cells = <1>;
1911                         #size-cells = <1>;
1912                         ranges = <0x0 0x90000 0x2000>;
1913
1914                         rng: rng@0 {
1915                                 compatible = "ti,omap4-rng";
1916                                 reg = <0x0 0x2000>;
1917                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1918                                 clocks = <&l3_iclk_div>;
1919                                 clock-names = "fck";
1920                         };
1921                 };
1922
1923                 target-module@98000 {                   /* 0x48098000, ap 47 08.0 */
1924                         compatible = "ti,sysc-omap4", "ti,sysc";
1925                         reg = <0x98000 0x4>,
1926                               <0x98010 0x4>;
1927                         reg-names = "rev", "sysc";
1928                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1929                                          SYSC_OMAP4_SOFTRESET)>;
1930                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1931                                         <SYSC_IDLE_NO>,
1932                                         <SYSC_IDLE_SMART>,
1933                                         <SYSC_IDLE_SMART_WKUP>;
1934                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1935                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1936                         clock-names = "fck";
1937                         #address-cells = <1>;
1938                         #size-cells = <1>;
1939                         ranges = <0x0 0x98000 0x1000>;
1940
1941                         mcspi1: spi@0 {
1942                                 compatible = "ti,omap4-mcspi";
1943                                 reg = <0x0 0x200>;
1944                                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1945                                 #address-cells = <1>;
1946                                 #size-cells = <0>;
1947                                 ti,spi-num-cs = <4>;
1948                                 dmas = <&sdma_xbar 35>,
1949                                        <&sdma_xbar 36>,
1950                                        <&sdma_xbar 37>,
1951                                        <&sdma_xbar 38>,
1952                                        <&sdma_xbar 39>,
1953                                        <&sdma_xbar 40>,
1954                                        <&sdma_xbar 41>,
1955                                        <&sdma_xbar 42>;
1956                                 dma-names = "tx0", "rx0", "tx1", "rx1",
1957                                             "tx2", "rx2", "tx3", "rx3";
1958                                 status = "disabled";
1959                         };
1960                 };
1961
1962                 target-module@9a000 {                   /* 0x4809a000, ap 49 10.0 */
1963                         compatible = "ti,sysc-omap4", "ti,sysc";
1964                         reg = <0x9a000 0x4>,
1965                               <0x9a010 0x4>;
1966                         reg-names = "rev", "sysc";
1967                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1968                                          SYSC_OMAP4_SOFTRESET)>;
1969                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1970                                         <SYSC_IDLE_NO>,
1971                                         <SYSC_IDLE_SMART>,
1972                                         <SYSC_IDLE_SMART_WKUP>;
1973                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1974                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1975                         clock-names = "fck";
1976                         #address-cells = <1>;
1977                         #size-cells = <1>;
1978                         ranges = <0x0 0x9a000 0x1000>;
1979
1980                         mcspi2: spi@0 {
1981                                 compatible = "ti,omap4-mcspi";
1982                                 reg = <0x0 0x200>;
1983                                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1984                                 #address-cells = <1>;
1985                                 #size-cells = <0>;
1986                                 ti,spi-num-cs = <2>;
1987                                 dmas = <&sdma_xbar 43>,
1988                                        <&sdma_xbar 44>,
1989                                        <&sdma_xbar 45>,
1990                                        <&sdma_xbar 46>;
1991                                 dma-names = "tx0", "rx0", "tx1", "rx1";
1992                                 status = "disabled";
1993                         };
1994                 };
1995
1996                 target-module@9c000 {                   /* 0x4809c000, ap 51 38.0 */
1997                         compatible = "ti,sysc-omap4", "ti,sysc";
1998                         reg = <0x9c000 0x4>,
1999                               <0x9c010 0x4>;
2000                         reg-names = "rev", "sysc";
2001                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2002                                          SYSC_OMAP4_SOFTRESET)>;
2003                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2004                                         <SYSC_IDLE_NO>,
2005                                         <SYSC_IDLE_SMART>,
2006                                         <SYSC_IDLE_SMART_WKUP>;
2007                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2008                                         <SYSC_IDLE_NO>,
2009                                         <SYSC_IDLE_SMART>,
2010                                         <SYSC_IDLE_SMART_WKUP>;
2011                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2012                         clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2013                         clock-names = "fck";
2014                         #address-cells = <1>;
2015                         #size-cells = <1>;
2016                         ranges = <0x0 0x9c000 0x1000>;
2017
2018                         mmc1: mmc@0 {
2019                                 compatible = "ti,dra7-sdhci";
2020                                 reg = <0x0 0x400>;
2021                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
2022                                 status = "disabled";
2023                                 pbias-supply = <&pbias_mmc_reg>;
2024                                 max-frequency = <192000000>;
2025                                 mmc-ddr-1_8v;
2026                                 mmc-ddr-3_3v;
2027                         };
2028                 };
2029
2030                 target-module@a2000 {                   /* 0x480a2000, ap 75 02.0 */
2031                         compatible = "ti,sysc";
2032                         status = "disabled";
2033                         #address-cells = <1>;
2034                         #size-cells = <1>;
2035                         ranges = <0x0 0xa2000 0x1000>;
2036                 };
2037
2038                 target-module@a4000 {                   /* 0x480a4000, ap 57 42.0 */
2039                         compatible = "ti,sysc";
2040                         status = "disabled";
2041                         #address-cells = <1>;
2042                         #size-cells = <1>;
2043                         ranges = <0x00000000 0x000a4000 0x00001000>,
2044                                  <0x00001000 0x000a5000 0x00001000>;
2045                 };
2046
2047                 target-module@a8000 {                   /* 0x480a8000, ap 59 1a.0 */
2048                         compatible = "ti,sysc";
2049                         status = "disabled";
2050                         #address-cells = <1>;
2051                         #size-cells = <1>;
2052                         ranges = <0x0 0xa8000 0x4000>;
2053                 };
2054
2055                 target-module@ad000 {                   /* 0x480ad000, ap 61 20.0 */
2056                         compatible = "ti,sysc-omap4", "ti,sysc";
2057                         reg = <0xad000 0x4>,
2058                               <0xad010 0x4>;
2059                         reg-names = "rev", "sysc";
2060                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2061                                          SYSC_OMAP4_SOFTRESET)>;
2062                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2063                                         <SYSC_IDLE_NO>,
2064                                         <SYSC_IDLE_SMART>,
2065                                         <SYSC_IDLE_SMART_WKUP>;
2066                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2067                                         <SYSC_IDLE_NO>,
2068                                         <SYSC_IDLE_SMART>,
2069                                         <SYSC_IDLE_SMART_WKUP>;
2070                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2071                         clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2072                         clock-names = "fck";
2073                         #address-cells = <1>;
2074                         #size-cells = <1>;
2075                         ranges = <0x0 0xad000 0x1000>;
2076
2077                         mmc3: mmc@0 {
2078                                 compatible = "ti,dra7-sdhci";
2079                                 reg = <0x0 0x400>;
2080                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
2081                                 status = "disabled";
2082                                 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
2083                                 max-frequency = <64000000>;
2084                                 /* SDMA is not supported */
2085                                 sdhci-caps-mask = <0x0 0x400000>;
2086                         };
2087                 };
2088
2089                 target-module@b2000 {                   /* 0x480b2000, ap 37 52.0 */
2090                         compatible = "ti,sysc-omap2", "ti,sysc";
2091                         reg = <0xb2000 0x4>,
2092                               <0xb2014 0x4>,
2093                               <0xb2018 0x4>;
2094                         reg-names = "rev", "sysc", "syss";
2095                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2096                                          SYSC_OMAP2_AUTOIDLE)>;
2097                         ti,syss-mask = <1>;
2098                         ti,no-reset-on-init;
2099                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2100                         clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2101                         clock-names = "fck";
2102                         #address-cells = <1>;
2103                         #size-cells = <1>;
2104                         ranges = <0x0 0xb2000 0x1000>;
2105
2106                         hdqw1w: 1w@0 {
2107                                 compatible = "ti,omap3-1w";
2108                                 reg = <0x0 0x1000>;
2109                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2110                         };
2111                 };
2112
2113                 target-module@b4000 {                   /* 0x480b4000, ap 65 40.0 */
2114                         compatible = "ti,sysc-omap4", "ti,sysc";
2115                         reg = <0xb4000 0x4>,
2116                               <0xb4010 0x4>;
2117                         reg-names = "rev", "sysc";
2118                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2119                                          SYSC_OMAP4_SOFTRESET)>;
2120                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2121                                         <SYSC_IDLE_NO>,
2122                                         <SYSC_IDLE_SMART>,
2123                                         <SYSC_IDLE_SMART_WKUP>;
2124                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2125                                         <SYSC_IDLE_NO>,
2126                                         <SYSC_IDLE_SMART>,
2127                                         <SYSC_IDLE_SMART_WKUP>;
2128                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2129                         clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2130                         clock-names = "fck";
2131                         #address-cells = <1>;
2132                         #size-cells = <1>;
2133                         ranges = <0x0 0xb4000 0x1000>;
2134
2135                         mmc2: mmc@0 {
2136                                 compatible = "ti,dra7-sdhci";
2137                                 reg = <0x0 0x400>;
2138                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2139                                 status = "disabled";
2140                                 max-frequency = <192000000>;
2141                                 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
2142                                 sdhci-caps-mask = <0x7 0x0>;
2143                                 mmc-hs200-1_8v;
2144                                 mmc-ddr-1_8v;
2145                                 mmc-ddr-3_3v;
2146                         };
2147                 };
2148
2149                 target-module@b8000 {                   /* 0x480b8000, ap 67 48.0 */
2150                         compatible = "ti,sysc-omap4", "ti,sysc";
2151                         reg = <0xb8000 0x4>,
2152                               <0xb8010 0x4>;
2153                         reg-names = "rev", "sysc";
2154                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2155                                          SYSC_OMAP4_SOFTRESET)>;
2156                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2157                                         <SYSC_IDLE_NO>,
2158                                         <SYSC_IDLE_SMART>,
2159                                         <SYSC_IDLE_SMART_WKUP>;
2160                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2161                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2162                         clock-names = "fck";
2163                         #address-cells = <1>;
2164                         #size-cells = <1>;
2165                         ranges = <0x0 0xb8000 0x1000>;
2166
2167                         mcspi3: spi@0 {
2168                                 compatible = "ti,omap4-mcspi";
2169                                 reg = <0x0 0x200>;
2170                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2171                                 #address-cells = <1>;
2172                                 #size-cells = <0>;
2173                                 ti,spi-num-cs = <2>;
2174                                 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
2175                                 dma-names = "tx0", "rx0";
2176                                 status = "disabled";
2177                         };
2178                 };
2179
2180                 target-module@ba000 {                   /* 0x480ba000, ap 69 18.0 */
2181                         compatible = "ti,sysc-omap4", "ti,sysc";
2182                         reg = <0xba000 0x4>,
2183                               <0xba010 0x4>;
2184                         reg-names = "rev", "sysc";
2185                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2186                                          SYSC_OMAP4_SOFTRESET)>;
2187                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2188                                         <SYSC_IDLE_NO>,
2189                                         <SYSC_IDLE_SMART>,
2190                                         <SYSC_IDLE_SMART_WKUP>;
2191                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2192                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2193                         clock-names = "fck";
2194                         #address-cells = <1>;
2195                         #size-cells = <1>;
2196                         ranges = <0x0 0xba000 0x1000>;
2197
2198                         mcspi4: spi@0 {
2199                                 compatible = "ti,omap4-mcspi";
2200                                 reg = <0x0 0x200>;
2201                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
2202                                 #address-cells = <1>;
2203                                 #size-cells = <0>;
2204                                 ti,spi-num-cs = <1>;
2205                                 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
2206                                 dma-names = "tx0", "rx0";
2207                                 status = "disabled";
2208                         };
2209                 };
2210
2211                 target-module@d1000 {                   /* 0x480d1000, ap 71 28.0 */
2212                         compatible = "ti,sysc-omap4", "ti,sysc";
2213                         reg = <0xd1000 0x4>,
2214                               <0xd1010 0x4>;
2215                         reg-names = "rev", "sysc";
2216                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2217                                          SYSC_OMAP4_SOFTRESET)>;
2218                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2219                                         <SYSC_IDLE_NO>,
2220                                         <SYSC_IDLE_SMART>,
2221                                         <SYSC_IDLE_SMART_WKUP>;
2222                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2223                                         <SYSC_IDLE_NO>,
2224                                         <SYSC_IDLE_SMART>,
2225                                         <SYSC_IDLE_SMART_WKUP>;
2226                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2227                         clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2228                         clock-names = "fck";
2229                         #address-cells = <1>;
2230                         #size-cells = <1>;
2231                         ranges = <0x0 0xd1000 0x1000>;
2232
2233                         mmc4: mmc@0 {
2234                                 compatible = "ti,dra7-sdhci";
2235                                 reg = <0x0 0x400>;
2236                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2237                                 status = "disabled";
2238                                 max-frequency = <192000000>;
2239                                 /* SDMA is not supported */
2240                                 sdhci-caps-mask = <0x0 0x400000>;
2241                         };
2242                 };
2243
2244                 target-module@d5000 {                   /* 0x480d5000, ap 73 30.0 */
2245                         compatible = "ti,sysc";
2246                         status = "disabled";
2247                         #address-cells = <1>;
2248                         #size-cells = <1>;
2249                         ranges = <0x0 0xd5000 0x1000>;
2250                 };
2251         };
2252
2253         segment@200000 {                                        /* 0x48200000 */
2254                 compatible = "simple-bus";
2255                 #address-cells = <1>;
2256                 #size-cells = <1>;
2257         };
2258 };
2259
2260 &l4_per2 {                                              /* 0x48400000 */
2261         compatible = "ti,dra7-l4-per2", "simple-bus";
2262         reg = <0x48400000 0x800>,
2263               <0x48400800 0x800>,
2264               <0x48401000 0x400>,
2265               <0x48401400 0x400>,
2266               <0x48401800 0x400>;
2267         reg-names = "ap", "la", "ia0", "ia1", "ia2";
2268         #address-cells = <1>;
2269         #size-cells = <1>;
2270         ranges = <0x00000000 0x48400000 0x400000>,      /* segment 0 */
2271                  <0x45800000 0x45800000 0x400000>,      /* L3 data port */
2272                  <0x45c00000 0x45c00000 0x400000>,      /* L3 data port */
2273                  <0x46000000 0x46000000 0x400000>,      /* L3 data port */
2274                  <0x48436000 0x48436000 0x400000>,      /* L3 data port */
2275                  <0x4843a000 0x4843a000 0x400000>,      /* L3 data port */
2276                  <0x4844c000 0x4844c000 0x400000>,      /* L3 data port */
2277                  <0x48450000 0x48450000 0x400000>,      /* L3 data port */
2278                  <0x48454000 0x48454000 0x400000>;      /* L3 data port */
2279
2280         segment@0 {                                     /* 0x48400000 */
2281                 compatible = "simple-bus";
2282                 #address-cells = <1>;
2283                 #size-cells = <1>;
2284                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
2285                          <0x00001000 0x00001000 0x000400>,      /* ap 1 */
2286                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
2287                          <0x00084000 0x00084000 0x004000>,      /* ap 3 */
2288                          <0x00001400 0x00001400 0x000400>,      /* ap 4 */
2289                          <0x00001800 0x00001800 0x000400>,      /* ap 5 */
2290                          <0x00088000 0x00088000 0x001000>,      /* ap 6 */
2291                          <0x0002c000 0x0002c000 0x001000>,      /* ap 7 */
2292                          <0x0002d000 0x0002d000 0x001000>,      /* ap 8 */
2293                          <0x00060000 0x00060000 0x002000>,      /* ap 9 */
2294                          <0x00062000 0x00062000 0x001000>,      /* ap 10 */
2295                          <0x00064000 0x00064000 0x002000>,      /* ap 11 */
2296                          <0x00066000 0x00066000 0x001000>,      /* ap 12 */
2297                          <0x00068000 0x00068000 0x002000>,      /* ap 13 */
2298                          <0x0006a000 0x0006a000 0x001000>,      /* ap 14 */
2299                          <0x0006c000 0x0006c000 0x002000>,      /* ap 15 */
2300                          <0x0006e000 0x0006e000 0x001000>,      /* ap 16 */
2301                          <0x00036000 0x00036000 0x001000>,      /* ap 17 */
2302                          <0x00037000 0x00037000 0x001000>,      /* ap 18 */
2303                          <0x00070000 0x00070000 0x002000>,      /* ap 19 */
2304                          <0x00072000 0x00072000 0x001000>,      /* ap 20 */
2305                          <0x0003a000 0x0003a000 0x001000>,      /* ap 21 */
2306                          <0x0003b000 0x0003b000 0x001000>,      /* ap 22 */
2307                          <0x0003c000 0x0003c000 0x001000>,      /* ap 23 */
2308                          <0x0003d000 0x0003d000 0x001000>,      /* ap 24 */
2309                          <0x0003e000 0x0003e000 0x001000>,      /* ap 25 */
2310                          <0x0003f000 0x0003f000 0x001000>,      /* ap 26 */
2311                          <0x00040000 0x00040000 0x001000>,      /* ap 27 */
2312                          <0x00041000 0x00041000 0x001000>,      /* ap 28 */
2313                          <0x00042000 0x00042000 0x001000>,      /* ap 29 */
2314                          <0x00043000 0x00043000 0x001000>,      /* ap 30 */
2315                          <0x00080000 0x00080000 0x002000>,      /* ap 31 */
2316                          <0x00082000 0x00082000 0x001000>,      /* ap 32 */
2317                          <0x0004a000 0x0004a000 0x001000>,      /* ap 33 */
2318                          <0x0004b000 0x0004b000 0x001000>,      /* ap 34 */
2319                          <0x00074000 0x00074000 0x002000>,      /* ap 35 */
2320                          <0x00076000 0x00076000 0x001000>,      /* ap 36 */
2321                          <0x00050000 0x00050000 0x001000>,      /* ap 37 */
2322                          <0x00051000 0x00051000 0x001000>,      /* ap 38 */
2323                          <0x00078000 0x00078000 0x002000>,      /* ap 39 */
2324                          <0x0007a000 0x0007a000 0x001000>,      /* ap 40 */
2325                          <0x00054000 0x00054000 0x001000>,      /* ap 41 */
2326                          <0x00055000 0x00055000 0x001000>,      /* ap 42 */
2327                          <0x0007c000 0x0007c000 0x002000>,      /* ap 43 */
2328                          <0x0007e000 0x0007e000 0x001000>,      /* ap 44 */
2329                          <0x0004c000 0x0004c000 0x001000>,      /* ap 45 */
2330                          <0x0004d000 0x0004d000 0x001000>,      /* ap 46 */
2331                          <0x00020000 0x00020000 0x001000>,      /* ap 47 */
2332                          <0x00021000 0x00021000 0x001000>,      /* ap 48 */
2333                          <0x00022000 0x00022000 0x001000>,      /* ap 49 */
2334                          <0x00023000 0x00023000 0x001000>,      /* ap 50 */
2335                          <0x00024000 0x00024000 0x001000>,      /* ap 51 */
2336                          <0x00025000 0x00025000 0x001000>,      /* ap 52 */
2337                          <0x00046000 0x00046000 0x001000>,      /* ap 53 */
2338                          <0x00047000 0x00047000 0x001000>,      /* ap 54 */
2339                          <0x00048000 0x00048000 0x001000>,      /* ap 55 */
2340                          <0x00049000 0x00049000 0x001000>,      /* ap 56 */
2341                          <0x00058000 0x00058000 0x002000>,      /* ap 57 */
2342                          <0x0005a000 0x0005a000 0x001000>,      /* ap 58 */
2343                          <0x0005b000 0x0005b000 0x001000>,      /* ap 59 */
2344                          <0x0005c000 0x0005c000 0x001000>,      /* ap 60 */
2345                          <0x0005d000 0x0005d000 0x001000>,      /* ap 61 */
2346                          <0x0005e000 0x0005e000 0x001000>,      /* ap 62 */
2347                          <0x45800000 0x45800000 0x400000>,      /* L3 data port */
2348                          <0x45c00000 0x45c00000 0x400000>,      /* L3 data port */
2349                          <0x46000000 0x46000000 0x400000>,      /* L3 data port */
2350                          <0x48436000 0x48436000 0x400000>,      /* L3 data port */
2351                          <0x4843a000 0x4843a000 0x400000>,      /* L3 data port */
2352                          <0x4844c000 0x4844c000 0x400000>,      /* L3 data port */
2353                          <0x48450000 0x48450000 0x400000>,      /* L3 data port */
2354                          <0x48454000 0x48454000 0x400000>;      /* L3 data port */
2355
2356                 target-module@20000 {                   /* 0x48420000, ap 47 02.0 */
2357                         compatible = "ti,sysc-omap2", "ti,sysc";
2358                         reg = <0x20050 0x4>,
2359                               <0x20054 0x4>,
2360                               <0x20058 0x4>;
2361                         reg-names = "rev", "sysc", "syss";
2362                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2363                                          SYSC_OMAP2_SOFTRESET |
2364                                          SYSC_OMAP2_AUTOIDLE)>;
2365                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2366                                         <SYSC_IDLE_NO>,
2367                                         <SYSC_IDLE_SMART>,
2368                                         <SYSC_IDLE_SMART_WKUP>;
2369                         ti,syss-mask = <1>;
2370                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2371                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2372                         clock-names = "fck";
2373                         #address-cells = <1>;
2374                         #size-cells = <1>;
2375                         ranges = <0x0 0x20000 0x1000>;
2376
2377                         uart7: serial@0 {
2378                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
2379                                 reg = <0x0 0x100>;
2380                                 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
2381                                 clock-frequency = <48000000>;
2382                                 status = "disabled";
2383                         };
2384                 };
2385
2386                 target-module@22000 {                   /* 0x48422000, ap 49 0a.0 */
2387                         compatible = "ti,sysc-omap2", "ti,sysc";
2388                         reg = <0x22050 0x4>,
2389                               <0x22054 0x4>,
2390                               <0x22058 0x4>;
2391                         reg-names = "rev", "sysc", "syss";
2392                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2393                                          SYSC_OMAP2_SOFTRESET |
2394                                          SYSC_OMAP2_AUTOIDLE)>;
2395                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2396                                         <SYSC_IDLE_NO>,
2397                                         <SYSC_IDLE_SMART>,
2398                                         <SYSC_IDLE_SMART_WKUP>;
2399                         ti,syss-mask = <1>;
2400                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2401                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2402                         clock-names = "fck";
2403                         #address-cells = <1>;
2404                         #size-cells = <1>;
2405                         ranges = <0x0 0x22000 0x1000>;
2406
2407                         uart8: serial@0 {
2408                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
2409                                 reg = <0x0 0x100>;
2410                                 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
2411                                 clock-frequency = <48000000>;
2412                                 status = "disabled";
2413                         };
2414                 };
2415
2416                 target-module@24000 {                   /* 0x48424000, ap 51 12.0 */
2417                         compatible = "ti,sysc-omap2", "ti,sysc";
2418                         reg = <0x24050 0x4>,
2419                               <0x24054 0x4>,
2420                               <0x24058 0x4>;
2421                         reg-names = "rev", "sysc", "syss";
2422                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2423                                          SYSC_OMAP2_SOFTRESET |
2424                                          SYSC_OMAP2_AUTOIDLE)>;
2425                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2426                                         <SYSC_IDLE_NO>,
2427                                         <SYSC_IDLE_SMART>,
2428                                         <SYSC_IDLE_SMART_WKUP>;
2429                         ti,syss-mask = <1>;
2430                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2431                         clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2432                         clock-names = "fck";
2433                         #address-cells = <1>;
2434                         #size-cells = <1>;
2435                         ranges = <0x0 0x24000 0x1000>;
2436
2437                         uart9: serial@0 {
2438                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
2439                                 reg = <0x0 0x100>;
2440                                 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
2441                                 clock-frequency = <48000000>;
2442                                 status = "disabled";
2443                         };
2444                 };
2445
2446                 target-module@2c000 {                   /* 0x4842c000, ap 7 18.0 */
2447                         compatible = "ti,sysc";
2448                         status = "disabled";
2449                         #address-cells = <1>;
2450                         #size-cells = <1>;
2451                         ranges = <0x0 0x2c000 0x1000>;
2452                 };
2453
2454                 target-module@36000 {                   /* 0x48436000, ap 17 06.0 */
2455                         compatible = "ti,sysc";
2456                         status = "disabled";
2457                         #address-cells = <1>;
2458                         #size-cells = <1>;
2459                         ranges = <0x0 0x36000 0x1000>;
2460                 };
2461
2462                 target-module@3a000 {                   /* 0x4843a000, ap 21 3e.0 */
2463                         compatible = "ti,sysc";
2464                         status = "disabled";
2465                         #address-cells = <1>;
2466                         #size-cells = <1>;
2467                         ranges = <0x0 0x3a000 0x1000>;
2468                 };
2469
2470                 atl_tm: target-module@3c000 {           /* 0x4843c000, ap 23 08.0 */
2471                         compatible = "ti,sysc-omap4", "ti,sysc";
2472                         reg = <0x3c000 0x4>;
2473                         reg-names = "rev";
2474                         clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
2475                         clock-names = "fck";
2476                         #address-cells = <1>;
2477                         #size-cells = <1>;
2478                         ranges = <0x0 0x3c000 0x1000>;
2479
2480                         atl: atl@0 {
2481                                 compatible = "ti,dra7-atl";
2482                                 reg = <0x0 0x3ff>;
2483                                 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
2484                                                      <&atl_clkin2_ck>, <&atl_clkin3_ck>;
2485                                 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
2486                                 clock-names = "fck";
2487                                 status = "disabled";
2488                         };
2489                 };
2490
2491                 target-module@3e000 {                   /* 0x4843e000, ap 25 30.0 */
2492                         compatible = "ti,sysc-omap4", "ti,sysc";
2493                         ti,hwmods = "epwmss0";
2494                         reg = <0x3e000 0x4>,
2495                               <0x3e004 0x4>;
2496                         reg-names = "rev", "sysc";
2497                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2498                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2499                                         <SYSC_IDLE_NO>,
2500                                         <SYSC_IDLE_SMART>;
2501                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2502                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2503                         clock-names = "fck";
2504                         #address-cells = <1>;
2505                         #size-cells = <1>;
2506                         ranges = <0x0 0x3e000 0x1000>;
2507
2508                         epwmss0: epwmss@0 {
2509                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2510                                 reg = <0x0 0x30>;
2511                                 #address-cells = <1>;
2512                                 #size-cells = <1>;
2513                                 status = "disabled";
2514                                 ranges = <0 0 0x1000>;
2515
2516                                 ecap0: ecap@100 {
2517                                         compatible = "ti,dra746-ecap",
2518                                                      "ti,am3352-ecap";
2519                                         #pwm-cells = <3>;
2520                                         reg = <0x100 0x80>;
2521                                         clocks = <&l4_root_clk_div>;
2522                                         clock-names = "fck";
2523                                         status = "disabled";
2524                                 };
2525
2526                                 ehrpwm0: pwm@200 {
2527                                         compatible = "ti,dra746-ehrpwm",
2528                                                      "ti,am3352-ehrpwm";
2529                                         #pwm-cells = <3>;
2530                                         reg = <0x200 0x80>;
2531                                         clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
2532                                         clock-names = "tbclk", "fck";
2533                                         status = "disabled";
2534                                 };
2535                         };
2536                 };
2537
2538                 target-module@40000 {                   /* 0x48440000, ap 27 38.0 */
2539                         compatible = "ti,sysc-omap4", "ti,sysc";
2540                         ti,hwmods = "epwmss1";
2541                         reg = <0x40000 0x4>,
2542                               <0x40004 0x4>;
2543                         reg-names = "rev", "sysc";
2544                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2545                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2546                                         <SYSC_IDLE_NO>,
2547                                         <SYSC_IDLE_SMART>;
2548                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2549                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2550                         clock-names = "fck";
2551                         #address-cells = <1>;
2552                         #size-cells = <1>;
2553                         ranges = <0x0 0x40000 0x1000>;
2554
2555                         epwmss1: epwmss@0 {
2556                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2557                                 reg = <0x0 0x30>;
2558                                 #address-cells = <1>;
2559                                 #size-cells = <1>;
2560                                 status = "disabled";
2561                                 ranges = <0 0 0x1000>;
2562
2563                                 ecap1: ecap@100 {
2564                                         compatible = "ti,dra746-ecap",
2565                                                      "ti,am3352-ecap";
2566                                         #pwm-cells = <3>;
2567                                         reg = <0x100 0x80>;
2568                                         clocks = <&l4_root_clk_div>;
2569                                         clock-names = "fck";
2570                                         status = "disabled";
2571                                 };
2572
2573                                 ehrpwm1: pwm@200 {
2574                                         compatible = "ti,dra746-ehrpwm",
2575                                                      "ti,am3352-ehrpwm";
2576                                         #pwm-cells = <3>;
2577                                         reg = <0x200 0x80>;
2578                                         clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
2579                                         clock-names = "tbclk", "fck";
2580                                         status = "disabled";
2581                                 };
2582                         };
2583                 };
2584
2585                 target-module@42000 {                   /* 0x48442000, ap 29 20.0 */
2586                         compatible = "ti,sysc-omap4", "ti,sysc";
2587                         ti,hwmods = "epwmss2";
2588                         reg = <0x42000 0x4>,
2589                               <0x42004 0x4>;
2590                         reg-names = "rev", "sysc";
2591                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2592                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2593                                         <SYSC_IDLE_NO>,
2594                                         <SYSC_IDLE_SMART>;
2595                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2596                         clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2597                         clock-names = "fck";
2598                         #address-cells = <1>;
2599                         #size-cells = <1>;
2600                         ranges = <0x0 0x42000 0x1000>;
2601
2602                         epwmss2: epwmss@0 {
2603                                 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2604                                 reg = <0x0 0x30>;
2605                                 #address-cells = <1>;
2606                                 #size-cells = <1>;
2607                                 status = "disabled";
2608                                 ranges = <0 0 0x1000>;
2609
2610                                 ecap2: ecap@100 {
2611                                         compatible = "ti,dra746-ecap",
2612                                                      "ti,am3352-ecap";
2613                                         #pwm-cells = <3>;
2614                                         reg = <0x100 0x80>;
2615                                         clocks = <&l4_root_clk_div>;
2616                                         clock-names = "fck";
2617                                         status = "disabled";
2618                                 };
2619
2620                                 ehrpwm2: pwm@200 {
2621                                         compatible = "ti,dra746-ehrpwm",
2622                                                      "ti,am3352-ehrpwm";
2623                                         #pwm-cells = <3>;
2624                                         reg = <0x200 0x80>;
2625                                         clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2626                                         clock-names = "tbclk", "fck";
2627                                         status = "disabled";
2628                                 };
2629                         };
2630                 };
2631
2632                 target-module@46000 {                   /* 0x48446000, ap 53 40.0 */
2633                         compatible = "ti,sysc";
2634                         status = "disabled";
2635                         #address-cells = <1>;
2636                         #size-cells = <1>;
2637                         ranges = <0x0 0x46000 0x1000>;
2638                 };
2639
2640                 target-module@48000 {                   /* 0x48448000, ap 55 48.0 */
2641                         compatible = "ti,sysc";
2642                         status = "disabled";
2643                         #address-cells = <1>;
2644                         #size-cells = <1>;
2645                         ranges = <0x0 0x48000 0x1000>;
2646                 };
2647
2648                 target-module@4a000 {                   /* 0x4844a000, ap 33 1a.0 */
2649                         compatible = "ti,sysc";
2650                         status = "disabled";
2651                         #address-cells = <1>;
2652                         #size-cells = <1>;
2653                         ranges = <0x0 0x4a000 0x1000>;
2654                 };
2655
2656                 target-module@4c000 {                   /* 0x4844c000, ap 45 1c.0 */
2657                         compatible = "ti,sysc";
2658                         status = "disabled";
2659                         #address-cells = <1>;
2660                         #size-cells = <1>;
2661                         ranges = <0x0 0x4c000 0x1000>;
2662                 };
2663
2664                 target-module@50000 {                   /* 0x48450000, ap 37 24.0 */
2665                         compatible = "ti,sysc";
2666                         status = "disabled";
2667                         #address-cells = <1>;
2668                         #size-cells = <1>;
2669                         ranges = <0x0 0x50000 0x1000>;
2670                 };
2671
2672                 target-module@54000 {                   /* 0x48454000, ap 41 2c.0 */
2673                         compatible = "ti,sysc";
2674                         status = "disabled";
2675                         #address-cells = <1>;
2676                         #size-cells = <1>;
2677                         ranges = <0x0 0x54000 0x1000>;
2678                 };
2679
2680                 target-module@58000 {                   /* 0x48458000, ap 57 28.0 */
2681                         compatible = "ti,sysc";
2682                         status = "disabled";
2683                         #address-cells = <1>;
2684                         #size-cells = <1>;
2685                         ranges = <0x0 0x58000 0x2000>;
2686                 };
2687
2688                 target-module@5b000 {                   /* 0x4845b000, ap 59 46.0 */
2689                         compatible = "ti,sysc";
2690                         status = "disabled";
2691                         #address-cells = <1>;
2692                         #size-cells = <1>;
2693                         ranges = <0x0 0x5b000 0x1000>;
2694                 };
2695
2696                 target-module@5d000 {                   /* 0x4845d000, ap 61 22.0 */
2697                         compatible = "ti,sysc";
2698                         status = "disabled";
2699                         #address-cells = <1>;
2700                         #size-cells = <1>;
2701                         ranges = <0x0 0x5d000 0x1000>;
2702                 };
2703
2704                 target-module@60000 {                   /* 0x48460000, ap 9 0e.0 */
2705                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2706                         reg = <0x60000 0x4>,
2707                               <0x60004 0x4>;
2708                         reg-names = "rev", "sysc";
2709                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2710                                         <SYSC_IDLE_NO>,
2711                                         <SYSC_IDLE_SMART>;
2712                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
2713                         clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2714                                  <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2715                                  <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2716                         clock-names = "fck", "ahclkx", "ahclkr";
2717                         #address-cells = <1>;
2718                         #size-cells = <1>;
2719                         ranges = <0x0 0x60000 0x2000>,
2720                                  <0x45800000 0x45800000 0x400000>;
2721
2722                         mcasp1: mcasp@0 {
2723                                 compatible = "ti,dra7-mcasp-audio";
2724                                 reg = <0x0 0x2000>,
2725                                       <0x45800000 0x1000>;      /* L3 data port */
2726                                 reg-names = "mpu","dat";
2727                                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2728                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2729                                 interrupt-names = "tx", "rx";
2730                                 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
2731                                 dma-names = "tx", "rx";
2732                                 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2733                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2734                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2735                                 clock-names = "fck", "ahclkx", "ahclkr";
2736                                 status = "disabled";
2737                         };
2738                 };
2739
2740                 target-module@64000 {                   /* 0x48464000, ap 11 1e.0 */
2741                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2742                         reg = <0x64000 0x4>,
2743                               <0x64004 0x4>;
2744                         reg-names = "rev", "sysc";
2745                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2746                                         <SYSC_IDLE_NO>,
2747                                         <SYSC_IDLE_SMART>;
2748                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2749                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2750                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2751                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2752                         clock-names = "fck", "ahclkx", "ahclkr";
2753                         #address-cells = <1>;
2754                         #size-cells = <1>;
2755                         ranges = <0x0 0x64000 0x2000>,
2756                                  <0x45c00000 0x45c00000 0x400000>;
2757
2758                         mcasp2: mcasp@0 {
2759                                 compatible = "ti,dra7-mcasp-audio";
2760                                 reg = <0x0 0x2000>,
2761                                       <0x45c00000 0x1000>;      /* L3 data port */
2762                                 reg-names = "mpu","dat";
2763                                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2764                                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2765                                 interrupt-names = "tx", "rx";
2766                                 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
2767                                 dma-names = "tx", "rx";
2768                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2769                                          <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2770                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2771                                 clock-names = "fck", "ahclkx", "ahclkr";
2772                                 status = "disabled";
2773                         };
2774                 };
2775
2776                 target-module@68000 {                   /* 0x48468000, ap 13 26.0 */
2777                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2778                         reg = <0x68000 0x4>,
2779                               <0x68004 0x4>;
2780                         reg-names = "rev", "sysc";
2781                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2782                                         <SYSC_IDLE_NO>,
2783                                         <SYSC_IDLE_SMART>;
2784                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2785                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2786                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2787                         clock-names = "fck", "ahclkx";
2788                         #address-cells = <1>;
2789                         #size-cells = <1>;
2790                         ranges = <0x0 0x68000 0x2000>,
2791                                  <0x46000000 0x46000000 0x400000>;
2792
2793                         mcasp3: mcasp@0 {
2794                                 compatible = "ti,dra7-mcasp-audio";
2795                                 reg = <0x0 0x2000>,
2796                                       <0x46000000 0x1000>;      /* L3 data port */
2797                                 reg-names = "mpu","dat";
2798                                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
2799                                              <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2800                                 interrupt-names = "tx", "rx";
2801                                 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
2802                                 dma-names = "tx", "rx";
2803                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2804                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2805                                 clock-names = "fck", "ahclkx";
2806                                 status = "disabled";
2807                         };
2808                 };
2809
2810                 target-module@6c000 {                   /* 0x4846c000, ap 15 2e.0 */
2811                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2812                         reg = <0x6c000 0x4>,
2813                               <0x6c004 0x4>;
2814                         reg-names = "rev", "sysc";
2815                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2816                                         <SYSC_IDLE_NO>,
2817                                         <SYSC_IDLE_SMART>;
2818                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2819                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2820                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2821                         clock-names = "fck", "ahclkx";
2822                         #address-cells = <1>;
2823                         #size-cells = <1>;
2824                         ranges = <0x0 0x6c000 0x2000>,
2825                                  <0x48436000 0x48436000 0x400000>;
2826
2827                         mcasp4: mcasp@0 {
2828                                 compatible = "ti,dra7-mcasp-audio";
2829                                 reg = <0x0 0x2000>,
2830                                       <0x48436000 0x1000>;      /* L3 data port */
2831                                 reg-names = "mpu","dat";
2832                                 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
2833                                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
2834                                 interrupt-names = "tx", "rx";
2835                                 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
2836                                 dma-names = "tx", "rx";
2837                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2838                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2839                                 clock-names = "fck", "ahclkx";
2840                                 status = "disabled";
2841                         };
2842                 };
2843
2844                 target-module@70000 {                   /* 0x48470000, ap 19 36.0 */
2845                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2846                         reg = <0x70000 0x4>,
2847                               <0x70004 0x4>;
2848                         reg-names = "rev", "sysc";
2849                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2850                                         <SYSC_IDLE_NO>,
2851                                         <SYSC_IDLE_SMART>;
2852                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2853                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2854                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2855                         clock-names = "fck", "ahclkx";
2856                         #address-cells = <1>;
2857                         #size-cells = <1>;
2858                         ranges = <0x0 0x70000 0x2000>,
2859                                  <0x4843a000 0x4843a000 0x400000>;
2860
2861                         mcasp5: mcasp@0 {
2862                                 compatible = "ti,dra7-mcasp-audio";
2863                                 reg = <0x0 0x2000>,
2864                                       <0x4843a000 0x1000>;      /* L3 data port */
2865                                 reg-names = "mpu","dat";
2866                                 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
2867                                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
2868                                 interrupt-names = "tx", "rx";
2869                                 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
2870                                 dma-names = "tx", "rx";
2871                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2872                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2873                                 clock-names = "fck", "ahclkx";
2874                                 status = "disabled";
2875                         };
2876                 };
2877
2878                 target-module@74000 {                   /* 0x48474000, ap 35 14.0 */
2879                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2880                         reg = <0x74000 0x4>,
2881                               <0x74004 0x4>;
2882                         reg-names = "rev", "sysc";
2883                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2884                                         <SYSC_IDLE_NO>,
2885                                         <SYSC_IDLE_SMART>;
2886                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2887                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2888                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2889                         clock-names = "fck", "ahclkx";
2890                         #address-cells = <1>;
2891                         #size-cells = <1>;
2892                         ranges = <0x0 0x74000 0x2000>,
2893                                  <0x4844c000 0x4844c000 0x400000>;
2894
2895                         mcasp6: mcasp@0 {
2896                                 compatible = "ti,dra7-mcasp-audio";
2897                                 reg = <0x0 0x2000>,
2898                                       <0x4844c000 0x1000>;      /* L3 data port */
2899                                 reg-names = "mpu","dat";
2900                                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
2901                                              <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
2902                                 interrupt-names = "tx", "rx";
2903                                 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
2904                                 dma-names = "tx", "rx";
2905                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2906                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2907                                 clock-names = "fck", "ahclkx";
2908                                 status = "disabled";
2909                         };
2910                 };
2911
2912                 target-module@78000 {                   /* 0x48478000, ap 39 0c.0 */
2913                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2914                         reg = <0x78000 0x4>,
2915                               <0x78004 0x4>;
2916                         reg-names = "rev", "sysc";
2917                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2918                                         <SYSC_IDLE_NO>,
2919                                         <SYSC_IDLE_SMART>;
2920                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2921                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2922                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2923                         clock-names = "fck", "ahclkx";
2924                         #address-cells = <1>;
2925                         #size-cells = <1>;
2926                         ranges = <0x0 0x78000 0x2000>,
2927                                  <0x48450000 0x48450000 0x400000>;
2928
2929                         mcasp7: mcasp@0 {
2930                                 compatible = "ti,dra7-mcasp-audio";
2931                                 reg = <0x0 0x2000>,
2932                                       <0x48450000 0x1000>;      /* L3 data port */
2933                                 reg-names = "mpu","dat";
2934                                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
2935                                              <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2936                                 interrupt-names = "tx", "rx";
2937                                 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
2938                                 dma-names = "tx", "rx";
2939                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2940                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2941                                 clock-names = "fck", "ahclkx";
2942                                 status = "disabled";
2943                         };
2944                 };
2945
2946                 target-module@7c000 {                   /* 0x4847c000, ap 43 04.0 */
2947                         compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2948                         reg = <0x7c000 0x4>,
2949                               <0x7c004 0x4>;
2950                         reg-names = "rev", "sysc";
2951                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2952                                         <SYSC_IDLE_NO>,
2953                                         <SYSC_IDLE_SMART>;
2954                         /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2955                         clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2956                                  <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2957                         clock-names = "fck", "ahclkx";
2958                         #address-cells = <1>;
2959                         #size-cells = <1>;
2960                         ranges = <0x0 0x7c000 0x2000>,
2961                                  <0x48454000 0x48454000 0x400000>;
2962
2963                         mcasp8: mcasp@0 {
2964                                 compatible = "ti,dra7-mcasp-audio";
2965                                 reg = <0x0 0x2000>,
2966                                       <0x48454000 0x1000>;      /* L3 data port */
2967                                 reg-names = "mpu","dat";
2968                                 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2969                                              <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2970                                 interrupt-names = "tx", "rx";
2971                                 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
2972                                 dma-names = "tx", "rx";
2973                                 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2974                                          <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2975                                 clock-names = "fck", "ahclkx";
2976                                 status = "disabled";
2977                         };
2978                 };
2979
2980                 target-module@80000 {                   /* 0x48480000, ap 31 16.0 */
2981                         compatible = "ti,sysc-omap4", "ti,sysc";
2982                         reg = <0x80020 0x4>;
2983                         reg-names = "rev";
2984                         clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
2985                         clock-names = "fck";
2986                         #address-cells = <1>;
2987                         #size-cells = <1>;
2988                         ranges = <0x0 0x80000 0x2000>;
2989
2990                         dcan2: can@0 {
2991                                 compatible = "ti,dra7-d_can";
2992                                 reg = <0x0 0x2000>;
2993                                 syscon-raminit = <&scm_conf 0x558 1>;
2994                                 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
2995                                 clocks = <&sys_clkin1>;
2996                                 status = "disabled";
2997                         };
2998                 };
2999
3000                 target-module@84000 {                   /* 0x48484000, ap 3 10.0 */
3001                         compatible = "ti,sysc-omap4-simple", "ti,sysc";
3002                         reg = <0x85200 0x4>,
3003                               <0x85208 0x4>,
3004                               <0x85204 0x4>;
3005                         reg-names = "rev", "sysc", "syss";
3006                         ti,sysc-mask = <0>;
3007                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
3008                                         <SYSC_IDLE_NO>;
3009                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3010                                         <SYSC_IDLE_NO>;
3011                         ti,syss-mask = <1>;
3012                         clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3013                         clock-names = "fck";
3014                         #address-cells = <1>;
3015                         #size-cells = <1>;
3016                         ranges = <0x0 0x84000 0x4000>;
3017                         /*
3018                          * Do not allow gating of cpsw clock as workaround
3019                          * for errata i877. Keeping internal clock disabled
3020                          * causes the device switching characteristics
3021                          * to degrade over time and eventually fail to meet
3022                          * the data manual delay time/skew specs.
3023                          */
3024                         ti,no-idle;
3025
3026                         mac: ethernet@0 {
3027                                 compatible = "ti,dra7-cpsw","ti,cpsw";
3028                                 clocks = <&gmac_main_clk>, <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3029                                 clock-names = "fck", "cpts";
3030                                 cpdma_channels = <8>;
3031                                 ale_entries = <1024>;
3032                                 bd_ram_size = <0x2000>;
3033                                 mac_control = <0x20>;
3034                                 slaves = <2>;
3035                                 active_slave = <0>;
3036                                 cpts_clock_mult = <0x784CFE14>;
3037                                 cpts_clock_shift = <29>;
3038                                 reg = <0x0 0x1000
3039                                        0x1200 0x2e00>;
3040                                 #address-cells = <1>;
3041                                 #size-cells = <1>;
3042
3043                                 /*
3044                                  * rx_thresh_pend
3045                                  * rx_pend
3046                                  * tx_pend
3047                                  * misc_pend
3048                                  */
3049                                 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3050                                              <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3051                                              <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3052                                              <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3053                                 ranges = <0 0 0x4000>;
3054                                 syscon = <&scm_conf>;
3055                                 status = "disabled";
3056
3057                                 davinci_mdio: mdio@1000 {
3058                                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3059                                         clocks = <&gmac_main_clk>;
3060                                         clock-names = "fck";
3061                                         #address-cells = <1>;
3062                                         #size-cells = <0>;
3063                                         bus_freq = <1000000>;
3064                                         reg = <0x1000 0x100>;
3065                                 };
3066
3067                                 cpsw_emac0: slave@200 {
3068                                         /* Filled in by U-Boot */
3069                                         mac-address = [ 00 00 00 00 00 00 ];
3070                                         phys = <&phy_gmii_sel 1>;
3071                                 };
3072
3073                                 cpsw_emac1: slave@300 {
3074                                         /* Filled in by U-Boot */
3075                                         mac-address = [ 00 00 00 00 00 00 ];
3076                                         phys = <&phy_gmii_sel 2>;
3077                                 };
3078                         };
3079
3080                         mac_sw: switch@0 {
3081                                 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
3082                                 reg = <0x0 0x4000>;
3083                                 ranges = <0 0 0x4000>;
3084                                 clocks = <&gmac_main_clk>;
3085                                 clock-names = "fck";
3086                                 #address-cells = <1>;
3087                                 #size-cells = <1>;
3088                                 syscon = <&scm_conf>;
3089                                 status = "disabled";
3090
3091                                 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3092                                              <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3093                                              <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3094                                              <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3095                                 interrupt-names = "rx_thresh", "rx", "tx", "misc";
3096
3097                                 ethernet-ports {
3098                                         #address-cells = <1>;
3099                                         #size-cells = <0>;
3100
3101                                         cpsw_port1: port@1 {
3102                                                 reg = <1>;
3103                                                 label = "port1";
3104                                                 mac-address = [ 00 00 00 00 00 00 ];
3105                                                 phys = <&phy_gmii_sel 1>;
3106                                         };
3107
3108                                         cpsw_port2: port@2 {
3109                                                 reg = <2>;
3110                                                 label = "port2";
3111                                                 mac-address = [ 00 00 00 00 00 00 ];
3112                                                 phys = <&phy_gmii_sel 2>;
3113                                         };
3114                                 };
3115
3116                                 davinci_mdio_sw: mdio@1000 {
3117                                         compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3118                                         clocks = <&gmac_main_clk>;
3119                                         clock-names = "fck";
3120                                         #address-cells = <1>;
3121                                         #size-cells = <0>;
3122                                         bus_freq = <1000000>;
3123                                         reg = <0x1000 0x100>;
3124                                 };
3125
3126                                 cpts {
3127                                         clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3128                                         clock-names = "cpts";
3129                                 };
3130                         };
3131                 };
3132         };
3133 };
3134
3135 &l4_per3 {                                              /* 0x48800000 */
3136         compatible = "ti,dra7-l4-per3", "simple-bus";
3137         reg = <0x48800000 0x800>,
3138               <0x48800800 0x800>,
3139               <0x48801000 0x400>,
3140               <0x48801400 0x400>,
3141               <0x48801800 0x400>;
3142         reg-names = "ap", "la", "ia0", "ia1", "ia2";
3143         #address-cells = <1>;
3144         #size-cells = <1>;
3145         ranges = <0x00000000 0x48800000 0x200000>;      /* segment 0 */
3146
3147         segment@0 {                                     /* 0x48800000 */
3148                 compatible = "simple-bus";
3149                 #address-cells = <1>;
3150                 #size-cells = <1>;
3151                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
3152                          <0x00000800 0x00000800 0x000800>,      /* ap 1 */
3153                          <0x00001000 0x00001000 0x000400>,      /* ap 2 */
3154                          <0x00001400 0x00001400 0x000400>,      /* ap 3 */
3155                          <0x00001800 0x00001800 0x000400>,      /* ap 4 */
3156                          <0x00020000 0x00020000 0x001000>,      /* ap 5 */
3157                          <0x00021000 0x00021000 0x001000>,      /* ap 6 */
3158                          <0x00022000 0x00022000 0x001000>,      /* ap 7 */
3159                          <0x00023000 0x00023000 0x001000>,      /* ap 8 */
3160                          <0x00024000 0x00024000 0x001000>,      /* ap 9 */
3161                          <0x00025000 0x00025000 0x001000>,      /* ap 10 */
3162                          <0x00026000 0x00026000 0x001000>,      /* ap 11 */
3163                          <0x00027000 0x00027000 0x001000>,      /* ap 12 */
3164                          <0x00028000 0x00028000 0x001000>,      /* ap 13 */
3165                          <0x00029000 0x00029000 0x001000>,      /* ap 14 */
3166                          <0x0002a000 0x0002a000 0x001000>,      /* ap 15 */
3167                          <0x0002b000 0x0002b000 0x001000>,      /* ap 16 */
3168                          <0x0002c000 0x0002c000 0x001000>,      /* ap 17 */
3169                          <0x0002d000 0x0002d000 0x001000>,      /* ap 18 */
3170                          <0x0002e000 0x0002e000 0x001000>,      /* ap 19 */
3171                          <0x0002f000 0x0002f000 0x001000>,      /* ap 20 */
3172                          <0x00170000 0x00170000 0x010000>,      /* ap 21 */
3173                          <0x00180000 0x00180000 0x001000>,      /* ap 22 */
3174                          <0x00190000 0x00190000 0x010000>,      /* ap 23 */
3175                          <0x001a0000 0x001a0000 0x001000>,      /* ap 24 */
3176                          <0x001b0000 0x001b0000 0x010000>,      /* ap 25 */
3177                          <0x001c0000 0x001c0000 0x001000>,      /* ap 26 */
3178                          <0x001d0000 0x001d0000 0x010000>,      /* ap 27 */
3179                          <0x001e0000 0x001e0000 0x001000>,      /* ap 28 */
3180                          <0x00038000 0x00038000 0x001000>,      /* ap 29 */
3181                          <0x00039000 0x00039000 0x001000>,      /* ap 30 */
3182                          <0x0005c000 0x0005c000 0x001000>,      /* ap 31 */
3183                          <0x0005d000 0x0005d000 0x001000>,      /* ap 32 */
3184                          <0x0003a000 0x0003a000 0x001000>,      /* ap 33 */
3185                          <0x0003b000 0x0003b000 0x001000>,      /* ap 34 */
3186                          <0x0003c000 0x0003c000 0x001000>,      /* ap 35 */
3187                          <0x0003d000 0x0003d000 0x001000>,      /* ap 36 */
3188                          <0x0003e000 0x0003e000 0x001000>,      /* ap 37 */
3189                          <0x0003f000 0x0003f000 0x001000>,      /* ap 38 */
3190                          <0x00040000 0x00040000 0x001000>,      /* ap 39 */
3191                          <0x00041000 0x00041000 0x001000>,      /* ap 40 */
3192                          <0x00042000 0x00042000 0x001000>,      /* ap 41 */
3193                          <0x00043000 0x00043000 0x001000>,      /* ap 42 */
3194                          <0x00044000 0x00044000 0x001000>,      /* ap 43 */
3195                          <0x00045000 0x00045000 0x001000>,      /* ap 44 */
3196                          <0x00046000 0x00046000 0x001000>,      /* ap 45 */
3197                          <0x00047000 0x00047000 0x001000>,      /* ap 46 */
3198                          <0x00048000 0x00048000 0x001000>,      /* ap 47 */
3199                          <0x00049000 0x00049000 0x001000>,      /* ap 48 */
3200                          <0x0004a000 0x0004a000 0x001000>,      /* ap 49 */
3201                          <0x0004b000 0x0004b000 0x001000>,      /* ap 50 */
3202                          <0x0004c000 0x0004c000 0x001000>,      /* ap 51 */
3203                          <0x0004d000 0x0004d000 0x001000>,      /* ap 52 */
3204                          <0x0004e000 0x0004e000 0x001000>,      /* ap 53 */
3205                          <0x0004f000 0x0004f000 0x001000>,      /* ap 54 */
3206                          <0x00050000 0x00050000 0x001000>,      /* ap 55 */
3207                          <0x00051000 0x00051000 0x001000>,      /* ap 56 */
3208                          <0x00052000 0x00052000 0x001000>,      /* ap 57 */
3209                          <0x00053000 0x00053000 0x001000>,      /* ap 58 */
3210                          <0x00054000 0x00054000 0x001000>,      /* ap 59 */
3211                          <0x00055000 0x00055000 0x001000>,      /* ap 60 */
3212                          <0x00056000 0x00056000 0x001000>,      /* ap 61 */
3213                          <0x00057000 0x00057000 0x001000>,      /* ap 62 */
3214                          <0x00058000 0x00058000 0x001000>,      /* ap 63 */
3215                          <0x00059000 0x00059000 0x001000>,      /* ap 64 */
3216                          <0x0005a000 0x0005a000 0x001000>,      /* ap 65 */
3217                          <0x0005b000 0x0005b000 0x001000>,      /* ap 66 */
3218                          <0x00064000 0x00064000 0x001000>,      /* ap 67 */
3219                          <0x00065000 0x00065000 0x001000>,      /* ap 68 */
3220                          <0x0005e000 0x0005e000 0x001000>,      /* ap 69 */
3221                          <0x0005f000 0x0005f000 0x001000>,      /* ap 70 */
3222                          <0x00060000 0x00060000 0x001000>,      /* ap 71 */
3223                          <0x00061000 0x00061000 0x001000>,      /* ap 72 */
3224                          <0x00062000 0x00062000 0x001000>,      /* ap 73 */
3225                          <0x00063000 0x00063000 0x001000>,      /* ap 74 */
3226                          <0x00140000 0x00140000 0x020000>,      /* ap 75 */
3227                          <0x00160000 0x00160000 0x001000>,      /* ap 76 */
3228                          <0x00016000 0x00016000 0x001000>,      /* ap 77 */
3229                          <0x00017000 0x00017000 0x001000>,      /* ap 78 */
3230                          <0x000c0000 0x000c0000 0x020000>,      /* ap 79 */
3231                          <0x000e0000 0x000e0000 0x001000>,      /* ap 80 */
3232                          <0x00004000 0x00004000 0x001000>,      /* ap 81 */
3233                          <0x00005000 0x00005000 0x001000>,      /* ap 82 */
3234                          <0x00080000 0x00080000 0x020000>,      /* ap 83 */
3235                          <0x000a0000 0x000a0000 0x001000>,      /* ap 84 */
3236                          <0x00100000 0x00100000 0x020000>,      /* ap 85 */
3237                          <0x00120000 0x00120000 0x001000>,      /* ap 86 */
3238                          <0x00010000 0x00010000 0x001000>,      /* ap 87 */
3239                          <0x00011000 0x00011000 0x001000>,      /* ap 88 */
3240                          <0x0000a000 0x0000a000 0x001000>,      /* ap 89 */
3241                          <0x0000b000 0x0000b000 0x001000>,      /* ap 90 */
3242                          <0x0001c000 0x0001c000 0x001000>,      /* ap 91 */
3243                          <0x0001d000 0x0001d000 0x001000>,      /* ap 92 */
3244                          <0x0001e000 0x0001e000 0x001000>,      /* ap 93 */
3245                          <0x0001f000 0x0001f000 0x001000>,      /* ap 94 */
3246                          <0x00002000 0x00002000 0x001000>,      /* ap 95 */
3247                          <0x00003000 0x00003000 0x001000>;      /* ap 96 */
3248
3249                 target-module@2000 {                    /* 0x48802000, ap 95 7c.0 */
3250                         compatible = "ti,sysc-omap4", "ti,sysc";
3251                         reg = <0x2000 0x4>,
3252                               <0x2010 0x4>;
3253                         reg-names = "rev", "sysc";
3254                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3255                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3256                                         <SYSC_IDLE_NO>,
3257                                         <SYSC_IDLE_SMART>;
3258                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3259                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
3260                         clock-names = "fck";
3261                         #address-cells = <1>;
3262                         #size-cells = <1>;
3263                         ranges = <0x0 0x2000 0x1000>;
3264
3265                         mailbox13: mailbox@0 {
3266                                 compatible = "ti,omap4-mailbox";
3267                                 reg = <0x0 0x200>;
3268                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
3269                                              <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
3270                                              <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
3271                                              <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
3272                                 #mbox-cells = <1>;
3273                                 ti,mbox-num-users = <4>;
3274                                 ti,mbox-num-fifos = <12>;
3275                                 status = "disabled";
3276                         };
3277                 };
3278
3279                 target-module@4000 {                    /* 0x48804000, ap 81 20.0 */
3280                         compatible = "ti,sysc";
3281                         status = "disabled";
3282                         #address-cells = <1>;
3283                         #size-cells = <1>;
3284                         ranges = <0x0 0x4000 0x1000>;
3285                 };
3286
3287                 target-module@a000 {                    /* 0x4880a000, ap 89 18.0 */
3288                         compatible = "ti,sysc";
3289                         status = "disabled";
3290                         #address-cells = <1>;
3291                         #size-cells = <1>;
3292                         ranges = <0x0 0xa000 0x1000>;
3293                 };
3294
3295                 target-module@10000 {                   /* 0x48810000, ap 87 28.0 */
3296                         compatible = "ti,sysc";
3297                         status = "disabled";
3298                         #address-cells = <1>;
3299                         #size-cells = <1>;
3300                         ranges = <0x0 0x10000 0x1000>;
3301                 };
3302
3303                 target-module@16000 {                   /* 0x48816000, ap 77 1e.0 */
3304                         compatible = "ti,sysc";
3305                         status = "disabled";
3306                         #address-cells = <1>;
3307                         #size-cells = <1>;
3308                         ranges = <0x0 0x16000 0x1000>;
3309                 };
3310
3311                 target-module@1c000 {                   /* 0x4881c000, ap 91 1c.0 */
3312                         compatible = "ti,sysc";
3313                         status = "disabled";
3314                         #address-cells = <1>;
3315                         #size-cells = <1>;
3316                         ranges = <0x0 0x1c000 0x1000>;
3317                 };
3318
3319                 target-module@1e000 {                   /* 0x4881e000, ap 93 2c.0 */
3320                         compatible = "ti,sysc";
3321                         status = "disabled";
3322                         #address-cells = <1>;
3323                         #size-cells = <1>;
3324                         ranges = <0x0 0x1e000 0x1000>;
3325                 };
3326
3327                 target-module@20000 {                   /* 0x48820000, ap 5 08.0 */
3328                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3329                         ti,hwmods = "timer5";
3330                         reg = <0x20000 0x4>,
3331                               <0x20010 0x4>;
3332                         reg-names = "rev", "sysc";
3333                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3334                                          SYSC_OMAP4_SOFTRESET)>;
3335                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3336                                         <SYSC_IDLE_NO>,
3337                                         <SYSC_IDLE_SMART>,
3338                                         <SYSC_IDLE_SMART_WKUP>;
3339                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3340                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3341                         clock-names = "fck";
3342                         #address-cells = <1>;
3343                         #size-cells = <1>;
3344                         ranges = <0x0 0x20000 0x1000>;
3345
3346                         timer5: timer@0 {
3347                                 compatible = "ti,omap5430-timer";
3348                                 reg = <0x0 0x80>;
3349                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>;
3350                                 clock-names = "fck";
3351                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3352                         };
3353                 };
3354
3355                 target-module@22000 {                   /* 0x48822000, ap 7 24.0 */
3356                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3357                         ti,hwmods = "timer6";
3358                         reg = <0x22000 0x4>,
3359                               <0x22010 0x4>;
3360                         reg-names = "rev", "sysc";
3361                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3362                                          SYSC_OMAP4_SOFTRESET)>;
3363                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3364                                         <SYSC_IDLE_NO>,
3365                                         <SYSC_IDLE_SMART>,
3366                                         <SYSC_IDLE_SMART_WKUP>;
3367                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3368                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3369                         clock-names = "fck";
3370                         #address-cells = <1>;
3371                         #size-cells = <1>;
3372                         ranges = <0x0 0x22000 0x1000>;
3373
3374                         timer6: timer@0 {
3375                                 compatible = "ti,omap5430-timer";
3376                                 reg = <0x0 0x80>;
3377                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>;
3378                                 clock-names = "fck";
3379                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3380                         };
3381                 };
3382
3383                 target-module@24000 {                   /* 0x48824000, ap 9 26.0 */
3384                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3385                         ti,hwmods = "timer7";
3386                         reg = <0x24000 0x4>,
3387                               <0x24010 0x4>;
3388                         reg-names = "rev", "sysc";
3389                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3390                                          SYSC_OMAP4_SOFTRESET)>;
3391                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3392                                         <SYSC_IDLE_NO>,
3393                                         <SYSC_IDLE_SMART>,
3394                                         <SYSC_IDLE_SMART_WKUP>;
3395                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3396                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
3397                         clock-names = "fck";
3398                         #address-cells = <1>;
3399                         #size-cells = <1>;
3400                         ranges = <0x0 0x24000 0x1000>;
3401
3402                         timer7: timer@0 {
3403                                 compatible = "ti,omap5430-timer";
3404                                 reg = <0x0 0x80>;
3405                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>;
3406                                 clock-names = "fck";
3407                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3408                         };
3409                 };
3410
3411                 target-module@26000 {                   /* 0x48826000, ap 11 0c.0 */
3412                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3413                         ti,hwmods = "timer8";
3414                         reg = <0x26000 0x4>,
3415                               <0x26010 0x4>;
3416                         reg-names = "rev", "sysc";
3417                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3418                                          SYSC_OMAP4_SOFTRESET)>;
3419                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3420                                         <SYSC_IDLE_NO>,
3421                                         <SYSC_IDLE_SMART>,
3422                                         <SYSC_IDLE_SMART_WKUP>;
3423                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3424                         clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
3425                         clock-names = "fck";
3426                         #address-cells = <1>;
3427                         #size-cells = <1>;
3428                         ranges = <0x0 0x26000 0x1000>;
3429
3430                         timer8: timer@0 {
3431                                 compatible = "ti,omap5430-timer";
3432                                 reg = <0x0 0x80>;
3433                                 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>;
3434                                 clock-names = "fck";
3435                                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
3436                         };
3437                 };
3438
3439                 target-module@28000 {                   /* 0x48828000, ap 13 16.0 */
3440                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3441                         ti,hwmods = "timer13";
3442                         reg = <0x28000 0x4>,
3443                               <0x28010 0x4>;
3444                         reg-names = "rev", "sysc";
3445                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3446                                          SYSC_OMAP4_SOFTRESET)>;
3447                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3448                                         <SYSC_IDLE_NO>,
3449                                         <SYSC_IDLE_SMART>,
3450                                         <SYSC_IDLE_SMART_WKUP>;
3451                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3452                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
3453                         clock-names = "fck";
3454                         #address-cells = <1>;
3455                         #size-cells = <1>;
3456                         ranges = <0x0 0x28000 0x1000>;
3457
3458                         timer13: timer@0 {
3459                                 compatible = "ti,omap5430-timer";
3460                                 reg = <0x0 0x80>;
3461                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;
3462                                 clock-names = "fck";
3463                                 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
3464                         };
3465                 };
3466
3467                 target-module@2a000 {                   /* 0x4882a000, ap 15 10.0 */
3468                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3469                         ti,hwmods = "timer14";
3470                         reg = <0x2a000 0x4>,
3471                               <0x2a010 0x4>;
3472                         reg-names = "rev", "sysc";
3473                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3474                                          SYSC_OMAP4_SOFTRESET)>;
3475                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3476                                         <SYSC_IDLE_NO>,
3477                                         <SYSC_IDLE_SMART>,
3478                                         <SYSC_IDLE_SMART_WKUP>;
3479                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3480                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
3481                         clock-names = "fck";
3482                         #address-cells = <1>;
3483                         #size-cells = <1>;
3484                         ranges = <0x0 0x2a000 0x1000>;
3485
3486                         timer14: timer@0 {
3487                                 compatible = "ti,omap5430-timer";
3488                                 reg = <0x0 0x80>;
3489                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
3490                                 clock-names = "fck";
3491                                 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
3492                         };
3493                 };
3494
3495                 target-module@2c000 {                   /* 0x4882c000, ap 17 02.0 */
3496                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3497                         ti,hwmods = "timer15";
3498                         reg = <0x2c000 0x4>,
3499                               <0x2c010 0x4>;
3500                         reg-names = "rev", "sysc";
3501                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3502                                          SYSC_OMAP4_SOFTRESET)>;
3503                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3504                                         <SYSC_IDLE_NO>,
3505                                         <SYSC_IDLE_SMART>,
3506                                         <SYSC_IDLE_SMART_WKUP>;
3507                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3508                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
3509                         clock-names = "fck";
3510                         #address-cells = <1>;
3511                         #size-cells = <1>;
3512                         ranges = <0x0 0x2c000 0x1000>;
3513
3514                         timer15: timer@0 {
3515                                 compatible = "ti,omap5430-timer";
3516                                 reg = <0x0 0x80>;
3517                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
3518                                 clock-names = "fck";
3519                                 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
3520                         };
3521                 };
3522
3523                 target-module@2e000 {                   /* 0x4882e000, ap 19 14.0 */
3524                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
3525                         ti,hwmods = "timer16";
3526                         reg = <0x2e000 0x4>,
3527                               <0x2e010 0x4>;
3528                         reg-names = "rev", "sysc";
3529                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3530                                          SYSC_OMAP4_SOFTRESET)>;
3531                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3532                                         <SYSC_IDLE_NO>,
3533                                         <SYSC_IDLE_SMART>,
3534                                         <SYSC_IDLE_SMART_WKUP>;
3535                         /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3536                         clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
3537                         clock-names = "fck";
3538                         #address-cells = <1>;
3539                         #size-cells = <1>;
3540                         ranges = <0x0 0x2e000 0x1000>;
3541
3542                         timer16: timer@0 {
3543                                 compatible = "ti,omap5430-timer";
3544                                 reg = <0x0 0x80>;
3545                                 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
3546                                 clock-names = "fck";
3547                                 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
3548                         };
3549                 };
3550
3551                 rtctarget: target-module@38000 {                        /* 0x48838000, ap 29 12.0 */
3552                         compatible = "ti,sysc-omap4-simple", "ti,sysc";
3553                         ti,hwmods = "rtcss";
3554                         reg = <0x38074 0x4>,
3555                               <0x38078 0x4>;
3556                         reg-names = "rev", "sysc";
3557                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3558                                         <SYSC_IDLE_NO>,
3559                                         <SYSC_IDLE_SMART>,
3560                                         <SYSC_IDLE_SMART_WKUP>;
3561                         /* Domains (P, C): rtc_pwrdm, rtc_clkdm */
3562                         clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
3563                         clock-names = "fck";
3564                         #address-cells = <1>;
3565                         #size-cells = <1>;
3566                         ranges = <0x0 0x38000 0x1000>;
3567
3568                         rtc: rtc@0 {
3569                                 compatible = "ti,am3352-rtc";
3570                                 reg = <0x0 0x100>;
3571                                 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
3572                                              <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
3573                                 clocks = <&sys_32k_ck>;
3574                         };
3575                 };
3576
3577                 target-module@3a000 {                   /* 0x4883a000, ap 33 3e.0 */
3578                         compatible = "ti,sysc-omap4", "ti,sysc";
3579                         reg = <0x3a000 0x4>,
3580                               <0x3a010 0x4>;
3581                         reg-names = "rev", "sysc";
3582                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3583                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3584                                         <SYSC_IDLE_NO>,
3585                                         <SYSC_IDLE_SMART>;
3586                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3587                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
3588                         clock-names = "fck";
3589                         #address-cells = <1>;
3590                         #size-cells = <1>;
3591                         ranges = <0x0 0x3a000 0x1000>;
3592
3593                         mailbox2: mailbox@0 {
3594                                 compatible = "ti,omap4-mailbox";
3595                                 reg = <0x0 0x200>;
3596                                 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
3597                                              <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3598                                              <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
3599                                              <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
3600                                 #mbox-cells = <1>;
3601                                 ti,mbox-num-users = <4>;
3602                                 ti,mbox-num-fifos = <12>;
3603                                 status = "disabled";
3604                         };
3605                 };
3606
3607                 target-module@3c000 {                   /* 0x4883c000, ap 35 3a.0 */
3608                         compatible = "ti,sysc-omap4", "ti,sysc";
3609                         reg = <0x3c000 0x4>,
3610                               <0x3c010 0x4>;
3611                         reg-names = "rev", "sysc";
3612                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3613                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3614                                         <SYSC_IDLE_NO>,
3615                                         <SYSC_IDLE_SMART>;
3616                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3617                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
3618                         clock-names = "fck";
3619                         #address-cells = <1>;
3620                         #size-cells = <1>;
3621                         ranges = <0x0 0x3c000 0x1000>;
3622
3623                         mailbox3: mailbox@0 {
3624                                 compatible = "ti,omap4-mailbox";
3625                                 reg = <0x0 0x200>;
3626                                 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3627                                              <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
3628                                              <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
3629                                              <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
3630                                 #mbox-cells = <1>;
3631                                 ti,mbox-num-users = <4>;
3632                                 ti,mbox-num-fifos = <12>;
3633                                 status = "disabled";
3634                         };
3635                 };
3636
3637                 target-module@3e000 {                   /* 0x4883e000, ap 37 46.0 */
3638                         compatible = "ti,sysc-omap4", "ti,sysc";
3639                         reg = <0x3e000 0x4>,
3640                               <0x3e010 0x4>;
3641                         reg-names = "rev", "sysc";
3642                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3643                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3644                                         <SYSC_IDLE_NO>,
3645                                         <SYSC_IDLE_SMART>;
3646                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3647                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
3648                         clock-names = "fck";
3649                         #address-cells = <1>;
3650                         #size-cells = <1>;
3651                         ranges = <0x0 0x3e000 0x1000>;
3652
3653                         mailbox4: mailbox@0 {
3654                                 compatible = "ti,omap4-mailbox";
3655                                 reg = <0x0 0x200>;
3656                                 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3657                                              <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
3658                                              <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3659                                              <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
3660                                 #mbox-cells = <1>;
3661                                 ti,mbox-num-users = <4>;
3662                                 ti,mbox-num-fifos = <12>;
3663                                 status = "disabled";
3664                         };
3665                 };
3666
3667                 target-module@40000 {                   /* 0x48840000, ap 39 64.0 */
3668                         compatible = "ti,sysc-omap4", "ti,sysc";
3669                         reg = <0x40000 0x4>,
3670                               <0x40010 0x4>;
3671                         reg-names = "rev", "sysc";
3672                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3673                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3674                                         <SYSC_IDLE_NO>,
3675                                         <SYSC_IDLE_SMART>;
3676                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3677                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
3678                         clock-names = "fck";
3679                         #address-cells = <1>;
3680                         #size-cells = <1>;
3681                         ranges = <0x0 0x40000 0x1000>;
3682
3683                         mailbox5: mailbox@0 {
3684                                 compatible = "ti,omap4-mailbox";
3685                                 reg = <0x0 0x200>;
3686                                 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3687                                              <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3688                                              <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3689                                              <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
3690                                 #mbox-cells = <1>;
3691                                 ti,mbox-num-users = <4>;
3692                                 ti,mbox-num-fifos = <12>;
3693                                 status = "disabled";
3694                         };
3695                 };
3696
3697                 target-module@42000 {                   /* 0x48842000, ap 41 4e.0 */
3698                         compatible = "ti,sysc-omap4", "ti,sysc";
3699                         reg = <0x42000 0x4>,
3700                               <0x42010 0x4>;
3701                         reg-names = "rev", "sysc";
3702                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3703                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3704                                         <SYSC_IDLE_NO>,
3705                                         <SYSC_IDLE_SMART>;
3706                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3707                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
3708                         clock-names = "fck";
3709                         #address-cells = <1>;
3710                         #size-cells = <1>;
3711                         ranges = <0x0 0x42000 0x1000>;
3712
3713                         mailbox6: mailbox@0 {
3714                                 compatible = "ti,omap4-mailbox";
3715                                 reg = <0x0 0x200>;
3716                                 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3717                                              <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3718                                              <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3719                                              <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
3720                                 #mbox-cells = <1>;
3721                                 ti,mbox-num-users = <4>;
3722                                 ti,mbox-num-fifos = <12>;
3723                                 status = "disabled";
3724                         };
3725                 };
3726
3727                 target-module@44000 {                   /* 0x48844000, ap 43 42.0 */
3728                         compatible = "ti,sysc-omap4", "ti,sysc";
3729                         reg = <0x44000 0x4>,
3730                               <0x44010 0x4>;
3731                         reg-names = "rev", "sysc";
3732                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3733                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3734                                         <SYSC_IDLE_NO>,
3735                                         <SYSC_IDLE_SMART>;
3736                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3737                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
3738                         clock-names = "fck";
3739                         #address-cells = <1>;
3740                         #size-cells = <1>;
3741                         ranges = <0x0 0x44000 0x1000>;
3742
3743                         mailbox7: mailbox@0 {
3744                                 compatible = "ti,omap4-mailbox";
3745                                 reg = <0x0 0x200>;
3746                                 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
3747                                              <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
3748                                              <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
3749                                              <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
3750                                 #mbox-cells = <1>;
3751                                 ti,mbox-num-users = <4>;
3752                                 ti,mbox-num-fifos = <12>;
3753                                 status = "disabled";
3754                         };
3755                 };
3756
3757                 target-module@46000 {                   /* 0x48846000, ap 45 48.0 */
3758                         compatible = "ti,sysc-omap4", "ti,sysc";
3759                         reg = <0x46000 0x4>,
3760                               <0x46010 0x4>;
3761                         reg-names = "rev", "sysc";
3762                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3763                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3764                                         <SYSC_IDLE_NO>,
3765                                         <SYSC_IDLE_SMART>;
3766                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3767                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
3768                         clock-names = "fck";
3769                         #address-cells = <1>;
3770                         #size-cells = <1>;
3771                         ranges = <0x0 0x46000 0x1000>;
3772
3773                         mailbox8: mailbox@0 {
3774                                 compatible = "ti,omap4-mailbox";
3775                                 reg = <0x0 0x200>;
3776                                 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3777                                              <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3778                                              <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3779                                              <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
3780                                 #mbox-cells = <1>;
3781                                 ti,mbox-num-users = <4>;
3782                                 ti,mbox-num-fifos = <12>;
3783                                 status = "disabled";
3784                         };
3785                 };
3786
3787                 target-module@48000 {                   /* 0x48848000, ap 47 36.0 */
3788                         compatible = "ti,sysc";
3789                         status = "disabled";
3790                         #address-cells = <1>;
3791                         #size-cells = <1>;
3792                         ranges = <0x0 0x48000 0x1000>;
3793                 };
3794
3795                 target-module@4a000 {                   /* 0x4884a000, ap 49 38.0 */
3796                         compatible = "ti,sysc";
3797                         status = "disabled";
3798                         #address-cells = <1>;
3799                         #size-cells = <1>;
3800                         ranges = <0x0 0x4a000 0x1000>;
3801                 };
3802
3803                 target-module@4c000 {                   /* 0x4884c000, ap 51 44.0 */
3804                         compatible = "ti,sysc";
3805                         status = "disabled";
3806                         #address-cells = <1>;
3807                         #size-cells = <1>;
3808                         ranges = <0x0 0x4c000 0x1000>;
3809                 };
3810
3811                 target-module@4e000 {                   /* 0x4884e000, ap 53 4c.0 */
3812                         compatible = "ti,sysc";
3813                         status = "disabled";
3814                         #address-cells = <1>;
3815                         #size-cells = <1>;
3816                         ranges = <0x0 0x4e000 0x1000>;
3817                 };
3818
3819                 target-module@50000 {                   /* 0x48850000, ap 55 40.0 */
3820                         compatible = "ti,sysc";
3821                         status = "disabled";
3822                         #address-cells = <1>;
3823                         #size-cells = <1>;
3824                         ranges = <0x0 0x50000 0x1000>;
3825                 };
3826
3827                 target-module@52000 {                   /* 0x48852000, ap 57 54.0 */
3828                         compatible = "ti,sysc";
3829                         status = "disabled";
3830                         #address-cells = <1>;
3831                         #size-cells = <1>;
3832                         ranges = <0x0 0x52000 0x1000>;
3833                 };
3834
3835                 target-module@54000 {                   /* 0x48854000, ap 59 1a.0 */
3836                         compatible = "ti,sysc";
3837                         status = "disabled";
3838                         #address-cells = <1>;
3839                         #size-cells = <1>;
3840                         ranges = <0x0 0x54000 0x1000>;
3841                 };
3842
3843                 target-module@56000 {                   /* 0x48856000, ap 61 22.0 */
3844                         compatible = "ti,sysc";
3845                         status = "disabled";
3846                         #address-cells = <1>;
3847                         #size-cells = <1>;
3848                         ranges = <0x0 0x56000 0x1000>;
3849                 };
3850
3851                 target-module@58000 {                   /* 0x48858000, ap 63 2a.0 */
3852                         compatible = "ti,sysc";
3853                         status = "disabled";
3854                         #address-cells = <1>;
3855                         #size-cells = <1>;
3856                         ranges = <0x0 0x58000 0x1000>;
3857                 };
3858
3859                 target-module@5a000 {                   /* 0x4885a000, ap 65 5c.0 */
3860                         compatible = "ti,sysc";
3861                         status = "disabled";
3862                         #address-cells = <1>;
3863                         #size-cells = <1>;
3864                         ranges = <0x0 0x5a000 0x1000>;
3865                 };
3866
3867                 target-module@5c000 {                   /* 0x4885c000, ap 31 32.0 */
3868                         compatible = "ti,sysc";
3869                         status = "disabled";
3870                         #address-cells = <1>;
3871                         #size-cells = <1>;
3872                         ranges = <0x0 0x5c000 0x1000>;
3873                 };
3874
3875                 target-module@5e000 {                   /* 0x4885e000, ap 69 6c.0 */
3876                         compatible = "ti,sysc-omap4", "ti,sysc";
3877                         reg = <0x5e000 0x4>,
3878                               <0x5e010 0x4>;
3879                         reg-names = "rev", "sysc";
3880                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3881                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3882                                         <SYSC_IDLE_NO>,
3883                                         <SYSC_IDLE_SMART>;
3884                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3885                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
3886                         clock-names = "fck";
3887                         #address-cells = <1>;
3888                         #size-cells = <1>;
3889                         ranges = <0x0 0x5e000 0x1000>;
3890
3891                         mailbox9: mailbox@0 {
3892                                 compatible = "ti,omap4-mailbox";
3893                                 reg = <0x0 0x200>;
3894                                 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
3895                                              <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3896                                              <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3897                                              <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3898                                 #mbox-cells = <1>;
3899                                 ti,mbox-num-users = <4>;
3900                                 ti,mbox-num-fifos = <12>;
3901                                 status = "disabled";
3902                         };
3903                 };
3904
3905                 target-module@60000 {                   /* 0x48860000, ap 71 4a.0 */
3906                         compatible = "ti,sysc-omap4", "ti,sysc";
3907                         reg = <0x60000 0x4>,
3908                               <0x60010 0x4>;
3909                         reg-names = "rev", "sysc";
3910                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3911                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3912                                         <SYSC_IDLE_NO>,
3913                                         <SYSC_IDLE_SMART>;
3914                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3915                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
3916                         clock-names = "fck";
3917                         #address-cells = <1>;
3918                         #size-cells = <1>;
3919                         ranges = <0x0 0x60000 0x1000>;
3920
3921                         mailbox10: mailbox@0 {
3922                                 compatible = "ti,omap4-mailbox";
3923                                 reg = <0x0 0x200>;
3924                                 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
3925                                              <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
3926                                              <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
3927                                              <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3928                                 #mbox-cells = <1>;
3929                                 ti,mbox-num-users = <4>;
3930                                 ti,mbox-num-fifos = <12>;
3931                                 status = "disabled";
3932                         };
3933                 };
3934
3935                 target-module@62000 {                   /* 0x48862000, ap 73 74.0 */
3936                         compatible = "ti,sysc-omap4", "ti,sysc";
3937                         reg = <0x62000 0x4>,
3938                               <0x62010 0x4>;
3939                         reg-names = "rev", "sysc";
3940                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3941                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3942                                         <SYSC_IDLE_NO>,
3943                                         <SYSC_IDLE_SMART>;
3944                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3945                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
3946                         clock-names = "fck";
3947                         #address-cells = <1>;
3948                         #size-cells = <1>;
3949                         ranges = <0x0 0x62000 0x1000>;
3950
3951                         mailbox11: mailbox@0 {
3952                                 compatible = "ti,omap4-mailbox";
3953                                 reg = <0x0 0x200>;
3954                                 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
3955                                              <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
3956                                              <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
3957                                              <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
3958                                 #mbox-cells = <1>;
3959                                 ti,mbox-num-users = <4>;
3960                                 ti,mbox-num-fifos = <12>;
3961                                 status = "disabled";
3962                         };
3963                 };
3964
3965                 target-module@64000 {                   /* 0x48864000, ap 67 52.0 */
3966                         compatible = "ti,sysc-omap4", "ti,sysc";
3967                         reg = <0x64000 0x4>,
3968                               <0x64010 0x4>;
3969                         reg-names = "rev", "sysc";
3970                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3971                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3972                                         <SYSC_IDLE_NO>,
3973                                         <SYSC_IDLE_SMART>;
3974                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3975                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
3976                         clock-names = "fck";
3977                         #address-cells = <1>;
3978                         #size-cells = <1>;
3979                         ranges = <0x0 0x64000 0x1000>;
3980
3981                         mailbox12: mailbox@0 {
3982                                 compatible = "ti,omap4-mailbox";
3983                                 reg = <0x0 0x200>;
3984                                 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
3985                                              <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
3986                                              <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
3987                                              <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
3988                                 #mbox-cells = <1>;
3989                                 ti,mbox-num-users = <4>;
3990                                 ti,mbox-num-fifos = <12>;
3991                                 status = "disabled";
3992                         };
3993                 };
3994
3995                 target-module@80000 {                   /* 0x48880000, ap 83 0e.1 */
3996                         compatible = "ti,sysc-omap4", "ti,sysc";
3997                         ti,hwmods = "usb_otg_ss1";
3998                         reg = <0x80000 0x4>,
3999                               <0x80010 0x4>;
4000                         reg-names = "rev", "sysc";
4001                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4002                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4003                                         <SYSC_IDLE_NO>,
4004                                         <SYSC_IDLE_SMART>,
4005                                         <SYSC_IDLE_SMART_WKUP>;
4006                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4007                                         <SYSC_IDLE_NO>,
4008                                         <SYSC_IDLE_SMART>,
4009                                         <SYSC_IDLE_SMART_WKUP>;
4010                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4011                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
4012                         clock-names = "fck";
4013                         #address-cells = <1>;
4014                         #size-cells = <1>;
4015                         ranges = <0x0 0x80000 0x20000>;
4016
4017                         omap_dwc3_1: omap_dwc3_1@0 {
4018                                 compatible = "ti,dwc3";
4019                                 reg = <0x0 0x10000>;
4020                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4021                                 #address-cells = <1>;
4022                                 #size-cells = <1>;
4023                                 utmi-mode = <2>;
4024                                 ranges = <0 0 0x20000>;
4025
4026                                 usb1: usb@10000 {
4027                                         compatible = "snps,dwc3";
4028                                         reg = <0x10000 0x17000>;
4029                                         interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
4030                                                      <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
4031                                                      <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4032                                         interrupt-names = "peripheral",
4033                                                           "host",
4034                                                           "otg";
4035                                         phys = <&usb2_phy1>, <&usb3_phy1>;
4036                                         phy-names = "usb2-phy", "usb3-phy";
4037                                         maximum-speed = "super-speed";
4038                                         dr_mode = "otg";
4039                                         snps,dis_u3_susphy_quirk;
4040                                         snps,dis_u2_susphy_quirk;
4041                                 };
4042                         };
4043                 };
4044
4045                 target-module@c0000 {                   /* 0x488c0000, ap 79 06.0 */
4046                         compatible = "ti,sysc-omap4", "ti,sysc";
4047                         ti,hwmods = "usb_otg_ss2";
4048                         reg = <0xc0000 0x4>,
4049                               <0xc0010 0x4>;
4050                         reg-names = "rev", "sysc";
4051                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4052                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4053                                         <SYSC_IDLE_NO>,
4054                                         <SYSC_IDLE_SMART>,
4055                                         <SYSC_IDLE_SMART_WKUP>;
4056                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4057                                         <SYSC_IDLE_NO>,
4058                                         <SYSC_IDLE_SMART>,
4059                                         <SYSC_IDLE_SMART_WKUP>;
4060                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4061                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
4062                         clock-names = "fck";
4063                         #address-cells = <1>;
4064                         #size-cells = <1>;
4065                         ranges = <0x0 0xc0000 0x20000>;
4066
4067                         omap_dwc3_2: omap_dwc3_2@0 {
4068                                 compatible = "ti,dwc3";
4069                                 reg = <0x0 0x10000>;
4070                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4071                                 #address-cells = <1>;
4072                                 #size-cells = <1>;
4073                                 utmi-mode = <2>;
4074                                 ranges = <0 0 0x20000>;
4075
4076                                 usb2: usb@10000 {
4077                                         compatible = "snps,dwc3";
4078                                         reg = <0x10000 0x17000>;
4079                                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4080                                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4081                                                      <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4082                                         interrupt-names = "peripheral",
4083                                                           "host",
4084                                                           "otg";
4085                                         phys = <&usb2_phy2>;
4086                                         phy-names = "usb2-phy";
4087                                         maximum-speed = "high-speed";
4088                                         dr_mode = "otg";
4089                                         snps,dis_u3_susphy_quirk;
4090                                         snps,dis_u2_susphy_quirk;
4091                                         snps,dis_metastability_quirk;
4092                                 };
4093                         };
4094                 };
4095
4096                 usb3_tm: target-module@100000 {         /* 0x48900000, ap 85 04.0 */
4097                         compatible = "ti,sysc-omap4", "ti,sysc";
4098                         ti,hwmods = "usb_otg_ss3";
4099                         reg = <0x100000 0x4>,
4100                               <0x100010 0x4>;
4101                         reg-names = "rev", "sysc";
4102                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4103                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4104                                         <SYSC_IDLE_NO>,
4105                                         <SYSC_IDLE_SMART>,
4106                                         <SYSC_IDLE_SMART_WKUP>;
4107                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4108                                         <SYSC_IDLE_NO>,
4109                                         <SYSC_IDLE_SMART>,
4110                                         <SYSC_IDLE_SMART_WKUP>;
4111                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4112                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
4113                         clock-names = "fck";
4114                         #address-cells = <1>;
4115                         #size-cells = <1>;
4116                         ranges = <0x0 0x100000 0x20000>;
4117
4118                         omap_dwc3_3: omap_dwc3_3@0 {
4119                                 compatible = "ti,dwc3";
4120                                 reg = <0x0 0x10000>;
4121                                 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4122                                 #address-cells = <1>;
4123                                 #size-cells = <1>;
4124                                 utmi-mode = <2>;
4125                                 ranges = <0 0 0x20000>;
4126                                 status = "disabled";
4127
4128                                 usb3: usb@10000 {
4129                                         compatible = "snps,dwc3";
4130                                         reg = <0x10000 0x17000>;
4131                                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4132                                                      <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4133                                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4134                                         interrupt-names = "peripheral",
4135                                                           "host",
4136                                                           "otg";
4137                                         maximum-speed = "high-speed";
4138                                         dr_mode = "otg";
4139                                         snps,dis_u3_susphy_quirk;
4140                                         snps,dis_u2_susphy_quirk;
4141                                 };
4142                         };
4143                 };
4144
4145                 usb4_tm: target-module@140000 {         /* 0x48940000, ap 75 3c.0 */
4146                         compatible = "ti,sysc-omap4", "ti,sysc";
4147                         ti,hwmods = "usb_otg_ss4";
4148                         reg = <0x140000 0x4>,
4149                               <0x140010 0x4>;
4150                         reg-names = "rev", "sysc";
4151                         ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4152                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
4153                                         <SYSC_IDLE_NO>,
4154                                         <SYSC_IDLE_SMART>,
4155                                         <SYSC_IDLE_SMART_WKUP>;
4156                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4157                                         <SYSC_IDLE_NO>,
4158                                         <SYSC_IDLE_SMART>,
4159                                         <SYSC_IDLE_SMART_WKUP>;
4160                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4161                         clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
4162                         clock-names = "fck";
4163                         #address-cells = <1>;
4164                         #size-cells = <1>;
4165                         ranges = <0x0 0x140000 0x20000>;
4166                 };
4167
4168                 target-module@170000 {                  /* 0x48970000, ap 21 0a.0 */
4169                         compatible = "ti,sysc";
4170                         status = "disabled";
4171                         #address-cells = <1>;
4172                         #size-cells = <1>;
4173                         ranges = <0x0 0x170000 0x10000>;
4174                 };
4175
4176                 target-module@190000 {                  /* 0x48990000, ap 23 2e.0 */
4177                         compatible = "ti,sysc";
4178                         status = "disabled";
4179                         #address-cells = <1>;
4180                         #size-cells = <1>;
4181                         ranges = <0x0 0x190000 0x10000>;
4182                 };
4183
4184                 target-module@1b0000 {                  /* 0x489b0000, ap 25 34.0 */
4185                         compatible = "ti,sysc";
4186                         status = "disabled";
4187                         #address-cells = <1>;
4188                         #size-cells = <1>;
4189                         ranges = <0x0 0x1b0000 0x10000>;
4190                 };
4191
4192                 target-module@1d0000 {                  /* 0x489d0000, ap 27 30.0 */
4193                         compatible = "ti,sysc";
4194                         status = "disabled";
4195                         #address-cells = <1>;
4196                         #size-cells = <1>;
4197                         ranges = <0x0 0x1d0000 0x10000>;
4198                 };
4199         };
4200 };
4201
4202 &l4_wkup {                                              /* 0x4ae00000 */
4203         compatible = "ti,dra7-l4-wkup", "simple-bus";
4204         reg = <0x4ae00000 0x800>,
4205               <0x4ae00800 0x800>,
4206               <0x4ae01000 0x1000>;
4207         reg-names = "ap", "la", "ia0";
4208         #address-cells = <1>;
4209         #size-cells = <1>;
4210         ranges = <0x00000000 0x4ae00000 0x010000>,      /* segment 0 */
4211                  <0x00010000 0x4ae10000 0x010000>,      /* segment 1 */
4212                  <0x00020000 0x4ae20000 0x010000>,      /* segment 2 */
4213                  <0x00030000 0x4ae30000 0x010000>;      /* segment 3 */
4214
4215         segment@0 {                                     /* 0x4ae00000 */
4216                 compatible = "simple-bus";
4217                 #address-cells = <1>;
4218                 #size-cells = <1>;
4219                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
4220                          <0x00001000 0x00001000 0x001000>,      /* ap 1 */
4221                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
4222                          <0x00006000 0x00006000 0x002000>,      /* ap 3 */
4223                          <0x00008000 0x00008000 0x001000>,      /* ap 4 */
4224                          <0x00004000 0x00004000 0x001000>,      /* ap 15 */
4225                          <0x00005000 0x00005000 0x001000>,      /* ap 16 */
4226                          <0x0000c000 0x0000c000 0x001000>,      /* ap 17 */
4227                          <0x0000d000 0x0000d000 0x001000>;      /* ap 18 */
4228
4229                 target-module@4000 {                    /* 0x4ae04000, ap 15 40.0 */
4230                         compatible = "ti,sysc-omap2", "ti,sysc";
4231                         ti,hwmods = "counter_32k";
4232                         reg = <0x4000 0x4>,
4233                               <0x4010 0x4>;
4234                         reg-names = "rev", "sysc";
4235                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4236                                         <SYSC_IDLE_NO>,
4237                                         <SYSC_IDLE_SMART>,
4238                                         <SYSC_IDLE_SMART_WKUP>;
4239                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4240                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
4241                         clock-names = "fck";
4242                         #address-cells = <1>;
4243                         #size-cells = <1>;
4244                         ranges = <0x0 0x4000 0x1000>;
4245
4246                         counter32k: counter@0 {
4247                                 compatible = "ti,omap-counter32k";
4248                                 reg = <0x0 0x40>;
4249                         };
4250                 };
4251
4252                 target-module@6000 {                    /* 0x4ae06000, ap 3 10.0 */
4253                         compatible = "ti,sysc-omap4", "ti,sysc";
4254                         reg = <0x6000 0x4>;
4255                         reg-names = "rev";
4256                         #address-cells = <1>;
4257                         #size-cells = <1>;
4258                         ranges = <0x0 0x6000 0x2000>;
4259
4260                         prm: prm@0 {
4261                                 compatible = "ti,dra7-prm", "simple-bus";
4262                                 reg = <0 0x3000>;
4263                                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4264                                 #address-cells = <1>;
4265                                 #size-cells = <1>;
4266                                 ranges = <0 0 0x3000>;
4267
4268                                 prm_clocks: clocks {
4269                                         #address-cells = <1>;
4270                                         #size-cells = <0>;
4271                                 };
4272
4273                                 prm_clockdomains: clockdomains {
4274                                 };
4275                         };
4276                 };
4277
4278                 target-module@c000 {                    /* 0x4ae0c000, ap 17 50.0 */
4279                         compatible = "ti,sysc-omap4", "ti,sysc";
4280                         reg = <0xc000 0x4>;
4281                         reg-names = "rev";
4282                         #address-cells = <1>;
4283                         #size-cells = <1>;
4284                         ranges = <0x0 0xc000 0x1000>;
4285
4286                         scm_wkup: scm_conf@0 {
4287                                 compatible = "syscon";
4288                                 reg = <0 0x1000>;
4289                         };
4290                 };
4291         };
4292
4293         segment@10000 {                                 /* 0x4ae10000 */
4294                 compatible = "simple-bus";
4295                 #address-cells = <1>;
4296                 #size-cells = <1>;
4297                 ranges = <0x00000000 0x00010000 0x001000>,      /* ap 5 */
4298                          <0x00001000 0x00011000 0x001000>,      /* ap 6 */
4299                          <0x00004000 0x00014000 0x001000>,      /* ap 7 */
4300                          <0x00005000 0x00015000 0x001000>,      /* ap 8 */
4301                          <0x00008000 0x00018000 0x001000>,      /* ap 9 */
4302                          <0x00009000 0x00019000 0x001000>,      /* ap 10 */
4303                          <0x0000c000 0x0001c000 0x001000>,      /* ap 11 */
4304                          <0x0000d000 0x0001d000 0x001000>;      /* ap 12 */
4305
4306                 target-module@0 {                       /* 0x4ae10000, ap 5 20.0 */
4307                         compatible = "ti,sysc-omap2", "ti,sysc";
4308                         reg = <0x0 0x4>,
4309                               <0x10 0x4>,
4310                               <0x114 0x4>;
4311                         reg-names = "rev", "sysc", "syss";
4312                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4313                                          SYSC_OMAP2_SOFTRESET |
4314                                          SYSC_OMAP2_AUTOIDLE)>;
4315                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4316                                         <SYSC_IDLE_NO>,
4317                                         <SYSC_IDLE_SMART>,
4318                                         <SYSC_IDLE_SMART_WKUP>;
4319                         ti,syss-mask = <1>;
4320                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4321                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
4322                                  <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>;
4323                         clock-names = "fck", "dbclk";
4324                         #address-cells = <1>;
4325                         #size-cells = <1>;
4326                         ranges = <0x0 0x0 0x1000>;
4327
4328                         gpio1: gpio@0 {
4329                                 compatible = "ti,omap4-gpio";
4330                                 reg = <0x0 0x200>;
4331                                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
4332                                 gpio-controller;
4333                                 #gpio-cells = <2>;
4334                                 interrupt-controller;
4335                                 #interrupt-cells = <2>;
4336                         };
4337                 };
4338
4339                 target-module@4000 {                    /* 0x4ae14000, ap 7 28.0 */
4340                         compatible = "ti,sysc-omap2", "ti,sysc";
4341                         reg = <0x4000 0x4>,
4342                               <0x4010 0x4>,
4343                               <0x4014 0x4>;
4344                         reg-names = "rev", "sysc", "syss";
4345                         ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
4346                                          SYSC_OMAP2_SOFTRESET)>;
4347                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4348                                         <SYSC_IDLE_NO>,
4349                                         <SYSC_IDLE_SMART>,
4350                                         <SYSC_IDLE_SMART_WKUP>;
4351                         ti,syss-mask = <1>;
4352                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4353                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
4354                         clock-names = "fck";
4355                         #address-cells = <1>;
4356                         #size-cells = <1>;
4357                         ranges = <0x0 0x4000 0x1000>;
4358
4359                         wdt2: wdt@0 {
4360                                 compatible = "ti,omap3-wdt";
4361                                 reg = <0x0 0x80>;
4362                                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4363                         };
4364                 };
4365
4366                 target-module@8000 {                    /* 0x4ae18000, ap 9 30.0 */
4367                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
4368                         ti,hwmods = "timer1";
4369                         reg = <0x8000 0x4>,
4370                               <0x8010 0x4>;
4371                         reg-names = "rev", "sysc";
4372                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4373                                          SYSC_OMAP4_SOFTRESET)>;
4374                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4375                                         <SYSC_IDLE_NO>,
4376                                         <SYSC_IDLE_SMART>,
4377                                         <SYSC_IDLE_SMART_WKUP>;
4378                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4379                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
4380                         clock-names = "fck";
4381                         #address-cells = <1>;
4382                         #size-cells = <1>;
4383                         ranges = <0x0 0x8000 0x1000>;
4384
4385                         timer1: timer@0 {
4386                                 compatible = "ti,omap5430-timer";
4387                                 reg = <0x0 0x80>;
4388                                 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
4389                                 clock-names = "fck";
4390                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4391                                 ti,timer-alwon;
4392                         };
4393                 };
4394
4395                 target-module@c000 {                    /* 0x4ae1c000, ap 11 38.0 */
4396                         compatible = "ti,sysc";
4397                         status = "disabled";
4398                         #address-cells = <1>;
4399                         #size-cells = <1>;
4400                         ranges = <0x0 0xc000 0x1000>;
4401                 };
4402         };
4403
4404         segment@20000 {                                 /* 0x4ae20000 */
4405                 compatible = "simple-bus";
4406                 #address-cells = <1>;
4407                 #size-cells = <1>;
4408                 ranges = <0x00006000 0x00026000 0x001000>,      /* ap 13 */
4409                          <0x0000a000 0x0002a000 0x001000>,      /* ap 14 */
4410                          <0x00000000 0x00020000 0x001000>,      /* ap 19 */
4411                          <0x00001000 0x00021000 0x001000>,      /* ap 20 */
4412                          <0x00002000 0x00022000 0x001000>,      /* ap 21 */
4413                          <0x00003000 0x00023000 0x001000>,      /* ap 22 */
4414                          <0x00007000 0x00027000 0x000400>,      /* ap 23 */
4415                          <0x00008000 0x00028000 0x000800>,      /* ap 24 */
4416                          <0x00009000 0x00029000 0x000100>,      /* ap 25 */
4417                          <0x00008800 0x00028800 0x000200>,      /* ap 26 */
4418                          <0x00008a00 0x00028a00 0x000100>,      /* ap 27 */
4419                          <0x0000b000 0x0002b000 0x001000>,      /* ap 28 */
4420                          <0x0000c000 0x0002c000 0x001000>,      /* ap 29 */
4421                          <0x0000f000 0x0002f000 0x001000>;      /* ap 32 */
4422
4423                 target-module@0 {                       /* 0x4ae20000, ap 19 08.0 */
4424                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
4425                         ti,hwmods = "timer12";
4426                         reg = <0x0 0x4>,
4427                               <0x10 0x4>;
4428                         reg-names = "rev", "sysc";
4429                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4430                                          SYSC_OMAP4_SOFTRESET)>;
4431                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4432                                         <SYSC_IDLE_NO>,
4433                                         <SYSC_IDLE_SMART>,
4434                                         <SYSC_IDLE_SMART_WKUP>;
4435                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4436                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
4437                         clock-names = "fck";
4438                         #address-cells = <1>;
4439                         #size-cells = <1>;
4440                         ranges = <0x0 0x0 0x1000>;
4441
4442                         timer12: timer@0 {
4443                                 compatible = "ti,omap5430-timer";
4444                                 reg = <0x0 0x80>;
4445                                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
4446                                 ti,timer-alwon;
4447                                 ti,timer-secure;
4448                         };
4449                 };
4450
4451                 target-module@2000 {                    /* 0x4ae22000, ap 21 18.0 */
4452                         compatible = "ti,sysc";
4453                         status = "disabled";
4454                         #address-cells = <1>;
4455                         #size-cells = <1>;
4456                         ranges = <0x0 0x2000 0x1000>;
4457                 };
4458
4459                 target-module@6000 {                    /* 0x4ae26000, ap 13 48.0 */
4460                         compatible = "ti,sysc";
4461                         status = "disabled";
4462                         #address-cells = <1>;
4463                         #size-cells = <1>;
4464                         ranges = <0x00000000 0x00006000 0x00001000>,
4465                                  <0x00001000 0x00007000 0x00000400>,
4466                                  <0x00002000 0x00008000 0x00000800>,
4467                                  <0x00002800 0x00008800 0x00000200>,
4468                                  <0x00002a00 0x00008a00 0x00000100>,
4469                                  <0x00003000 0x00009000 0x00000100>;
4470                 };
4471
4472                 target-module@b000 {                    /* 0x4ae2b000, ap 28 02.0 */
4473                         compatible = "ti,sysc-omap2", "ti,sysc";
4474                         reg = <0xb050 0x4>,
4475                               <0xb054 0x4>,
4476                               <0xb058 0x4>;
4477                         reg-names = "rev", "sysc", "syss";
4478                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4479                                          SYSC_OMAP2_SOFTRESET |
4480                                          SYSC_OMAP2_AUTOIDLE)>;
4481                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4482                                         <SYSC_IDLE_NO>,
4483                                         <SYSC_IDLE_SMART>,
4484                                         <SYSC_IDLE_SMART_WKUP>;
4485                         ti,syss-mask = <1>;
4486                         /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4487                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
4488                         clock-names = "fck";
4489                         #address-cells = <1>;
4490                         #size-cells = <1>;
4491                         ranges = <0x0 0xb000 0x1000>;
4492
4493                         uart10: serial@0 {
4494                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
4495                                 reg = <0x0 0x100>;
4496                                 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
4497                                 clock-frequency = <48000000>;
4498                                 status = "disabled";
4499                         };
4500                 };
4501
4502                 target-module@f000 {                    /* 0x4ae2f000, ap 32 58.0 */
4503                         compatible = "ti,sysc";
4504                         status = "disabled";
4505                         #address-cells = <1>;
4506                         #size-cells = <1>;
4507                         ranges = <0x0 0xf000 0x1000>;
4508                 };
4509         };
4510
4511         segment@30000 {                                 /* 0x4ae30000 */
4512                 compatible = "simple-bus";
4513                 #address-cells = <1>;
4514                 #size-cells = <1>;
4515                 ranges = <0x0000c000 0x0003c000 0x002000>,      /* ap 30 */
4516                          <0x0000e000 0x0003e000 0x001000>,      /* ap 31 */
4517                          <0x00000000 0x00030000 0x001000>,      /* ap 33 */
4518                          <0x00001000 0x00031000 0x001000>,      /* ap 34 */
4519                          <0x00002000 0x00032000 0x001000>,      /* ap 35 */
4520                          <0x00003000 0x00033000 0x001000>,      /* ap 36 */
4521                          <0x00004000 0x00034000 0x001000>,      /* ap 37 */
4522                          <0x00005000 0x00035000 0x001000>,      /* ap 38 */
4523                          <0x00006000 0x00036000 0x001000>,      /* ap 39 */
4524                          <0x00007000 0x00037000 0x001000>,      /* ap 40 */
4525                          <0x00008000 0x00038000 0x001000>,      /* ap 41 */
4526                          <0x00009000 0x00039000 0x001000>,      /* ap 42 */
4527                          <0x0000a000 0x0003a000 0x001000>;      /* ap 43 */
4528
4529                 target-module@1000 {                    /* 0x4ae31000, ap 34 60.0 */
4530                         compatible = "ti,sysc";
4531                         status = "disabled";
4532                         #address-cells = <1>;
4533                         #size-cells = <1>;
4534                         ranges = <0x0 0x1000 0x1000>;
4535                 };
4536
4537                 target-module@3000 {                    /* 0x4ae33000, ap 36 0a.0 */
4538                         compatible = "ti,sysc";
4539                         status = "disabled";
4540                         #address-cells = <1>;
4541                         #size-cells = <1>;
4542                         ranges = <0x0 0x3000 0x1000>;
4543                 };
4544
4545                 target-module@5000 {                    /* 0x4ae35000, ap 38 0c.0 */
4546                         compatible = "ti,sysc";
4547                         status = "disabled";
4548                         #address-cells = <1>;
4549                         #size-cells = <1>;
4550                         ranges = <0x0 0x5000 0x1000>;
4551                 };
4552
4553                 target-module@7000 {                    /* 0x4ae37000, ap 40 68.0 */
4554                         compatible = "ti,sysc";
4555                         status = "disabled";
4556                         #address-cells = <1>;
4557                         #size-cells = <1>;
4558                         ranges = <0x0 0x7000 0x1000>;
4559                 };
4560
4561                 target-module@9000 {                    /* 0x4ae39000, ap 42 70.0 */
4562                         compatible = "ti,sysc";
4563                         status = "disabled";
4564                         #address-cells = <1>;
4565                         #size-cells = <1>;
4566                         ranges = <0x0 0x9000 0x1000>;
4567                 };
4568
4569                 target-module@c000 {                    /* 0x4ae3c000, ap 30 04.0 */
4570                         compatible = "ti,sysc-omap4", "ti,sysc";
4571                         reg = <0xc020 0x4>;
4572                         reg-names = "rev";
4573                         clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
4574                         clock-names = "fck";
4575                         #address-cells = <1>;
4576                         #size-cells = <1>;
4577                         ranges = <0x0 0xc000 0x2000>;
4578
4579                         dcan1: can@0 {
4580                                 compatible = "ti,dra7-d_can";
4581                                 reg = <0x0 0x2000>;
4582                                 syscon-raminit = <&scm_conf 0x558 0>;
4583                                 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
4584                                 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>;
4585                                 status = "disabled";
4586                         };
4587                 };
4588         };
4589 };
4590