Merge tag 'fix-missing-panels' into fixes
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / dra7-l4.dtsi
1 &l4_cfg {                                               /* 0x4a000000 */
2         compatible = "ti,dra7-l4-cfg", "simple-bus";
3         reg = <0x4a000000 0x800>,
4               <0x4a000800 0x800>,
5               <0x4a001000 0x1000>;
6         reg-names = "ap", "la", "ia0";
7         #address-cells = <1>;
8         #size-cells = <1>;
9         ranges = <0x00000000 0x4a000000 0x100000>,      /* segment 0 */
10                  <0x00100000 0x4a100000 0x100000>,      /* segment 1 */
11                  <0x00200000 0x4a200000 0x100000>;      /* segment 2 */
12
13         segment@0 {                                     /* 0x4a000000 */
14                 compatible = "simple-bus";
15                 #address-cells = <1>;
16                 #size-cells = <1>;
17                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
18                          <0x00000800 0x00000800 0x000800>,      /* ap 1 */
19                          <0x00001000 0x00001000 0x001000>,      /* ap 2 */
20                          <0x00002000 0x00002000 0x002000>,      /* ap 3 */
21                          <0x00004000 0x00004000 0x001000>,      /* ap 4 */
22                          <0x00005000 0x00005000 0x001000>,      /* ap 5 */
23                          <0x00006000 0x00006000 0x001000>,      /* ap 6 */
24                          <0x00008000 0x00008000 0x002000>,      /* ap 7 */
25                          <0x0000a000 0x0000a000 0x001000>,      /* ap 8 */
26                          <0x00056000 0x00056000 0x001000>,      /* ap 9 */
27                          <0x00057000 0x00057000 0x001000>,      /* ap 10 */
28                          <0x0005e000 0x0005e000 0x002000>,      /* ap 11 */
29                          <0x00060000 0x00060000 0x001000>,      /* ap 12 */
30                          <0x00080000 0x00080000 0x008000>,      /* ap 13 */
31                          <0x00088000 0x00088000 0x001000>,      /* ap 14 */
32                          <0x000a0000 0x000a0000 0x008000>,      /* ap 15 */
33                          <0x000a8000 0x000a8000 0x001000>,      /* ap 16 */
34                          <0x000d9000 0x000d9000 0x001000>,      /* ap 17 */
35                          <0x000da000 0x000da000 0x001000>,      /* ap 18 */
36                          <0x000dd000 0x000dd000 0x001000>,      /* ap 19 */
37                          <0x000de000 0x000de000 0x001000>,      /* ap 20 */
38                          <0x000e0000 0x000e0000 0x001000>,      /* ap 21 */
39                          <0x000e1000 0x000e1000 0x001000>,      /* ap 22 */
40                          <0x000f4000 0x000f4000 0x001000>,      /* ap 23 */
41                          <0x000f5000 0x000f5000 0x001000>,      /* ap 24 */
42                          <0x000f6000 0x000f6000 0x001000>,      /* ap 25 */
43                          <0x000f7000 0x000f7000 0x001000>,      /* ap 26 */
44                          <0x00090000 0x00090000 0x008000>,      /* ap 59 */
45                          <0x00098000 0x00098000 0x001000>;      /* ap 60 */
46
47                 target-module@2000 {                    /* 0x4a002000, ap 3 08.0 */
48                         compatible = "ti,sysc-omap4", "ti,sysc";
49                         reg = <0x2000 0x4>;
50                         reg-names = "rev";
51                         #address-cells = <1>;
52                         #size-cells = <1>;
53                         ranges = <0x0 0x2000 0x2000>;
54
55                         scm: scm@0 {
56                                 compatible = "ti,dra7-scm-core", "simple-bus";
57                                 reg = <0 0x2000>;
58                                 #address-cells = <1>;
59                                 #size-cells = <1>;
60                                 ranges = <0 0 0x2000>;
61
62                                 scm_conf: scm_conf@0 {
63                                         compatible = "syscon", "simple-bus";
64                                         reg = <0x0 0x1400>;
65                                         #address-cells = <1>;
66                                         #size-cells = <1>;
67                                         ranges = <0 0x0 0x1400>;
68
69                                         pbias_regulator: pbias_regulator@e00 {
70                                                 compatible = "ti,pbias-dra7", "ti,pbias-omap";
71                                                 reg = <0xe00 0x4>;
72                                                 syscon = <&scm_conf>;
73                                                 pbias_mmc_reg: pbias_mmc_omap5 {
74                                                         regulator-name = "pbias_mmc_omap5";
75                                                         regulator-min-microvolt = <1800000>;
76                                                         regulator-max-microvolt = <3300000>;
77                                                 };
78                                         };
79
80                                         phy_gmii_sel: phy-gmii-sel {
81                                                 compatible = "ti,dra7xx-phy-gmii-sel";
82                                                 reg = <0x554 0x4>;
83                                                 #phy-cells = <1>;
84                                         };
85
86                                         scm_conf_clocks: clocks {
87                                                 #address-cells = <1>;
88                                                 #size-cells = <0>;
89                                         };
90                                 };
91
92                                 dra7_pmx_core: pinmux@1400 {
93                                         compatible = "ti,dra7-padconf",
94                                                      "pinctrl-single";
95                                         reg = <0x1400 0x0468>;
96                                         #address-cells = <1>;
97                                         #size-cells = <0>;
98                                         #pinctrl-cells = <1>;
99                                         #interrupt-cells = <1>;
100                                         interrupt-controller;
101                                         pinctrl-single,register-width = <32>;
102                                         pinctrl-single,function-mask = <0x3fffffff>;
103                                 };
104
105                                 scm_conf1: scm_conf@1c04 {
106                                         compatible = "syscon";
107                                         reg = <0x1c04 0x0020>;
108                                         #syscon-cells = <2>;
109                                 };
110
111                                 scm_conf_pcie: scm_conf@1c24 {
112                                         compatible = "syscon";
113                                         reg = <0x1c24 0x0024>;
114                                 };
115
116                                 sdma_xbar: dma-router@b78 {
117                                         compatible = "ti,dra7-dma-crossbar";
118                                         reg = <0xb78 0xfc>;
119                                         #dma-cells = <1>;
120                                         dma-requests = <205>;
121                                         ti,dma-safe-map = <0>;
122                                         dma-masters = <&sdma>;
123                                 };
124
125                                 edma_xbar: dma-router@c78 {
126                                         compatible = "ti,dra7-dma-crossbar";
127                                         reg = <0xc78 0x7c>;
128                                         #dma-cells = <2>;
129                                         dma-requests = <204>;
130                                         ti,dma-safe-map = <0>;
131                                         dma-masters = <&edma>;
132                                 };
133                         };
134                 };
135
136                 target-module@5000 {                    /* 0x4a005000, ap 5 10.0 */
137                         compatible = "ti,sysc-omap4", "ti,sysc";
138                         reg = <0x5000 0x4>;
139                         reg-names = "rev";
140                         #address-cells = <1>;
141                         #size-cells = <1>;
142                         ranges = <0x0 0x5000 0x1000>;
143
144                         cm_core_aon: cm_core_aon@0 {
145                                 compatible = "ti,dra7-cm-core-aon",
146                                               "simple-bus";
147                                 #address-cells = <1>;
148                                 #size-cells = <1>;
149                                 reg = <0 0x2000>;
150                                 ranges = <0 0 0x2000>;
151
152                                 cm_core_aon_clocks: clocks {
153                                         #address-cells = <1>;
154                                         #size-cells = <0>;
155                                 };
156
157                                 cm_core_aon_clockdomains: clockdomains {
158                                 };
159                         };
160                 };
161
162                 target-module@8000 {                    /* 0x4a008000, ap 7 0e.0 */
163                         compatible = "ti,sysc-omap4", "ti,sysc";
164                         reg = <0x8000 0x4>;
165                         reg-names = "rev";
166                         #address-cells = <1>;
167                         #size-cells = <1>;
168                         ranges = <0x0 0x8000 0x2000>;
169
170                         cm_core: cm_core@0 {
171                                 compatible = "ti,dra7-cm-core", "simple-bus";
172                                 #address-cells = <1>;
173                                 #size-cells = <1>;
174                                 reg = <0 0x3000>;
175                                 ranges = <0 0 0x3000>;
176
177                                 cm_core_clocks: clocks {
178                                         #address-cells = <1>;
179                                         #size-cells = <0>;
180                                 };
181
182                                 cm_core_clockdomains: clockdomains {
183                                 };
184                         };
185                 };
186
187                 target-module@56000 {                   /* 0x4a056000, ap 9 02.0 */
188                         compatible = "ti,sysc-omap2", "ti,sysc";
189                         ti,hwmods = "dma_system";
190                         reg = <0x56000 0x4>,
191                               <0x5602c 0x4>,
192                               <0x56028 0x4>;
193                         reg-names = "rev", "sysc", "syss";
194                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
195                                          SYSC_OMAP2_EMUFREE |
196                                          SYSC_OMAP2_SOFTRESET |
197                                          SYSC_OMAP2_AUTOIDLE)>;
198                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
199                                         <SYSC_IDLE_NO>,
200                                         <SYSC_IDLE_SMART>,
201                                         <SYSC_IDLE_SMART_WKUP>;
202                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
203                                         <SYSC_IDLE_NO>,
204                                         <SYSC_IDLE_SMART>,
205                                         <SYSC_IDLE_SMART_WKUP>;
206                         ti,syss-mask = <1>;
207                         /* Domains (P, C): core_pwrdm, dma_clkdm */
208                         clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
209                         clock-names = "fck";
210                         #address-cells = <1>;
211                         #size-cells = <1>;
212                         ranges = <0x0 0x56000 0x1000>;
213
214                         sdma: dma-controller@0 {
215                                 compatible = "ti,omap4430-sdma";
216                                 reg = <0x0 0x1000>;
217                                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
218                                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
219                                              <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
220                                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
221                                 #dma-cells = <1>;
222                                 dma-channels = <32>;
223                                 dma-requests = <127>;
224                         };
225                 };
226
227                 target-module@5e000 {                   /* 0x4a05e000, ap 11 1a.0 */
228                         compatible = "ti,sysc";
229                         status = "disabled";
230                         #address-cells = <1>;
231                         #size-cells = <1>;
232                         ranges = <0x0 0x5e000 0x2000>;
233                 };
234
235                 target-module@80000 {                   /* 0x4a080000, ap 13 20.0 */
236                         compatible = "ti,sysc-omap2", "ti,sysc";
237                         ti,hwmods = "ocp2scp1";
238                         reg = <0x80000 0x4>,
239                               <0x80010 0x4>,
240                               <0x80014 0x4>;
241                         reg-names = "rev", "sysc", "syss";
242                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
243                                          SYSC_OMAP2_AUTOIDLE)>;
244                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
245                                         <SYSC_IDLE_NO>,
246                                         <SYSC_IDLE_SMART>;
247                         ti,syss-mask = <1>;
248                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
249                         clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
250                         clock-names = "fck";
251                         #address-cells = <1>;
252                         #size-cells = <1>;
253                         ranges = <0x0 0x80000 0x8000>;
254
255                         ocp2scp@0 {
256                                 compatible = "ti,omap-ocp2scp";
257                                 #address-cells = <1>;
258                                 #size-cells = <1>;
259                                 ranges = <0 0 0x8000>;
260                                 reg = <0x0 0x20>;
261
262                                 usb2_phy1: phy@4000 {
263                                         compatible = "ti,dra7x-usb2", "ti,omap-usb2";
264                                         reg = <0x4000 0x400>;
265                                         syscon-phy-power = <&scm_conf 0x300>;
266                                         clocks = <&usb_phy1_always_on_clk32k>,
267                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
268                                         clock-names =   "wkupclk",
269                                                         "refclk";
270                                         #phy-cells = <0>;
271                                 };
272
273                                 usb2_phy2: phy@5000 {
274                                         compatible = "ti,dra7x-usb2-phy2",
275                                                      "ti,omap-usb2";
276                                         reg = <0x5000 0x400>;
277                                         syscon-phy-power = <&scm_conf 0xe74>;
278                                         clocks = <&usb_phy2_always_on_clk32k>,
279                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
280                                         clock-names =   "wkupclk",
281                                                         "refclk";
282                                         #phy-cells = <0>;
283                                 };
284
285                                 usb3_phy1: phy@4400 {
286                                         compatible = "ti,omap-usb3";
287                                         reg = <0x4400 0x80>,
288                                               <0x4800 0x64>,
289                                               <0x4c00 0x40>;
290                                         reg-names = "phy_rx", "phy_tx", "pll_ctrl";
291                                         syscon-phy-power = <&scm_conf 0x370>;
292                                         clocks = <&usb_phy3_always_on_clk32k>,
293                                                  <&sys_clkin1>,
294                                                  <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
295                                         clock-names =   "wkupclk",
296                                                         "sysclk",
297                                                         "refclk";
298                                         #phy-cells = <0>;
299                                 };
300                         };
301                 };
302
303                 target-module@90000 {                   /* 0x4a090000, ap 59 42.0 */
304                         compatible = "ti,sysc-omap2", "ti,sysc";
305                         ti,hwmods = "ocp2scp3";
306                         reg = <0x90000 0x4>,
307                               <0x90010 0x4>,
308                               <0x90014 0x4>;
309                         reg-names = "rev", "sysc", "syss";
310                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
311                                          SYSC_OMAP2_AUTOIDLE)>;
312                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
313                                         <SYSC_IDLE_NO>,
314                                         <SYSC_IDLE_SMART>;
315                         ti,syss-mask = <1>;
316                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
317                         clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
318                         clock-names = "fck";
319                         #address-cells = <1>;
320                         #size-cells = <1>;
321                         ranges = <0x0 0x90000 0x8000>;
322
323                         ocp2scp@0 {
324                                 compatible = "ti,omap-ocp2scp";
325                                 #address-cells = <1>;
326                                 #size-cells = <1>;
327                                 ranges = <0 0 0x8000>;
328                                 reg = <0x0 0x20>;
329
330                                 pcie1_phy: pciephy@4000 {
331                                         compatible = "ti,phy-pipe3-pcie";
332                                         reg = <0x4000 0x80>, /* phy_rx */
333                                               <0x4400 0x64>; /* phy_tx */
334                                         reg-names = "phy_rx", "phy_tx";
335                                         syscon-phy-power = <&scm_conf_pcie 0x1c>;
336                                         syscon-pcs = <&scm_conf_pcie 0x10>;
337                                         clocks = <&dpll_pcie_ref_ck>,
338                                                  <&dpll_pcie_ref_m2ldo_ck>,
339                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
340                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
341                                                  <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
342                                                  <&optfclk_pciephy_div>,
343                                                  <&sys_clkin1>;
344                                         clock-names = "dpll_ref", "dpll_ref_m2",
345                                                       "wkupclk", "refclk",
346                                                       "div-clk", "phy-div", "sysclk";
347                                         #phy-cells = <0>;
348                                 };
349
350                                 pcie2_phy: pciephy@5000 {
351                                         compatible = "ti,phy-pipe3-pcie";
352                                         reg = <0x5000 0x80>, /* phy_rx */
353                                               <0x5400 0x64>; /* phy_tx */
354                                         reg-names = "phy_rx", "phy_tx";
355                                         syscon-phy-power = <&scm_conf_pcie 0x20>;
356                                         syscon-pcs = <&scm_conf_pcie 0x10>;
357                                         clocks = <&dpll_pcie_ref_ck>,
358                                                  <&dpll_pcie_ref_m2ldo_ck>,
359                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
360                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
361                                                  <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
362                                                  <&optfclk_pciephy_div>,
363                                                  <&sys_clkin1>;
364                                         clock-names = "dpll_ref", "dpll_ref_m2",
365                                                       "wkupclk", "refclk",
366                                                       "div-clk", "phy-div", "sysclk";
367                                         #phy-cells = <0>;
368                                         status = "disabled";
369                                 };
370
371                                 sata_phy: phy@6000 {
372                                         compatible = "ti,phy-pipe3-sata";
373                                         reg = <0x6000 0x80>, /* phy_rx */
374                                               <0x6400 0x64>, /* phy_tx */
375                                               <0x6800 0x40>; /* pll_ctrl */
376                                         reg-names = "phy_rx", "phy_tx", "pll_ctrl";
377                                         syscon-phy-power = <&scm_conf 0x374>;
378                                         clocks = <&sys_clkin1>,
379                                                  <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
380                                         clock-names = "sysclk", "refclk";
381                                         syscon-pllreset = <&scm_conf 0x3fc>;
382                                         #phy-cells = <0>;
383                                 };
384                         };
385                 };
386
387                 target-module@a0000 {                   /* 0x4a0a0000, ap 15 40.0 */
388                         compatible = "ti,sysc";
389                         status = "disabled";
390                         #address-cells = <1>;
391                         #size-cells = <1>;
392                         ranges = <0x0 0xa0000 0x8000>;
393                 };
394
395                 target-module@d9000 {                   /* 0x4a0d9000, ap 17 72.0 */
396                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
397                         ti,hwmods = "smartreflex_mpu";
398                         reg = <0xd9038 0x4>;
399                         reg-names = "sysc";
400                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
401                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
402                                         <SYSC_IDLE_NO>,
403                                         <SYSC_IDLE_SMART>,
404                                         <SYSC_IDLE_SMART_WKUP>;
405                         /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
406                         clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
407                         clock-names = "fck";
408                         #address-cells = <1>;
409                         #size-cells = <1>;
410                         ranges = <0x0 0xd9000 0x1000>;
411
412                         /* SmartReflex child device marked reserved in TRM */
413                 };
414
415                 target-module@dd000 {                   /* 0x4a0dd000, ap 19 18.0 */
416                         compatible = "ti,sysc-omap4-sr", "ti,sysc";
417                         ti,hwmods = "smartreflex_core";
418                         reg = <0xdd038 0x4>;
419                         reg-names = "sysc";
420                         ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
421                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
422                                         <SYSC_IDLE_NO>,
423                                         <SYSC_IDLE_SMART>,
424                                         <SYSC_IDLE_SMART_WKUP>;
425                         /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
426                         clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
427                         clock-names = "fck";
428                         #address-cells = <1>;
429                         #size-cells = <1>;
430                         ranges = <0x0 0xdd000 0x1000>;
431
432                         /* SmartReflex child device marked reserved in TRM */
433                 };
434
435                 target-module@e0000 {                   /* 0x4a0e0000, ap 21 28.0 */
436                         compatible = "ti,sysc";
437                         status = "disabled";
438                         #address-cells = <1>;
439                         #size-cells = <1>;
440                         ranges = <0x0 0xe0000 0x1000>;
441                 };
442
443                 target-module@f4000 {                   /* 0x4a0f4000, ap 23 04.0 */
444                         compatible = "ti,sysc-omap4", "ti,sysc";
445                         ti,hwmods = "mailbox1";
446                         reg = <0xf4000 0x4>,
447                               <0xf4010 0x4>;
448                         reg-names = "rev", "sysc";
449                         ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
450                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
451                                         <SYSC_IDLE_NO>,
452                                         <SYSC_IDLE_SMART>;
453                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
454                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
455                         clock-names = "fck";
456                         #address-cells = <1>;
457                         #size-cells = <1>;
458                         ranges = <0x0 0xf4000 0x1000>;
459
460                         mailbox1: mailbox@0 {
461                                 compatible = "ti,omap4-mailbox";
462                                 reg = <0x0 0x200>;
463                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
464                                              <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
465                                              <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
466                                 #mbox-cells = <1>;
467                                 ti,mbox-num-users = <3>;
468                                 ti,mbox-num-fifos = <8>;
469                                 status = "disabled";
470                         };
471                 };
472
473                 target-module@f6000 {                   /* 0x4a0f6000, ap 25 78.0 */
474                         compatible = "ti,sysc-omap2", "ti,sysc";
475                         ti,hwmods = "spinlock";
476                         reg = <0xf6000 0x4>,
477                               <0xf6010 0x4>,
478                               <0xf6014 0x4>;
479                         reg-names = "rev", "sysc", "syss";
480                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
481                                          SYSC_OMAP2_SOFTRESET |
482                                          SYSC_OMAP2_AUTOIDLE)>;
483                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
484                                         <SYSC_IDLE_NO>,
485                                         <SYSC_IDLE_SMART>;
486                         ti,syss-mask = <1>;
487                         /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
488                         clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
489                         clock-names = "fck";
490                         #address-cells = <1>;
491                         #size-cells = <1>;
492                         ranges = <0x0 0xf6000 0x1000>;
493
494                         hwspinlock: spinlock@0 {
495                                 compatible = "ti,omap4-hwspinlock";
496                                 reg = <0x0 0x1000>;
497                                 #hwlock-cells = <1>;
498                         };
499                 };
500         };
501
502         segment@100000 {                                        /* 0x4a100000 */
503                 compatible = "simple-bus";
504                 #address-cells = <1>;
505                 #size-cells = <1>;
506                 ranges = <0x00002000 0x00102000 0x001000>,      /* ap 27 */
507                          <0x00003000 0x00103000 0x001000>,      /* ap 28 */
508                          <0x00008000 0x00108000 0x001000>,      /* ap 29 */
509                          <0x00009000 0x00109000 0x001000>,      /* ap 30 */
510                          <0x00040000 0x00140000 0x010000>,      /* ap 31 */
511                          <0x00050000 0x00150000 0x001000>,      /* ap 32 */
512                          <0x00051000 0x00151000 0x001000>,      /* ap 33 */
513                          <0x00052000 0x00152000 0x001000>,      /* ap 34 */
514                          <0x00053000 0x00153000 0x001000>,      /* ap 35 */
515                          <0x00054000 0x00154000 0x001000>,      /* ap 36 */
516                          <0x00055000 0x00155000 0x001000>,      /* ap 37 */
517                          <0x00056000 0x00156000 0x001000>,      /* ap 38 */
518                          <0x00057000 0x00157000 0x001000>,      /* ap 39 */
519                          <0x00058000 0x00158000 0x001000>,      /* ap 40 */
520                          <0x0005b000 0x0015b000 0x001000>,      /* ap 41 */
521                          <0x0005c000 0x0015c000 0x001000>,      /* ap 42 */
522                          <0x0005d000 0x0015d000 0x001000>,      /* ap 45 */
523                          <0x0005e000 0x0015e000 0x001000>,      /* ap 46 */
524                          <0x0005f000 0x0015f000 0x001000>,      /* ap 47 */
525                          <0x00060000 0x00160000 0x001000>,      /* ap 48 */
526                          <0x00061000 0x00161000 0x001000>,      /* ap 49 */
527                          <0x00062000 0x00162000 0x001000>,      /* ap 50 */
528                          <0x00063000 0x00163000 0x001000>,      /* ap 51 */
529                          <0x00064000 0x00164000 0x001000>,      /* ap 52 */
530                          <0x00065000 0x00165000 0x001000>,      /* ap 53 */
531                          <0x00066000 0x00166000 0x001000>,      /* ap 54 */
532                          <0x00067000 0x00167000 0x001000>,      /* ap 55 */
533                          <0x00068000 0x00168000 0x001000>,      /* ap 56 */
534                          <0x0006d000 0x0016d000 0x001000>,      /* ap 57 */
535                          <0x0006e000 0x0016e000 0x001000>,      /* ap 58 */
536                          <0x00071000 0x00171000 0x001000>,      /* ap 61 */
537                          <0x00072000 0x00172000 0x001000>,      /* ap 62 */
538                          <0x00073000 0x00173000 0x001000>,      /* ap 63 */
539                          <0x00074000 0x00174000 0x001000>,      /* ap 64 */
540                          <0x00075000 0x00175000 0x001000>,      /* ap 65 */
541                          <0x00076000 0x00176000 0x001000>,      /* ap 66 */
542                          <0x00077000 0x00177000 0x001000>,      /* ap 67 */
543                          <0x00078000 0x00178000 0x001000>,      /* ap 68 */
544                          <0x00081000 0x00181000 0x001000>,      /* ap 69 */
545                          <0x00082000 0x00182000 0x001000>,      /* ap 70 */
546                          <0x00083000 0x00183000 0x001000>,      /* ap 71 */
547                          <0x00084000 0x00184000 0x001000>,      /* ap 72 */
548                          <0x00085000 0x00185000 0x001000>,      /* ap 73 */
549                          <0x00086000 0x00186000 0x001000>,      /* ap 74 */
550                          <0x00087000 0x00187000 0x001000>,      /* ap 75 */
551                          <0x00088000 0x00188000 0x001000>,      /* ap 76 */
552                          <0x00069000 0x00169000 0x001000>,      /* ap 103 */
553                          <0x0006a000 0x0016a000 0x001000>,      /* ap 104 */
554                          <0x00079000 0x00179000 0x001000>,      /* ap 105 */
555                          <0x0007a000 0x0017a000 0x001000>,      /* ap 106 */
556                          <0x0006b000 0x0016b000 0x001000>,      /* ap 107 */
557                          <0x0006c000 0x0016c000 0x001000>,      /* ap 108 */
558                          <0x0007b000 0x0017b000 0x001000>,      /* ap 121 */
559                          <0x0007c000 0x0017c000 0x001000>,      /* ap 122 */
560                          <0x0007d000 0x0017d000 0x001000>,      /* ap 123 */
561                          <0x0007e000 0x0017e000 0x001000>,      /* ap 124 */
562                          <0x00059000 0x00159000 0x001000>,      /* ap 125 */
563                          <0x0005a000 0x0015a000 0x001000>;      /* ap 126 */
564
565                 target-module@2000 {                    /* 0x4a102000, ap 27 3c.0 */
566                         compatible = "ti,sysc";
567                         status = "disabled";
568                         #address-cells = <1>;
569                         #size-cells = <1>;
570                         ranges = <0x0 0x2000 0x1000>;
571                 };
572
573                 target-module@8000 {                    /* 0x4a108000, ap 29 1e.0 */
574                         compatible = "ti,sysc";
575                         status = "disabled";
576                         #address-cells = <1>;
577                         #size-cells = <1>;
578                         ranges = <0x0 0x8000 0x1000>;
579                 };
580
581                 target-module@40000 {                   /* 0x4a140000, ap 31 06.0 */
582                         compatible = "ti,sysc";
583                         status = "disabled";
584                         #address-cells = <1>;
585                         #size-cells = <1>;
586                         ranges = <0x0 0x40000 0x10000>;
587                 };
588
589                 target-module@51000 {                   /* 0x4a151000, ap 33 50.0 */
590                         compatible = "ti,sysc";
591                         status = "disabled";
592                         #address-cells = <1>;
593                         #size-cells = <1>;
594                         ranges = <0x0 0x51000 0x1000>;
595                 };
596
597                 target-module@53000 {                   /* 0x4a153000, ap 35 54.0 */
598                         compatible = "ti,sysc";
599                         status = "disabled";
600                         #address-cells = <1>;
601                         #size-cells = <1>;
602                         ranges = <0x0 0x53000 0x1000>;
603                 };
604
605                 target-module@55000 {                   /* 0x4a155000, ap 37 46.0 */
606                         compatible = "ti,sysc";
607                         status = "disabled";
608                         #address-cells = <1>;
609                         #size-cells = <1>;
610                         ranges = <0x0 0x55000 0x1000>;
611                 };
612
613                 target-module@57000 {                   /* 0x4a157000, ap 39 58.0 */
614                         compatible = "ti,sysc";
615                         status = "disabled";
616                         #address-cells = <1>;
617                         #size-cells = <1>;
618                         ranges = <0x0 0x57000 0x1000>;
619                 };
620
621                 target-module@59000 {                   /* 0x4a159000, ap 125 6a.0 */
622                         compatible = "ti,sysc";
623                         status = "disabled";
624                         #address-cells = <1>;
625                         #size-cells = <1>;
626                         ranges = <0x0 0x59000 0x1000>;
627                 };
628
629                 target-module@5b000 {                   /* 0x4a15b000, ap 41 60.0 */
630                         compatible = "ti,sysc";
631                         status = "disabled";
632                         #address-cells = <1>;
633                         #size-cells = <1>;
634                         ranges = <0x0 0x5b000 0x1000>;
635                 };
636
637                 target-module@5d000 {                   /* 0x4a15d000, ap 45 3a.0 */
638                         compatible = "ti,sysc";
639                         status = "disabled";
640                         #address-cells = <1>;
641                         #size-cells = <1>;
642                         ranges = <0x0 0x5d000 0x1000>;
643                 };
644
645                 target-module@5f000 {                   /* 0x4a15f000, ap 47 56.0 */
646                         compatible = "ti,sysc";
647                         status = "disabled";
648                         #address-cells = <1>;
649                         #size-cells = <1>;
650                         ranges = <0x0 0x5f000 0x1000>;
651                 };
652
653                 target-module@61000 {                   /* 0x4a161000, ap 49 32.0 */
654                         compatible = "ti,sysc";
655                         status = "disabled";
656                         #address-cells = <1>;
657                         #size-cells = <1>;
658                         ranges = <0x0 0x61000 0x1000>;
659                 };
660
661                 target-module@63000 {                   /* 0x4a163000, ap 51 5c.0 */
662                         compatible = "ti,sysc";
663                         status = "disabled";
664                         #address-cells = <1>;
665                         #size-cells = <1>;
666                         ranges = <0x0 0x63000 0x1000>;
667                 };
668
669                 target-module@65000 {                   /* 0x4a165000, ap 53 4e.0 */
670                         compatible = "ti,sysc";
671                         status = "disabled";
672                         #address-cells = <1>;
673                         #size-cells = <1>;
674                         ranges = <0x0 0x65000 0x1000>;
675                 };
676
677                 target-module@67000 {                   /* 0x4a167000, ap 55 5e.0 */
678                         compatible = "ti,sysc";
679                         status = "disabled";
680                         #address-cells = <1>;
681                         #size-cells = <1>;
682                         ranges = <0x0 0x67000 0x1000>;
683                 };
684
685                 target-module@69000 {                   /* 0x4a169000, ap 103 4a.0 */
686                         compatible = "ti,sysc";
687                         status = "disabled";
688                         #address-cells = <1>;
689                         #size-cells = <1>;
690                         ranges = <0x0 0x69000 0x1000>;
691                 };
692
693                 target-module@6b000 {                   /* 0x4a16b000, ap 107 52.0 */
694                         compatible = "ti,sysc";
695                         status = "disabled";
696                         #address-cells = <1>;
697                         #size-cells = <1>;
698                         ranges = <0x0 0x6b000 0x1000>;
699                 };
700
701                 target-module@6d000 {                   /* 0x4a16d000, ap 57 68.0 */
702                         compatible = "ti,sysc";
703                         status = "disabled";
704                         #address-cells = <1>;
705                         #size-cells = <1>;
706                         ranges = <0x0 0x6d000 0x1000>;
707                 };
708
709                 target-module@71000 {                   /* 0x4a171000, ap 61 48.0 */
710                         compatible = "ti,sysc";
711                         status = "disabled";
712                         #address-cells = <1>;
713                         #size-cells = <1>;
714                         ranges = <0x0 0x71000 0x1000>;
715                 };
716
717                 target-module@73000 {                   /* 0x4a173000, ap 63 2a.0 */
718                         compatible = "ti,sysc";
719                         status = "disabled";
720                         #address-cells = <1>;
721                         #size-cells = <1>;
722                         ranges = <0x0 0x73000 0x1000>;
723                 };
724
725                 target-module@75000 {                   /* 0x4a175000, ap 65 64.0 */
726                         compatible = "ti,sysc";
727                         status = "disabled";
728                         #address-cells = <1>;
729                         #size-cells = <1>;
730                         ranges = <0x0 0x75000 0x1000>;
731                 };
732
733                 target-module@77000 {                   /* 0x4a177000, ap 67 66.0 */
734                         compatible = "ti,sysc";
735                         status = "disabled";
736                         #address-cells = <1>;
737                         #size-cells = <1>;
738                         ranges = <0x0 0x77000 0x1000>;
739                 };
740
741                 target-module@79000 {                   /* 0x4a179000, ap 105 34.0 */
742                         compatible = "ti,sysc";
743                         status = "disabled";
744                         #address-cells = <1>;
745                         #size-cells = <1>;
746                         ranges = <0x0 0x79000 0x1000>;
747                 };
748
749                 target-module@7b000 {                   /* 0x4a17b000, ap 121 7c.0 */
750                         compatible = "ti,sysc";
751                         status = "disabled";
752                         #address-cells = <1>;
753                         #size-cells = <1>;
754                         ranges = <0x0 0x7b000 0x1000>;
755                 };
756
757                 target-module@7d000 {                   /* 0x4a17d000, ap 123 7e.0 */
758                         compatible = "ti,sysc";
759                         status = "disabled";
760                         #address-cells = <1>;
761                         #size-cells = <1>;
762                         ranges = <0x0 0x7d000 0x1000>;
763                 };
764
765                 target-module@81000 {                   /* 0x4a181000, ap 69 26.0 */
766                         compatible = "ti,sysc";
767                         status = "disabled";
768                         #address-cells = <1>;
769                         #size-cells = <1>;
770                         ranges = <0x0 0x81000 0x1000>;
771                 };
772
773                 target-module@83000 {                   /* 0x4a183000, ap 71 2e.0 */
774                         compatible = "ti,sysc";
775                         status = "disabled";
776                         #address-cells = <1>;
777                         #size-cells = <1>;
778                         ranges = <0x0 0x83000 0x1000>;
779                 };
780
781                 target-module@85000 {                   /* 0x4a185000, ap 73 36.0 */
782                         compatible = "ti,sysc";
783                         status = "disabled";
784                         #address-cells = <1>;
785                         #size-cells = <1>;
786                         ranges = <0x0 0x85000 0x1000>;
787                 };
788
789                 target-module@87000 {                   /* 0x4a187000, ap 75 74.0 */
790                         compatible = "ti,sysc";
791                         status = "disabled";
792                         #address-cells = <1>;
793                         #size-cells = <1>;
794                         ranges = <0x0 0x87000 0x1000>;
795                 };
796         };
797
798         segment@200000 {                                        /* 0x4a200000 */
799                 compatible = "simple-bus";
800                 #address-cells = <1>;
801                 #size-cells = <1>;
802                 ranges = <0x00018000 0x00218000 0x001000>,      /* ap 43 */
803                          <0x00019000 0x00219000 0x001000>,      /* ap 44 */
804                          <0x00000000 0x00200000 0x001000>,      /* ap 77 */
805                          <0x00001000 0x00201000 0x001000>,      /* ap 78 */
806                          <0x0000a000 0x0020a000 0x001000>,      /* ap 79 */
807                          <0x0000b000 0x0020b000 0x001000>,      /* ap 80 */
808                          <0x0000c000 0x0020c000 0x001000>,      /* ap 81 */
809                          <0x0000d000 0x0020d000 0x001000>,      /* ap 82 */
810                          <0x0000e000 0x0020e000 0x001000>,      /* ap 83 */
811                          <0x0000f000 0x0020f000 0x001000>,      /* ap 84 */
812                          <0x00010000 0x00210000 0x001000>,      /* ap 85 */
813                          <0x00011000 0x00211000 0x001000>,      /* ap 86 */
814                          <0x00012000 0x00212000 0x001000>,      /* ap 87 */
815                          <0x00013000 0x00213000 0x001000>,      /* ap 88 */
816                          <0x00014000 0x00214000 0x001000>,      /* ap 89 */
817                          <0x00015000 0x00215000 0x001000>,      /* ap 90 */
818                          <0x0002a000 0x0022a000 0x001000>,      /* ap 91 */
819                          <0x0002b000 0x0022b000 0x001000>,      /* ap 92 */
820                          <0x0001c000 0x0021c000 0x001000>,      /* ap 93 */
821                          <0x0001d000 0x0021d000 0x001000>,      /* ap 94 */
822                          <0x0001e000 0x0021e000 0x001000>,      /* ap 95 */
823                          <0x0001f000 0x0021f000 0x001000>,      /* ap 96 */
824                          <0x00020000 0x00220000 0x001000>,      /* ap 97 */
825                          <0x00021000 0x00221000 0x001000>,      /* ap 98 */
826                          <0x00024000 0x00224000 0x001000>,      /* ap 99 */
827                          <0x00025000 0x00225000 0x001000>,      /* ap 100 */
828                          <0x00026000 0x00226000 0x001000>,      /* ap 101 */
829                          <0x00027000 0x00227000 0x001000>,      /* ap 102 */
830                          <0x0002c000 0x0022c000 0x001000>,      /* ap 109 */
831                          <0x0002d000 0x0022d000 0x001000>,      /* ap 110 */
832                          <0x0002e000 0x0022e000 0x001000>,      /* ap 111 */
833                          <0x0002f000 0x0022f000 0x001000>,      /* ap 112 */
834                          <0x00030000 0x00230000 0x001000>,      /* ap 113 */
835                          <0x00031000 0x00231000 0x001000>,      /* ap 114 */
836                          <0x00032000 0x00232000 0x001000>,      /* ap 115 */
837                          <0x00033000 0x00233000 0x001000>,      /* ap 116 */
838                          <0x00034000 0x00234000 0x001000>,      /* ap 117 */
839                          <0x00035000 0x00235000 0x001000>,      /* ap 118 */
840                          <0x00036000 0x00236000 0x001000>,      /* ap 119 */
841                          <0x00037000 0x00237000 0x001000>,      /* ap 120 */
842                          <0x0001a000 0x0021a000 0x001000>,      /* ap 127 */
843                          <0x0001b000 0x0021b000 0x001000>;      /* ap 128 */
844
845                 target-module@0 {                       /* 0x4a200000, ap 77 3e.0 */
846                         compatible = "ti,sysc";
847                         status = "disabled";
848                         #address-cells = <1>;
849                         #size-cells = <1>;
850                         ranges = <0x0 0x0 0x1000>;
851                 };
852
853                 target-module@a000 {                    /* 0x4a20a000, ap 79 30.0 */
854                         compatible = "ti,sysc";
855                         status = "disabled";
856                         #address-cells = <1>;
857                         #size-cells = <1>;
858                         ranges = <0x0 0xa000 0x1000>;
859                 };
860
861                 target-module@c000 {                    /* 0x4a20c000, ap 81 0c.0 */
862                         compatible = "ti,sysc";
863                         status = "disabled";
864                         #address-cells = <1>;
865                         #size-cells = <1>;
866                         ranges = <0x0 0xc000 0x1000>;
867                 };
868
869                 target-module@e000 {                    /* 0x4a20e000, ap 83 22.0 */
870                         compatible = "ti,sysc";
871                         status = "disabled";
872                         #address-cells = <1>;
873                         #size-cells = <1>;
874                         ranges = <0x0 0xe000 0x1000>;
875                 };
876
877                 target-module@10000 {                   /* 0x4a210000, ap 85 14.0 */
878                         compatible = "ti,sysc";
879                         status = "disabled";
880                         #address-cells = <1>;
881                         #size-cells = <1>;
882                         ranges = <0x0 0x10000 0x1000>;
883                 };
884
885                 target-module@12000 {                   /* 0x4a212000, ap 87 16.0 */
886                         compatible = "ti,sysc";
887                         status = "disabled";
888                         #address-cells = <1>;
889                         #size-cells = <1>;
890                         ranges = <0x0 0x12000 0x1000>;
891                 };
892
893                 target-module@14000 {                   /* 0x4a214000, ap 89 1c.0 */
894                         compatible = "ti,sysc";
895                         status = "disabled";
896                         #address-cells = <1>;
897                         #size-cells = <1>;
898                         ranges = <0x0 0x14000 0x1000>;
899                 };
900
901                 target-module@18000 {                   /* 0x4a218000, ap 43 12.0 */
902                         compatible = "ti,sysc";
903                         status = "disabled";
904                         #address-cells = <1>;
905                         #size-cells = <1>;
906                         ranges = <0x0 0x18000 0x1000>;
907                 };
908
909                 target-module@1a000 {                   /* 0x4a21a000, ap 127 7a.0 */
910                         compatible = "ti,sysc";
911                         status = "disabled";
912                         #address-cells = <1>;
913                         #size-cells = <1>;
914                         ranges = <0x0 0x1a000 0x1000>;
915                 };
916
917                 target-module@1c000 {                   /* 0x4a21c000, ap 93 38.0 */
918                         compatible = "ti,sysc";
919                         status = "disabled";
920                         #address-cells = <1>;
921                         #size-cells = <1>;
922                         ranges = <0x0 0x1c000 0x1000>;
923                 };
924
925                 target-module@1e000 {                   /* 0x4a21e000, ap 95 0a.0 */
926                         compatible = "ti,sysc";
927                         status = "disabled";
928                         #address-cells = <1>;
929                         #size-cells = <1>;
930                         ranges = <0x0 0x1e000 0x1000>;
931                 };
932
933                 target-module@20000 {                   /* 0x4a220000, ap 97 24.0 */
934                         compatible = "ti,sysc";
935                         status = "disabled";
936                         #address-cells = <1>;
937                         #size-cells = <1>;
938                         ranges = <0x0 0x20000 0x1000>;
939                 };
940
941                 target-module@24000 {                   /* 0x4a224000, ap 99 44.0 */
942                         compatible = "ti,sysc";
943                         status = "disabled";
944                         #address-cells = <1>;
945                         #size-cells = <1>;
946                         ranges = <0x0 0x24000 0x1000>;
947                 };
948
949                 target-module@26000 {                   /* 0x4a226000, ap 101 2c.0 */
950                         compatible = "ti,sysc";
951                         status = "disabled";
952                         #address-cells = <1>;
953                         #size-cells = <1>;
954                         ranges = <0x0 0x26000 0x1000>;
955                 };
956
957                 target-module@2a000 {                   /* 0x4a22a000, ap 91 4c.0 */
958                         compatible = "ti,sysc";
959                         status = "disabled";
960                         #address-cells = <1>;
961                         #size-cells = <1>;
962                         ranges = <0x0 0x2a000 0x1000>;
963                 };
964
965                 target-module@2c000 {                   /* 0x4a22c000, ap 109 6c.0 */
966                         compatible = "ti,sysc";
967                         status = "disabled";
968                         #address-cells = <1>;
969                         #size-cells = <1>;
970                         ranges = <0x0 0x2c000 0x1000>;
971                 };
972
973                 target-module@2e000 {                   /* 0x4a22e000, ap 111 6e.0 */
974                         compatible = "ti,sysc";
975                         status = "disabled";
976                         #address-cells = <1>;
977                         #size-cells = <1>;
978                         ranges = <0x0 0x2e000 0x1000>;
979                 };
980
981                 target-module@30000 {                   /* 0x4a230000, ap 113 70.0 */
982                         compatible = "ti,sysc";
983                         status = "disabled";
984                         #address-cells = <1>;
985                         #size-cells = <1>;
986                         ranges = <0x0 0x30000 0x1000>;
987                 };
988
989                 target-module@32000 {                   /* 0x4a232000, ap 115 5a.0 */
990                         compatible = "ti,sysc";
991                         status = "disabled";
992                         #address-cells = <1>;
993                         #size-cells = <1>;
994                         ranges = <0x0 0x32000 0x1000>;
995                 };
996
997                 target-module@34000 {                   /* 0x4a234000, ap 117 76.1 */
998                         compatible = "ti,sysc";
999                         status = "disabled";
1000                         #address-cells = <1>;
1001                         #size-cells = <1>;
1002                         ranges = <0x0 0x34000 0x1000>;
1003                 };
1004
1005                 target-module@36000 {                   /* 0x4a236000, ap 119 62.0 */
1006                         compatible = "ti,sysc";
1007                         status = "disabled";
1008                         #address-cells = <1>;
1009                         #size-cells = <1>;
1010                         ranges = <0x0 0x36000 0x1000>;
1011                 };
1012         };
1013 };
1014
1015 &l4_per1 {                                              /* 0x48000000 */
1016         compatible = "ti,dra7-l4-per1", "simple-bus";
1017         reg = <0x48000000 0x800>,
1018               <0x48000800 0x800>,
1019               <0x48001000 0x400>,
1020               <0x48001400 0x400>,
1021               <0x48001800 0x400>,
1022               <0x48001c00 0x400>;
1023         reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
1024         #address-cells = <1>;
1025         #size-cells = <1>;
1026         ranges = <0x00000000 0x48000000 0x200000>,      /* segment 0 */
1027                  <0x00200000 0x48200000 0x200000>;      /* segment 1 */
1028
1029         segment@0 {                                     /* 0x48000000 */
1030                 compatible = "simple-bus";
1031                 #address-cells = <1>;
1032                 #size-cells = <1>;
1033                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
1034                          <0x00001000 0x00001000 0x000400>,      /* ap 1 */
1035                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
1036                          <0x00020000 0x00020000 0x001000>,      /* ap 3 */
1037                          <0x00021000 0x00021000 0x001000>,      /* ap 4 */
1038                          <0x00032000 0x00032000 0x001000>,      /* ap 5 */
1039                          <0x00033000 0x00033000 0x001000>,      /* ap 6 */
1040                          <0x00034000 0x00034000 0x001000>,      /* ap 7 */
1041                          <0x00035000 0x00035000 0x001000>,      /* ap 8 */
1042                          <0x00036000 0x00036000 0x001000>,      /* ap 9 */
1043                          <0x00037000 0x00037000 0x001000>,      /* ap 10 */
1044                          <0x0003e000 0x0003e000 0x001000>,      /* ap 11 */
1045                          <0x0003f000 0x0003f000 0x001000>,      /* ap 12 */
1046                          <0x00055000 0x00055000 0x001000>,      /* ap 13 */
1047                          <0x00056000 0x00056000 0x001000>,      /* ap 14 */
1048                          <0x00057000 0x00057000 0x001000>,      /* ap 15 */
1049                          <0x00058000 0x00058000 0x001000>,      /* ap 16 */
1050                          <0x00059000 0x00059000 0x001000>,      /* ap 17 */
1051                          <0x0005a000 0x0005a000 0x001000>,      /* ap 18 */
1052                          <0x0005b000 0x0005b000 0x001000>,      /* ap 19 */
1053                          <0x0005c000 0x0005c000 0x001000>,      /* ap 20 */
1054                          <0x0005d000 0x0005d000 0x001000>,      /* ap 21 */
1055                          <0x0005e000 0x0005e000 0x001000>,      /* ap 22 */
1056                          <0x00060000 0x00060000 0x001000>,      /* ap 23 */
1057                          <0x0006a000 0x0006a000 0x001000>,      /* ap 24 */
1058                          <0x0006b000 0x0006b000 0x001000>,      /* ap 25 */
1059                          <0x0006c000 0x0006c000 0x001000>,      /* ap 26 */
1060                          <0x0006d000 0x0006d000 0x001000>,      /* ap 27 */
1061                          <0x0006e000 0x0006e000 0x001000>,      /* ap 28 */
1062                          <0x0006f000 0x0006f000 0x001000>,      /* ap 29 */
1063                          <0x00070000 0x00070000 0x001000>,      /* ap 30 */
1064                          <0x00071000 0x00071000 0x001000>,      /* ap 31 */
1065                          <0x00072000 0x00072000 0x001000>,      /* ap 32 */
1066                          <0x00073000 0x00073000 0x001000>,      /* ap 33 */
1067                          <0x00061000 0x00061000 0x001000>,      /* ap 34 */
1068                          <0x00053000 0x00053000 0x001000>,      /* ap 35 */
1069                          <0x00054000 0x00054000 0x001000>,      /* ap 36 */
1070                          <0x000b2000 0x000b2000 0x001000>,      /* ap 37 */
1071                          <0x000b3000 0x000b3000 0x001000>,      /* ap 38 */
1072                          <0x00078000 0x00078000 0x001000>,      /* ap 39 */
1073                          <0x00079000 0x00079000 0x001000>,      /* ap 40 */
1074                          <0x00086000 0x00086000 0x001000>,      /* ap 41 */
1075                          <0x00087000 0x00087000 0x001000>,      /* ap 42 */
1076                          <0x00088000 0x00088000 0x001000>,      /* ap 43 */
1077                          <0x00089000 0x00089000 0x001000>,      /* ap 44 */
1078                          <0x00051000 0x00051000 0x001000>,      /* ap 45 */
1079                          <0x00052000 0x00052000 0x001000>,      /* ap 46 */
1080                          <0x00098000 0x00098000 0x001000>,      /* ap 47 */
1081                          <0x00099000 0x00099000 0x001000>,      /* ap 48 */
1082                          <0x0009a000 0x0009a000 0x001000>,      /* ap 49 */
1083                          <0x0009b000 0x0009b000 0x001000>,      /* ap 50 */
1084                          <0x0009c000 0x0009c000 0x001000>,      /* ap 51 */
1085                          <0x0009d000 0x0009d000 0x001000>,      /* ap 52 */
1086                          <0x00068000 0x00068000 0x001000>,      /* ap 53 */
1087                          <0x00069000 0x00069000 0x001000>,      /* ap 54 */
1088                          <0x00090000 0x00090000 0x002000>,      /* ap 55 */
1089                          <0x00092000 0x00092000 0x001000>,      /* ap 56 */
1090                          <0x000a4000 0x000a4000 0x001000>,      /* ap 57 */
1091                          <0x000a6000 0x000a6000 0x001000>,      /* ap 58 */
1092                          <0x000a8000 0x000a8000 0x004000>,      /* ap 59 */
1093                          <0x000ac000 0x000ac000 0x001000>,      /* ap 60 */
1094                          <0x000ad000 0x000ad000 0x001000>,      /* ap 61 */
1095                          <0x000ae000 0x000ae000 0x001000>,      /* ap 62 */
1096                          <0x00066000 0x00066000 0x001000>,      /* ap 63 */
1097                          <0x00067000 0x00067000 0x001000>,      /* ap 64 */
1098                          <0x000b4000 0x000b4000 0x001000>,      /* ap 65 */
1099                          <0x000b5000 0x000b5000 0x001000>,      /* ap 66 */
1100                          <0x000b8000 0x000b8000 0x001000>,      /* ap 67 */
1101                          <0x000b9000 0x000b9000 0x001000>,      /* ap 68 */
1102                          <0x000ba000 0x000ba000 0x001000>,      /* ap 69 */
1103                          <0x000bb000 0x000bb000 0x001000>,      /* ap 70 */
1104                          <0x000d1000 0x000d1000 0x001000>,      /* ap 71 */
1105                          <0x000d2000 0x000d2000 0x001000>,      /* ap 72 */
1106                          <0x000d5000 0x000d5000 0x001000>,      /* ap 73 */
1107                          <0x000d6000 0x000d6000 0x001000>,      /* ap 74 */
1108                          <0x000a2000 0x000a2000 0x001000>,      /* ap 75 */
1109                          <0x000a3000 0x000a3000 0x001000>,      /* ap 76 */
1110                          <0x00001400 0x00001400 0x000400>,      /* ap 77 */
1111                          <0x00001800 0x00001800 0x000400>,      /* ap 78 */
1112                          <0x00001c00 0x00001c00 0x000400>,      /* ap 79 */
1113                          <0x000a5000 0x000a5000 0x001000>,      /* ap 80 */
1114                          <0x0007a000 0x0007a000 0x001000>,      /* ap 81 */
1115                          <0x0007b000 0x0007b000 0x001000>,      /* ap 82 */
1116                          <0x0007c000 0x0007c000 0x001000>,      /* ap 83 */
1117                          <0x0007d000 0x0007d000 0x001000>;      /* ap 84 */
1118
1119                 target-module@20000 {                   /* 0x48020000, ap 3 04.0 */
1120                         compatible = "ti,sysc-omap2", "ti,sysc";
1121                         reg = <0x20050 0x4>,
1122                               <0x20054 0x4>,
1123                               <0x20058 0x4>;
1124                         reg-names = "rev", "sysc", "syss";
1125                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1126                                          SYSC_OMAP2_SOFTRESET |
1127                                          SYSC_OMAP2_AUTOIDLE)>;
1128                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1129                                         <SYSC_IDLE_NO>,
1130                                         <SYSC_IDLE_SMART>,
1131                                         <SYSC_IDLE_SMART_WKUP>;
1132                         ti,syss-mask = <1>;
1133                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1134                         clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1135                         clock-names = "fck";
1136                         #address-cells = <1>;
1137                         #size-cells = <1>;
1138                         ranges = <0x0 0x20000 0x1000>;
1139
1140                         uart3: serial@0 {
1141                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1142                                 reg = <0x0 0x100>;
1143                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1144                                 clock-frequency = <48000000>;
1145                                 status = "disabled";
1146                                 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
1147                                 dma-names = "tx", "rx";
1148                         };
1149                 };
1150
1151                 target-module@32000 {                   /* 0x48032000, ap 5 3e.0 */
1152                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1153                         ti,hwmods = "timer2";
1154                         reg = <0x32000 0x4>,
1155                               <0x32010 0x4>;
1156                         reg-names = "rev", "sysc";
1157                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1158                                          SYSC_OMAP4_SOFTRESET)>;
1159                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1160                                         <SYSC_IDLE_NO>,
1161                                         <SYSC_IDLE_SMART>,
1162                                         <SYSC_IDLE_SMART_WKUP>;
1163                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1164                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1165                         clock-names = "fck";
1166                         #address-cells = <1>;
1167                         #size-cells = <1>;
1168                         ranges = <0x0 0x32000 0x1000>;
1169
1170                         timer2: timer@0 {
1171                                 compatible = "ti,omap5430-timer";
1172                                 reg = <0x0 0x80>;
1173                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>;
1174                                 clock-names = "fck";
1175                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1176                         };
1177                 };
1178
1179                 target-module@34000 {                   /* 0x48034000, ap 7 46.0 */
1180                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1181                         ti,hwmods = "timer3";
1182                         reg = <0x34000 0x4>,
1183                               <0x34010 0x4>;
1184                         reg-names = "rev", "sysc";
1185                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1186                                          SYSC_OMAP4_SOFTRESET)>;
1187                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1188                                         <SYSC_IDLE_NO>,
1189                                         <SYSC_IDLE_SMART>,
1190                                         <SYSC_IDLE_SMART_WKUP>;
1191                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1192                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1193                         clock-names = "fck";
1194                         #address-cells = <1>;
1195                         #size-cells = <1>;
1196                         ranges = <0x0 0x34000 0x1000>;
1197
1198                         timer3: timer@0 {
1199                                 compatible = "ti,omap5430-timer";
1200                                 reg = <0x0 0x80>;
1201                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
1202                                 clock-names = "fck";
1203                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1204                         };
1205                 };
1206
1207                 target-module@36000 {                   /* 0x48036000, ap 9 4e.0 */
1208                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1209                         ti,hwmods = "timer4";
1210                         reg = <0x36000 0x4>,
1211                               <0x36010 0x4>;
1212                         reg-names = "rev", "sysc";
1213                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1214                                          SYSC_OMAP4_SOFTRESET)>;
1215                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1216                                         <SYSC_IDLE_NO>,
1217                                         <SYSC_IDLE_SMART>,
1218                                         <SYSC_IDLE_SMART_WKUP>;
1219                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1220                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1221                         clock-names = "fck";
1222                         #address-cells = <1>;
1223                         #size-cells = <1>;
1224                         ranges = <0x0 0x36000 0x1000>;
1225
1226                         timer4: timer@0 {
1227                                 compatible = "ti,omap5430-timer";
1228                                 reg = <0x0 0x80>;
1229                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
1230                                 clock-names = "fck";
1231                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1232                         };
1233                 };
1234
1235                 target-module@3e000 {                   /* 0x4803e000, ap 11 56.0 */
1236                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1237                         ti,hwmods = "timer9";
1238                         reg = <0x3e000 0x4>,
1239                               <0x3e010 0x4>;
1240                         reg-names = "rev", "sysc";
1241                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1242                                          SYSC_OMAP4_SOFTRESET)>;
1243                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1244                                         <SYSC_IDLE_NO>,
1245                                         <SYSC_IDLE_SMART>,
1246                                         <SYSC_IDLE_SMART_WKUP>;
1247                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1248                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1249                         clock-names = "fck";
1250                         #address-cells = <1>;
1251                         #size-cells = <1>;
1252                         ranges = <0x0 0x3e000 0x1000>;
1253
1254                         timer9: timer@0 {
1255                                 compatible = "ti,omap5430-timer";
1256                                 reg = <0x0 0x80>;
1257                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>;
1258                                 clock-names = "fck";
1259                                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1260                         };
1261                 };
1262
1263                 gpio7_target: target-module@51000 {             /* 0x48051000, ap 45 2e.0 */
1264                         compatible = "ti,sysc-omap2", "ti,sysc";
1265                         reg = <0x51000 0x4>,
1266                               <0x51010 0x4>,
1267                               <0x51114 0x4>;
1268                         reg-names = "rev", "sysc", "syss";
1269                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1270                                          SYSC_OMAP2_SOFTRESET |
1271                                          SYSC_OMAP2_AUTOIDLE)>;
1272                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1273                                         <SYSC_IDLE_NO>,
1274                                         <SYSC_IDLE_SMART>,
1275                                         <SYSC_IDLE_SMART_WKUP>;
1276                         ti,syss-mask = <1>;
1277                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1278                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1279                                  <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
1280                         clock-names = "fck", "dbclk";
1281                         #address-cells = <1>;
1282                         #size-cells = <1>;
1283                         ranges = <0x0 0x51000 0x1000>;
1284
1285                         gpio7: gpio@0 {
1286                                 compatible = "ti,omap4-gpio";
1287                                 reg = <0x0 0x200>;
1288                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1289                                 gpio-controller;
1290                                 #gpio-cells = <2>;
1291                                 interrupt-controller;
1292                                 #interrupt-cells = <2>;
1293                         };
1294                 };
1295
1296                 target-module@53000 {                   /* 0x48053000, ap 35 36.0 */
1297                         compatible = "ti,sysc-omap2", "ti,sysc";
1298                         reg = <0x53000 0x4>,
1299                               <0x53010 0x4>,
1300                               <0x53114 0x4>;
1301                         reg-names = "rev", "sysc", "syss";
1302                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1303                                          SYSC_OMAP2_SOFTRESET |
1304                                          SYSC_OMAP2_AUTOIDLE)>;
1305                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1306                                         <SYSC_IDLE_NO>,
1307                                         <SYSC_IDLE_SMART>,
1308                                         <SYSC_IDLE_SMART_WKUP>;
1309                         ti,syss-mask = <1>;
1310                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1311                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1312                                  <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
1313                         clock-names = "fck", "dbclk";
1314                         #address-cells = <1>;
1315                         #size-cells = <1>;
1316                         ranges = <0x0 0x53000 0x1000>;
1317
1318                         gpio8: gpio@0 {
1319                                 compatible = "ti,omap4-gpio";
1320                                 reg = <0x0 0x200>;
1321                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1322                                 gpio-controller;
1323                                 #gpio-cells = <2>;
1324                                 interrupt-controller;
1325                                 #interrupt-cells = <2>;
1326                         };
1327                 };
1328
1329                 target-module@55000 {                   /* 0x48055000, ap 13 0e.0 */
1330                         compatible = "ti,sysc-omap2", "ti,sysc";
1331                         reg = <0x55000 0x4>,
1332                               <0x55010 0x4>,
1333                               <0x55114 0x4>;
1334                         reg-names = "rev", "sysc", "syss";
1335                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1336                                          SYSC_OMAP2_SOFTRESET |
1337                                          SYSC_OMAP2_AUTOIDLE)>;
1338                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1339                                         <SYSC_IDLE_NO>,
1340                                         <SYSC_IDLE_SMART>,
1341                                         <SYSC_IDLE_SMART_WKUP>;
1342                         ti,syss-mask = <1>;
1343                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1344                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1345                                  <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
1346                         clock-names = "fck", "dbclk";
1347                         #address-cells = <1>;
1348                         #size-cells = <1>;
1349                         ranges = <0x0 0x55000 0x1000>;
1350
1351                         gpio2: gpio@0 {
1352                                 compatible = "ti,omap4-gpio";
1353                                 reg = <0x0 0x200>;
1354                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1355                                 gpio-controller;
1356                                 #gpio-cells = <2>;
1357                                 interrupt-controller;
1358                                 #interrupt-cells = <2>;
1359                         };
1360                 };
1361
1362                 target-module@57000 {                   /* 0x48057000, ap 15 06.0 */
1363                         compatible = "ti,sysc-omap2", "ti,sysc";
1364                         reg = <0x57000 0x4>,
1365                               <0x57010 0x4>,
1366                               <0x57114 0x4>;
1367                         reg-names = "rev", "sysc", "syss";
1368                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1369                                          SYSC_OMAP2_SOFTRESET |
1370                                          SYSC_OMAP2_AUTOIDLE)>;
1371                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1372                                         <SYSC_IDLE_NO>,
1373                                         <SYSC_IDLE_SMART>,
1374                                         <SYSC_IDLE_SMART_WKUP>;
1375                         ti,syss-mask = <1>;
1376                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1377                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1378                                  <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
1379                         clock-names = "fck", "dbclk";
1380                         #address-cells = <1>;
1381                         #size-cells = <1>;
1382                         ranges = <0x0 0x57000 0x1000>;
1383
1384                         gpio3: gpio@0 {
1385                                 compatible = "ti,omap4-gpio";
1386                                 reg = <0x0 0x200>;
1387                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1388                                 gpio-controller;
1389                                 #gpio-cells = <2>;
1390                                 interrupt-controller;
1391                                 #interrupt-cells = <2>;
1392                         };
1393                 };
1394
1395                 target-module@59000 {                   /* 0x48059000, ap 17 16.0 */
1396                         compatible = "ti,sysc-omap2", "ti,sysc";
1397                         reg = <0x59000 0x4>,
1398                               <0x59010 0x4>,
1399                               <0x59114 0x4>;
1400                         reg-names = "rev", "sysc", "syss";
1401                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1402                                          SYSC_OMAP2_SOFTRESET |
1403                                          SYSC_OMAP2_AUTOIDLE)>;
1404                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1405                                         <SYSC_IDLE_NO>,
1406                                         <SYSC_IDLE_SMART>,
1407                                         <SYSC_IDLE_SMART_WKUP>;
1408                         ti,syss-mask = <1>;
1409                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1410                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1411                                  <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
1412                         clock-names = "fck", "dbclk";
1413                         #address-cells = <1>;
1414                         #size-cells = <1>;
1415                         ranges = <0x0 0x59000 0x1000>;
1416
1417                         gpio4: gpio@0 {
1418                                 compatible = "ti,omap4-gpio";
1419                                 reg = <0x0 0x200>;
1420                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1421                                 gpio-controller;
1422                                 #gpio-cells = <2>;
1423                                 interrupt-controller;
1424                                 #interrupt-cells = <2>;
1425                         };
1426                 };
1427
1428                 target-module@5b000 {                   /* 0x4805b000, ap 19 1e.0 */
1429                         compatible = "ti,sysc-omap2", "ti,sysc";
1430                         reg = <0x5b000 0x4>,
1431                               <0x5b010 0x4>,
1432                               <0x5b114 0x4>;
1433                         reg-names = "rev", "sysc", "syss";
1434                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1435                                          SYSC_OMAP2_SOFTRESET |
1436                                          SYSC_OMAP2_AUTOIDLE)>;
1437                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1438                                         <SYSC_IDLE_NO>,
1439                                         <SYSC_IDLE_SMART>,
1440                                         <SYSC_IDLE_SMART_WKUP>;
1441                         ti,syss-mask = <1>;
1442                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1443                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1444                                  <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
1445                         clock-names = "fck", "dbclk";
1446                         #address-cells = <1>;
1447                         #size-cells = <1>;
1448                         ranges = <0x0 0x5b000 0x1000>;
1449
1450                         gpio5: gpio@0 {
1451                                 compatible = "ti,omap4-gpio";
1452                                 reg = <0x0 0x200>;
1453                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1454                                 gpio-controller;
1455                                 #gpio-cells = <2>;
1456                                 interrupt-controller;
1457                                 #interrupt-cells = <2>;
1458                         };
1459                 };
1460
1461                 target-module@5d000 {                   /* 0x4805d000, ap 21 26.0 */
1462                         compatible = "ti,sysc-omap2", "ti,sysc";
1463                         reg = <0x5d000 0x4>,
1464                               <0x5d010 0x4>,
1465                               <0x5d114 0x4>;
1466                         reg-names = "rev", "sysc", "syss";
1467                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1468                                          SYSC_OMAP2_SOFTRESET |
1469                                          SYSC_OMAP2_AUTOIDLE)>;
1470                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1471                                         <SYSC_IDLE_NO>,
1472                                         <SYSC_IDLE_SMART>,
1473                                         <SYSC_IDLE_SMART_WKUP>;
1474                         ti,syss-mask = <1>;
1475                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1476                         clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1477                                  <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
1478                         clock-names = "fck", "dbclk";
1479                         #address-cells = <1>;
1480                         #size-cells = <1>;
1481                         ranges = <0x0 0x5d000 0x1000>;
1482
1483                         gpio6: gpio@0 {
1484                                 compatible = "ti,omap4-gpio";
1485                                 reg = <0x0 0x200>;
1486                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1487                                 gpio-controller;
1488                                 #gpio-cells = <2>;
1489                                 interrupt-controller;
1490                                 #interrupt-cells = <2>;
1491                         };
1492                 };
1493
1494                 target-module@60000 {                   /* 0x48060000, ap 23 32.0 */
1495                         compatible = "ti,sysc-omap2", "ti,sysc";
1496                         reg = <0x60000 0x8>,
1497                               <0x60010 0x8>,
1498                               <0x60090 0x8>;
1499                         reg-names = "rev", "sysc", "syss";
1500                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1501                                          SYSC_OMAP2_ENAWAKEUP |
1502                                          SYSC_OMAP2_SOFTRESET |
1503                                          SYSC_OMAP2_AUTOIDLE)>;
1504                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1505                                         <SYSC_IDLE_NO>,
1506                                         <SYSC_IDLE_SMART>,
1507                                         <SYSC_IDLE_SMART_WKUP>;
1508                         ti,syss-mask = <1>;
1509                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1510                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1511                         clock-names = "fck";
1512                         #address-cells = <1>;
1513                         #size-cells = <1>;
1514                         ranges = <0x0 0x60000 0x1000>;
1515
1516                         i2c3: i2c@0 {
1517                                 compatible = "ti,omap4-i2c";
1518                                 reg = <0x0 0x100>;
1519                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1520                                 #address-cells = <1>;
1521                                 #size-cells = <0>;
1522                                 status = "disabled";
1523                         };
1524                 };
1525
1526                 target-module@66000 {                   /* 0x48066000, ap 63 14.0 */
1527                         compatible = "ti,sysc-omap2", "ti,sysc";
1528                         reg = <0x66050 0x4>,
1529                               <0x66054 0x4>,
1530                               <0x66058 0x4>;
1531                         reg-names = "rev", "sysc", "syss";
1532                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1533                                          SYSC_OMAP2_SOFTRESET |
1534                                          SYSC_OMAP2_AUTOIDLE)>;
1535                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1536                                         <SYSC_IDLE_NO>,
1537                                         <SYSC_IDLE_SMART>,
1538                                         <SYSC_IDLE_SMART_WKUP>;
1539                         ti,syss-mask = <1>;
1540                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1541                         clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1542                         clock-names = "fck";
1543                         #address-cells = <1>;
1544                         #size-cells = <1>;
1545                         ranges = <0x0 0x66000 0x1000>;
1546
1547                         uart5: serial@0 {
1548                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1549                                 reg = <0x0 0x100>;
1550                                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1551                                 clock-frequency = <48000000>;
1552                                 status = "disabled";
1553                                 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
1554                                 dma-names = "tx", "rx";
1555                         };
1556                 };
1557
1558                 target-module@68000 {                   /* 0x48068000, ap 53 1c.0 */
1559                         compatible = "ti,sysc-omap2", "ti,sysc";
1560                         reg = <0x68050 0x4>,
1561                               <0x68054 0x4>,
1562                               <0x68058 0x4>;
1563                         reg-names = "rev", "sysc", "syss";
1564                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1565                                          SYSC_OMAP2_SOFTRESET |
1566                                          SYSC_OMAP2_AUTOIDLE)>;
1567                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1568                                         <SYSC_IDLE_NO>,
1569                                         <SYSC_IDLE_SMART>,
1570                                         <SYSC_IDLE_SMART_WKUP>;
1571                         ti,syss-mask = <1>;
1572                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1573                         clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1574                         clock-names = "fck";
1575                         #address-cells = <1>;
1576                         #size-cells = <1>;
1577                         ranges = <0x0 0x68000 0x1000>;
1578
1579                         uart6: serial@0 {
1580                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1581                                 reg = <0x0 0x100>;
1582                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1583                                 clock-frequency = <48000000>;
1584                                 status = "disabled";
1585                                 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
1586                                 dma-names = "tx", "rx";
1587                         };
1588                 };
1589
1590                 target-module@6a000 {                   /* 0x4806a000, ap 24 24.0 */
1591                         compatible = "ti,sysc-omap2", "ti,sysc";
1592                         reg = <0x6a050 0x4>,
1593                               <0x6a054 0x4>,
1594                               <0x6a058 0x4>;
1595                         reg-names = "rev", "sysc", "syss";
1596                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1597                                          SYSC_OMAP2_SOFTRESET |
1598                                          SYSC_OMAP2_AUTOIDLE)>;
1599                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1600                                         <SYSC_IDLE_NO>,
1601                                         <SYSC_IDLE_SMART>,
1602                                         <SYSC_IDLE_SMART_WKUP>;
1603                         ti,syss-mask = <1>;
1604                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1605                         clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1606                         clock-names = "fck";
1607                         #address-cells = <1>;
1608                         #size-cells = <1>;
1609                         ranges = <0x0 0x6a000 0x1000>;
1610
1611                         uart1: serial@0 {
1612                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1613                                 reg = <0x0 0x100>;
1614                                 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1615                                 clock-frequency = <48000000>;
1616                                 status = "disabled";
1617                                 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
1618                                 dma-names = "tx", "rx";
1619                         };
1620                 };
1621
1622                 target-module@6c000 {                   /* 0x4806c000, ap 26 2c.0 */
1623                         compatible = "ti,sysc-omap2", "ti,sysc";
1624                         reg = <0x6c050 0x4>,
1625                               <0x6c054 0x4>,
1626                               <0x6c058 0x4>;
1627                         reg-names = "rev", "sysc", "syss";
1628                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1629                                          SYSC_OMAP2_SOFTRESET |
1630                                          SYSC_OMAP2_AUTOIDLE)>;
1631                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1632                                         <SYSC_IDLE_NO>,
1633                                         <SYSC_IDLE_SMART>,
1634                                         <SYSC_IDLE_SMART_WKUP>;
1635                         ti,syss-mask = <1>;
1636                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1637                         clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1638                         clock-names = "fck";
1639                         #address-cells = <1>;
1640                         #size-cells = <1>;
1641                         ranges = <0x0 0x6c000 0x1000>;
1642
1643                         uart2: serial@0 {
1644                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1645                                 reg = <0x0 0x100>;
1646                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1647                                 clock-frequency = <48000000>;
1648                                 status = "disabled";
1649                                 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
1650                                 dma-names = "tx", "rx";
1651                         };
1652                 };
1653
1654                 target-module@6e000 {                   /* 0x4806e000, ap 28 0c.1 */
1655                         compatible = "ti,sysc-omap2", "ti,sysc";
1656                         reg = <0x6e050 0x4>,
1657                               <0x6e054 0x4>,
1658                               <0x6e058 0x4>;
1659                         reg-names = "rev", "sysc", "syss";
1660                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1661                                          SYSC_OMAP2_SOFTRESET |
1662                                          SYSC_OMAP2_AUTOIDLE)>;
1663                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1664                                         <SYSC_IDLE_NO>,
1665                                         <SYSC_IDLE_SMART>,
1666                                         <SYSC_IDLE_SMART_WKUP>;
1667                         ti,syss-mask = <1>;
1668                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1669                         clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1670                         clock-names = "fck";
1671                         #address-cells = <1>;
1672                         #size-cells = <1>;
1673                         ranges = <0x0 0x6e000 0x1000>;
1674
1675                         uart4: serial@0 {
1676                                 compatible = "ti,dra742-uart", "ti,omap4-uart";
1677                                 reg = <0x0 0x100>;
1678                                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1679                                 clock-frequency = <48000000>;
1680                                                 status = "disabled";
1681                                 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
1682                                 dma-names = "tx", "rx";
1683                         };
1684                 };
1685
1686                 target-module@70000 {                   /* 0x48070000, ap 30 22.0 */
1687                         compatible = "ti,sysc-omap2", "ti,sysc";
1688                         reg = <0x70000 0x8>,
1689                               <0x70010 0x8>,
1690                               <0x70090 0x8>;
1691                         reg-names = "rev", "sysc", "syss";
1692                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1693                                          SYSC_OMAP2_ENAWAKEUP |
1694                                          SYSC_OMAP2_SOFTRESET |
1695                                          SYSC_OMAP2_AUTOIDLE)>;
1696                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1697                                         <SYSC_IDLE_NO>,
1698                                         <SYSC_IDLE_SMART>,
1699                                         <SYSC_IDLE_SMART_WKUP>;
1700                         ti,syss-mask = <1>;
1701                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1702                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1703                         clock-names = "fck";
1704                         #address-cells = <1>;
1705                         #size-cells = <1>;
1706                         ranges = <0x0 0x70000 0x1000>;
1707
1708                         i2c1: i2c@0 {
1709                                 compatible = "ti,omap4-i2c";
1710                                 reg = <0x0 0x100>;
1711                                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1712                                 #address-cells = <1>;
1713                                 #size-cells = <0>;
1714                                 status = "disabled";
1715                         };
1716                 };
1717
1718                 target-module@72000 {                   /* 0x48072000, ap 32 2a.0 */
1719                         compatible = "ti,sysc-omap2", "ti,sysc";
1720                         reg = <0x72000 0x8>,
1721                               <0x72010 0x8>,
1722                               <0x72090 0x8>;
1723                         reg-names = "rev", "sysc", "syss";
1724                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1725                                          SYSC_OMAP2_ENAWAKEUP |
1726                                          SYSC_OMAP2_SOFTRESET |
1727                                          SYSC_OMAP2_AUTOIDLE)>;
1728                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1729                                         <SYSC_IDLE_NO>,
1730                                         <SYSC_IDLE_SMART>,
1731                                         <SYSC_IDLE_SMART_WKUP>;
1732                         ti,syss-mask = <1>;
1733                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1734                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1735                         clock-names = "fck";
1736                         #address-cells = <1>;
1737                         #size-cells = <1>;
1738                         ranges = <0x0 0x72000 0x1000>;
1739
1740                         i2c2: i2c@0 {
1741                                 compatible = "ti,omap4-i2c";
1742                                 reg = <0x0 0x100>;
1743                                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1744                                 #address-cells = <1>;
1745                                 #size-cells = <0>;
1746                                 status = "disabled";
1747                         };
1748                 };
1749
1750                 target-module@78000 {                   /* 0x48078000, ap 39 0a.0 */
1751                         compatible = "ti,sysc-omap2", "ti,sysc";
1752                         ti,hwmods = "elm";
1753                         reg = <0x78000 0x4>,
1754                               <0x78010 0x4>,
1755                               <0x78014 0x4>;
1756                         reg-names = "rev", "sysc", "syss";
1757                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1758                                          SYSC_OMAP2_SOFTRESET |
1759                                          SYSC_OMAP2_AUTOIDLE)>;
1760                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1761                                         <SYSC_IDLE_NO>,
1762                                         <SYSC_IDLE_SMART>,
1763                                         <SYSC_IDLE_SMART_WKUP>;
1764                         ti,syss-mask = <1>;
1765                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1766                         clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1767                         clock-names = "fck";
1768                         #address-cells = <1>;
1769                         #size-cells = <1>;
1770                         ranges = <0x0 0x78000 0x1000>;
1771
1772                         elm: elm@0 {
1773                                 compatible = "ti,am3352-elm";
1774                                 reg = <0x0 0xfc0>;      /* device IO registers */
1775                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1776                                 status = "disabled";
1777                         };
1778                 };
1779
1780                 target-module@7a000 {                   /* 0x4807a000, ap 81 3a.0 */
1781                         compatible = "ti,sysc-omap2", "ti,sysc";
1782                         reg = <0x7a000 0x8>,
1783                               <0x7a010 0x8>,
1784                               <0x7a090 0x8>;
1785                         reg-names = "rev", "sysc", "syss";
1786                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1787                                          SYSC_OMAP2_ENAWAKEUP |
1788                                          SYSC_OMAP2_SOFTRESET |
1789                                          SYSC_OMAP2_AUTOIDLE)>;
1790                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1791                                         <SYSC_IDLE_NO>,
1792                                         <SYSC_IDLE_SMART>,
1793                                         <SYSC_IDLE_SMART_WKUP>;
1794                         ti,syss-mask = <1>;
1795                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1796                         clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1797                         clock-names = "fck";
1798                         #address-cells = <1>;
1799                         #size-cells = <1>;
1800                         ranges = <0x0 0x7a000 0x1000>;
1801
1802                         i2c4: i2c@0 {
1803                                 compatible = "ti,omap4-i2c";
1804                                 reg = <0x0 0x100>;
1805                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1806                                 #address-cells = <1>;
1807                                 #size-cells = <0>;
1808                                 status = "disabled";
1809                         };
1810                 };
1811
1812                 target-module@7c000 {                   /* 0x4807c000, ap 83 4a.0 */
1813                         compatible = "ti,sysc-omap2", "ti,sysc";
1814                         reg = <0x7c000 0x8>,
1815                               <0x7c010 0x8>,
1816                               <0x7c090 0x8>;
1817                         reg-names = "rev", "sysc", "syss";
1818                         ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1819                                          SYSC_OMAP2_ENAWAKEUP |
1820                                          SYSC_OMAP2_SOFTRESET |
1821                                          SYSC_OMAP2_AUTOIDLE)>;
1822                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1823                                         <SYSC_IDLE_NO>,
1824                                         <SYSC_IDLE_SMART>,
1825                                         <SYSC_IDLE_SMART_WKUP>;
1826                         ti,syss-mask = <1>;
1827                         /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1828                         clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1829                         clock-names = "fck";
1830                         #address-cells = <1>;
1831                         #size-cells = <1>;
1832                         ranges = <0x0 0x7c000 0x1000>;
1833
1834                         i2c5: i2c@0 {
1835                                 compatible = "ti,omap4-i2c";
1836                                 reg = <0x0 0x100>;
1837                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1838                                 #address-cells = <1>;
1839                                 #size-cells = <0>;
1840                                 status = "disabled";
1841                         };
1842                 };
1843
1844                 target-module@86000 {                   /* 0x48086000, ap 41 5e.0 */
1845                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1846                         ti,hwmods = "timer10";
1847                         reg = <0x86000 0x4>,
1848                               <0x86010 0x4>;
1849                         reg-names = "rev", "sysc";
1850                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1851                                          SYSC_OMAP4_SOFTRESET)>;
1852                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1853                                         <SYSC_IDLE_NO>,
1854                                         <SYSC_IDLE_SMART>,
1855                                         <SYSC_IDLE_SMART_WKUP>;
1856                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1857                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1858                         clock-names = "fck";
1859                         #address-cells = <1>;
1860                         #size-cells = <1>;
1861                         ranges = <0x0 0x86000 0x1000>;
1862
1863                         timer10: timer@0 {
1864                                 compatible = "ti,omap5430-timer";
1865                                 reg = <0x0 0x80>;
1866                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>;
1867                                 clock-names = "fck";
1868                                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1869                         };
1870                 };
1871
1872                 target-module@88000 {                   /* 0x48088000, ap 43 66.0 */
1873                         compatible = "ti,sysc-omap4-timer", "ti,sysc";
1874                         ti,hwmods = "timer11";
1875                         reg = <0x88000 0x4>,
1876                               <0x88010 0x4>;
1877                         reg-names = "rev", "sysc";
1878                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1879                                          SYSC_OMAP4_SOFTRESET)>;
1880                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1881                                         <SYSC_IDLE_NO>,
1882                                         <SYSC_IDLE_SMART>,
1883                                         <SYSC_IDLE_SMART_WKUP>;
1884                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1885                         clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1886                         clock-names = "fck";
1887                         #address-cells = <1>;
1888                         #size-cells = <1>;
1889                         ranges = <0x0 0x88000 0x1000>;
1890
1891                         timer11: timer@0 {
1892                                 compatible = "ti,omap5430-timer";
1893                                 reg = <0x0 0x80>;
1894                                 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>;
1895                                 clock-names = "fck";
1896                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1897                         };
1898                 };
1899
1900                 target-module@90000 {                   /* 0x48090000, ap 55 12.0 */
1901                         compatible = "ti,sysc-omap2", "ti,sysc";
1902                         ti,hwmods = "rng";
1903                         reg = <0x91fe0 0x4>,
1904                               <0x91fe4 0x4>;
1905                         reg-names = "rev", "sysc";
1906                         ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
1907                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1908                                         <SYSC_IDLE_NO>;
1909                         /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1910                         clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1911                         clock-names = "fck";
1912                         #address-cells = <1>;
1913                         #size-cells = <1>;
1914                         ranges = <0x0 0x90000 0x2000>;
1915
1916                         rng: rng@0 {
1917                                 compatible = "ti,omap4-rng";
1918                                 reg = <0x0 0x2000>;
1919                                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1920                                 clocks = <&l3_iclk_div>;
1921                                 clock-names = "fck";
1922                         };
1923                 };
1924
1925                 target-module@98000 {                   /* 0x48098000, ap 47 08.0 */
1926                         compatible = "ti,sysc-omap4", "ti,sysc";
1927                         reg = <0x98000 0x4>,
1928                               <0x98010 0x4>;
1929                         reg-names = "rev", "sysc";
1930                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1931                                          SYSC_OMAP4_SOFTRESET)>;
1932                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1933                                         <SYSC_IDLE_NO>,
1934                                         <SYSC_IDLE_SMART>,
1935                                         <SYSC_IDLE_SMART_WKUP>;
1936                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1937                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1938                         clock-names = "fck";
1939                         #address-cells = <1>;
1940                         #size-cells = <1>;
1941                         ranges = <0x0 0x98000 0x1000>;
1942
1943                         mcspi1: spi@0 {
1944                                 compatible = "ti,omap4-mcspi";
1945                                 reg = <0x0 0x200>;
1946                                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1947                                 #address-cells = <1>;
1948                                 #size-cells = <0>;
1949                                 ti,spi-num-cs = <4>;
1950                                 dmas = <&sdma_xbar 35>,
1951                                        <&sdma_xbar 36>,
1952                                        <&sdma_xbar 37>,
1953                                        <&sdma_xbar 38>,
1954                                        <&sdma_xbar 39>,
1955                                        <&sdma_xbar 40>,
1956                                        <&sdma_xbar 41>,
1957                                        <&sdma_xbar 42>;
1958                                 dma-names = "tx0", "rx0", "tx1", "rx1",
1959                                             "tx2", "rx2", "tx3", "rx3";
1960                                 status = "disabled";
1961                         };
1962                 };
1963
1964                 target-module@9a000 {                   /* 0x4809a000, ap 49 10.0 */
1965                         compatible = "ti,sysc-omap4", "ti,sysc";
1966                         reg = <0x9a000 0x4>,
1967                               <0x9a010 0x4>;
1968                         reg-names = "rev", "sysc";
1969                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1970                                          SYSC_OMAP4_SOFTRESET)>;
1971                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1972                                         <SYSC_IDLE_NO>,
1973                                         <SYSC_IDLE_SMART>,
1974                                         <SYSC_IDLE_SMART_WKUP>;
1975                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1976                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1977                         clock-names = "fck";
1978                         #address-cells = <1>;
1979                         #size-cells = <1>;
1980                         ranges = <0x0 0x9a000 0x1000>;
1981
1982                         mcspi2: spi@0 {
1983                                 compatible = "ti,omap4-mcspi";
1984                                 reg = <0x0 0x200>;
1985                                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1986                                 #address-cells = <1>;
1987                                 #size-cells = <0>;
1988                                 ti,spi-num-cs = <2>;
1989                                 dmas = <&sdma_xbar 43>,
1990                                        <&sdma_xbar 44>,
1991                                        <&sdma_xbar 45>,
1992                                        <&sdma_xbar 46>;
1993                                 dma-names = "tx0", "rx0", "tx1", "rx1";
1994                                 status = "disabled";
1995                         };
1996                 };
1997
1998                 target-module@9c000 {                   /* 0x4809c000, ap 51 38.0 */
1999                         compatible = "ti,sysc-omap4", "ti,sysc";
2000                         reg = <0x9c000 0x4>,
2001                               <0x9c010 0x4>;
2002                         reg-names = "rev", "sysc";
2003                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2004                                          SYSC_OMAP4_SOFTRESET)>;
2005                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2006                                         <SYSC_IDLE_NO>,
2007                                         <SYSC_IDLE_SMART>,
2008                                         <SYSC_IDLE_SMART_WKUP>;
2009                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2010                                         <SYSC_IDLE_NO>,
2011                                         <SYSC_IDLE_SMART>,
2012                                         <SYSC_IDLE_SMART_WKUP>;
2013                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2014                         clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2015                         clock-names = "fck";
2016                         #address-cells = <1>;
2017                         #size-cells = <1>;
2018                         ranges = <0x0 0x9c000 0x1000>;
2019
2020                         mmc1: mmc@0 {
2021                                 compatible = "ti,dra7-sdhci";
2022                                 reg = <0x0 0x400>;
2023                                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
2024                                 status = "disabled";
2025                                 pbias-supply = <&pbias_mmc_reg>;
2026                                 max-frequency = <192000000>;
2027                                 mmc-ddr-1_8v;
2028                                 mmc-ddr-3_3v;
2029                         };
2030                 };
2031
2032                 target-module@a2000 {                   /* 0x480a2000, ap 75 02.0 */
2033                         compatible = "ti,sysc";
2034                         status = "disabled";
2035                         #address-cells = <1>;
2036                         #size-cells = <1>;
2037                         ranges = <0x0 0xa2000 0x1000>;
2038                 };
2039
2040                 target-module@a4000 {                   /* 0x480a4000, ap 57 42.0 */
2041                         compatible = "ti,sysc";
2042                         status = "disabled";
2043                         #address-cells = <1>;
2044                         #size-cells = <1>;
2045                         ranges = <0x00000000 0x000a4000 0x00001000>,
2046                                  <0x00001000 0x000a5000 0x00001000>;
2047                 };
2048
2049                 target-module@a8000 {                   /* 0x480a8000, ap 59 1a.0 */
2050                         compatible = "ti,sysc";
2051                         status = "disabled";
2052                         #address-cells = <1>;
2053                         #size-cells = <1>;
2054                         ranges = <0x0 0xa8000 0x4000>;
2055                 };
2056
2057                 target-module@ad000 {                   /* 0x480ad000, ap 61 20.0 */
2058                         compatible = "ti,sysc-omap4", "ti,sysc";
2059                         reg = <0xad000 0x4>,
2060                               <0xad010 0x4>;
2061                         reg-names = "rev", "sysc";
2062                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2063                                          SYSC_OMAP4_SOFTRESET)>;
2064                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2065                                         <SYSC_IDLE_NO>,
2066                                         <SYSC_IDLE_SMART>,
2067                                         <SYSC_IDLE_SMART_WKUP>;
2068                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2069                                         <SYSC_IDLE_NO>,
2070                                         <SYSC_IDLE_SMART>,
2071                                         <SYSC_IDLE_SMART_WKUP>;
2072                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2073                         clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2074                         clock-names = "fck";
2075                         #address-cells = <1>;
2076                         #size-cells = <1>;
2077                         ranges = <0x0 0xad000 0x1000>;
2078
2079                         mmc3: mmc@0 {
2080                                 compatible = "ti,dra7-sdhci";
2081                                 reg = <0x0 0x400>;
2082                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
2083                                 status = "disabled";
2084                                 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
2085                                 max-frequency = <64000000>;
2086                                 /* SDMA is not supported */
2087                                 sdhci-caps-mask = <0x0 0x400000>;
2088                         };
2089                 };
2090
2091                 target-module@b2000 {                   /* 0x480b2000, ap 37 52.0 */
2092                         compatible = "ti,sysc-omap2", "ti,sysc";
2093                         ti,hwmods = "hdq1w";
2094                         reg = <0xb2000 0x4>,
2095                               <0xb2014 0x4>,
2096                               <0xb2018 0x4>;
2097                         reg-names = "rev", "sysc", "syss";
2098                         ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2099                                          SYSC_OMAP2_AUTOIDLE)>;
2100                         ti,syss-mask = <1>;
2101                         ti,no-reset-on-init;
2102                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2103                         clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2104                         clock-names = "fck";
2105                         #address-cells = <1>;
2106                         #size-cells = <1>;
2107                         ranges = <0x0 0xb2000 0x1000>;
2108
2109                         hdqw1w: 1w@0 {
2110                                 compatible = "ti,omap3-1w";
2111                                 reg = <0x0 0x1000>;
2112                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2113                         };
2114                 };
2115
2116                 target-module@b4000 {                   /* 0x480b4000, ap 65 40.0 */
2117                         compatible = "ti,sysc-omap4", "ti,sysc";
2118                         reg = <0xb4000 0x4>,
2119                               <0xb4010 0x4>;
2120                         reg-names = "rev", "sysc";
2121                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2122                                          SYSC_OMAP4_SOFTRESET)>;
2123                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2124                                         <SYSC_IDLE_NO>,
2125                                         <SYSC_IDLE_SMART>,
2126                                         <SYSC_IDLE_SMART_WKUP>;
2127                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2128                                         <SYSC_IDLE_NO>,
2129                                         <SYSC_IDLE_SMART>,
2130                                         <SYSC_IDLE_SMART_WKUP>;
2131                         /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2132                         clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2133                         clock-names = "fck";
2134                         #address-cells = <1>;
2135                         #size-cells = <1>;
2136                         ranges = <0x0 0xb4000 0x1000>;
2137
2138                         mmc2: mmc@0 {
2139                                 compatible = "ti,dra7-sdhci";
2140                                 reg = <0x0 0x400>;
2141                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2142                                 status = "disabled";
2143                                 max-frequency = <192000000>;
2144                                 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
2145                                 sdhci-caps-mask = <0x7 0x0>;
2146                                 mmc-hs200-1_8v;
2147                                 mmc-ddr-1_8v;
2148                                 mmc-ddr-3_3v;
2149                         };
2150                 };
2151
2152                 target-module@b8000 {                   /* 0x480b8000, ap 67 48.0 */
2153                         compatible = "ti,sysc-omap4", "ti,sysc";
2154                         reg = <0xb8000 0x4>,
2155                               <0xb8010 0x4>;
2156                         reg-names = "rev", "sysc";
2157                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2158                                          SYSC_OMAP4_SOFTRESET)>;
2159                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2160                                         <SYSC_IDLE_NO>,
2161                                         <SYSC_IDLE_SMART>,
2162                                         <SYSC_IDLE_SMART_WKUP>;
2163                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2164                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2165                         clock-names = "fck";
2166                         #address-cells = <1>;
2167                         #size-cells = <1>;
2168                         ranges = <0x0 0xb8000 0x1000>;
2169
2170                         mcspi3: spi@0 {
2171                                 compatible = "ti,omap4-mcspi";
2172                                 reg = <0x0 0x200>;
2173                                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2174                                 #address-cells = <1>;
2175                                 #size-cells = <0>;
2176                                 ti,spi-num-cs = <2>;
2177                                 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
2178                                 dma-names = "tx0", "rx0";
2179                                 status = "disabled";
2180                         };
2181                 };
2182
2183                 target-module@ba000 {                   /* 0x480ba000, ap 69 18.0 */
2184                         compatible = "ti,sysc-omap4", "ti,sysc";
2185                         reg = <0xba000 0x4>,
2186                               <0xba010 0x4>;
2187                         reg-names = "rev", "sysc";
2188                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2189                                          SYSC_OMAP4_SOFTRESET)>;
2190                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2191                                         <SYSC_IDLE_NO>,
2192                                         <SYSC_IDLE_SMART>,
2193                                         <SYSC_IDLE_SMART_WKUP>;
2194                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2195                         clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2196                         clock-names = "fck";
2197                         #address-cells = <1>;
2198                         #size-cells = <1>;
2199                         ranges = <0x0 0xba000 0x1000>;
2200
2201                         mcspi4: spi@0 {
2202                                 compatible = "ti,omap4-mcspi";
2203                                 reg = <0x0 0x200>;
2204                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
2205                                 #address-cells = <1>;
2206                                 #size-cells = <0>;
2207                                 ti,spi-num-cs = <1>;
2208                                 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
2209                                 dma-names = "tx0", "rx0";
2210                                 status = "disabled";
2211                         };
2212                 };
2213
2214                 target-module@d1000 {                   /* 0x480d1000, ap 71 28.0 */
2215                         compatible = "ti,sysc-omap4", "ti,sysc";
2216                         reg = <0xd1000 0x4>,
2217                               <0xd1010 0x4>;
2218                         reg-names = "rev", "sysc";
2219                         ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2220                                          SYSC_OMAP4_SOFTRESET)>;
2221                         ti,sysc-midle = <SYSC_IDLE_FORCE>,
2222                                         <SYSC_IDLE_NO>,
2223                                         <SYSC_IDLE_SMART>,
2224                                         <SYSC_IDLE_SMART_WKUP>;
2225                         ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2226                                         <SYSC_IDLE_NO>,
2227                                         <SYSC_IDLE_SMART>,
2228                                         <SYSC_IDLE_SMART_WKUP>;
2229                         /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2230                         clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2231                         clock-names = "fck";
2232                         #address-cells = <1>;
2233                         #size-cells = <1>;
2234                         ranges = <0x0 0xd1000 0x1000>;
2235
2236                         mmc4: mmc@0 {
2237                                 compatible = "ti,dra7-sdhci";
2238                                 reg = <0x0 0x400>;
2239                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2240                                 status = "disabled";
2241                                 max-frequency = <192000000>;
2242                                 /* SDMA is not supported */
2243                                 sdhci-caps-mask = <0x0 0x400000>;
2244                         };
2245                 };
2246
2247                 target-module@d5000 {                   /* 0x480d5000, ap 73 30.0 */
2248                         compatible = "ti,sysc";
2249                         status = "disabled";
2250                         #address-cells = <1>;
2251                         #size-cells = <1>;
2252                         ranges = <0x0 0xd5000 0x1000>;
2253                 };
2254         };
2255
2256         segment@200000 {                                        /* 0x48200000 */
2257                 compatible = "simple-bus";
2258                 #address-cells = <1>;
2259                 #size-cells = <1>;
2260         };
2261 };
2262
2263 &l4_per2 {                                              /* 0x48400000 */
2264         compatible = "ti,dra7-l4-per2", "simple-bus";
2265         reg = <0x48400000 0x800>,
2266               <0x48400800 0x800>,
2267               <0x48401000 0x400>,
2268               <0x48401400 0x400>,
2269               <0x48401800 0x400>;
2270         reg-names = "ap", "la", "ia0", "ia1", "ia2";
2271         #address-cells = <1>;
2272         #size-cells = <1>;
2273         ranges = <0x00000000 0x48400000 0x400000>,      /* segment 0 */
2274                  <0x45800000 0x45800000 0x400000>,      /* L3 data port */
2275                  <0x45c00000 0x45c00000 0x400000>,      /* L3 data port */
2276                  <0x46000000 0x46000000 0x400000>,      /* L3 data port */
2277                  <0x48436000 0x48436000 0x400000>,      /* L3 data port */
2278                  <0x4843a000 0x4843a000 0x400000>,      /* L3 data port */
2279                  <0x4844c000 0x4844c000 0x400000>,      /* L3 data port */
2280                  <0x48450000 0x48450000 0x400000>,      /* L3 data port */
2281                  <0x48454000 0x48454000 0x400000>;      /* L3 data port */
2282
2283         segment@0 {                                     /* 0x48400000 */
2284                 compatible = "simple-bus";
2285                 #address-cells = <1>;
2286                 #size-cells = <1>;
2287                 ranges = <0x00000000 0x00000000 0x000800>,      /* ap 0 */
2288                          <0x00001000 0x00001000 0x000400>,      /* ap 1 */
2289                          <0x00000800 0x00000800 0x000800>,      /* ap 2 */
2290                          <0x00084000 0x00084000 0x004000>,      /* ap 3 */
2291                          <0x00001400 0x00001400 0x000400>,      /* ap 4 */
2292                          <0x00001800 0x00001800 0x000400>,      /* ap 5 */
2293                          <0x00088000 0x00088000 0x001000>,      /* ap 6 */
2294                          <0x0002c000 0x0002c000 0x001000>,      /* ap 7 */
2295                          <0x0002d000 0x0002d000 0x001000>,      /* ap 8 */
2296                          <0x00060000 0x00060000 0x002000>,      /* ap 9 */
2297                          <0x00062000 0x00062000 0x001000>,      /* ap 10 */
2298                          <0x00064000 0x00064000 0x002000>,      /* ap 11 */
2299                          <0x00066000 0x00066000 0x001000>,      /* ap 12 */
2300                          <0x00068000 0x00068000 0x002000>,      /* ap 13 */
2301                          <0x0006a000 0x0006a000 0x001000>,      /* ap 14 */
2302                          <0x0006c000 0x0006c000 0x002000>,      /* ap 15 */
2303                          <0x0006e000 0x0006e000 0x001000>,      /* ap 16 */
2304                          <0x00036000 0x00036000 0x001000>,      /* ap 17 */
2305                          <0x00037000 0x00037000 0x001000>,      /* ap 18 */
2306                          <0x00070000 0x00070000 0x002000>,      /* ap 19 */
2307                          <0x00072000 0x00072000 0x001000>,      /* ap 20 */
2308                          <0x0003a000 0x0003a000 0x001000>,      /* ap 21 */
2309                          <0x0003b000 0x0003b000 0x001000>,      /* ap 22 */
2310                          <0x0003c000 0x0003c000 0x001000>,      /* ap 23 */
2311                          <0x0003d000 0x0003d000 0x001000>,      /* ap 24 */
2312                          <0x0003e000 0x0003e000 0x001000>,      /* ap 25 */
2313                          <0x0003f000 0x0003f000 0x001000>,      /* ap 26 */
2314                          <0x00040000 0x00040000 0x001000>,      /* ap 27 */
2315                          <0x00041000 0x00041000 0x001000>,      /* ap 28 */
2316                          <0x00042000 0x00042000 0x001000>,      /* ap 29 */
2317                          <0x00043000 0x00043000 0x001000>,      /* ap 30 */
2318                          <0x00080000 0x00080000 0x002000>,      /* ap 31 */
2319                          <0x00082000 0x00082000 0x001000>,      /* ap 32 */
2320                          <0x0004a000 0x0004a000 0x001000>,      /* ap 33 */
2321                          <0x0004b000 0x0004b000 0x001000>,      /* ap 34 */
2322                          <0x00074000 0x00074000 0x002000>,      /* ap 35 */
2323                          <0x00076000 0x00076000 0x001000>,      /* ap 36 */
2324                          <0x00050000 0x00050000 0x001000>,      /* ap 37 */
2325                          <0x00051000 0x00051000 0x001000>,      /* ap 38 */
2326                          <0x00078000 0x00078000 0x002000>,      /* ap 39 */
2327                          <0x0007a000 0x0007a000 0x001000>,      /* ap 40 */
2328                          <0x00054000 0x00054000 0x001000>,      /* ap 41 */
2329                          <0x00055000 0x00055000 0x001000>,      /* ap 42 */
2330                          <0x0007c000 0x0007c000 0x002000>,      /* ap 43 */
2331                          <0x0007e000 0x0007e000 0x001000>,      /* ap 44 */
2332                          <0x0004c000 0x0004c000 0x001000>,      /* ap 45 */
2333                          <0x0004d000 0x0004d000 0x001000>,      /* ap 46 */
2334                          <0x00020000 0x00020000 0x001000>,      /* ap 47 */
2335                          <0x00021000 0x00021000 0x001000>,      /* ap 48 */
2336                          <0x00022000 0x00022000 0x001000>,      /* ap 49 */
2337                          <0x00023000 0x00023000 0x001000>,      /* ap 50 */
2338                          <0x00024000 0x00024000 0x001000>,      /* ap 51 */
2339                          <0x00025000 0x00025000 0x001000>,      /* ap 52 */
2340                          <0x00046000 0x00046000 0x001000>,      /* ap 53 */
2341                          <0x00047000 0x00047000 0x001000>,      /* ap 54 */
2342                          <0x00048000 0x00048000 0x001000>,      /* ap 55 */
2343                          <0x00049000 0x00049000 0x001000>,      /* ap 56 */
2344                          <0x00058000 0x00058000 0x002000>,      /* ap 57 */
2345                          <0x0005a000 0x0005a000 0x001000>,      /* ap 58 */
2346                          <0x0005b000 0x0005b000 0x001000>,      /* ap 59 */
2347                          <0x0005c000 0x0005c000 0x001000>,      /* ap 60 */
2348                          <0x0005d000 0x0005d000 0x001000>,      /* ap 61 */
2349                          <0x0005e000 0x0005e000 0x001000>,      /* ap 62 */
2350                          <0x45800000 0x45800000 0x400000>,      /* L3 data port */
2351                          <0x45c00000 0x45c00000 0x400000>,      /* L3 data port */
2352                          <0x46000000 0x46000000 0x400000>,      /* L3 data port */
2353                          <0x48436000 0x48436000 0x400000>,      /* L3 data port */
2354                          <0x4843a000 0x4843a000 0x400000>,      /* L3 data port */
2355                          <0x4844c000 0x4844c000 0x400000>,      /* L3 data port */
2356                          <0x48450000 0x48450000 0x400000>,      /* L3 data port */
2357                          <0x48454000 0x48454000 0x400000>;      /* L3 data port */
2358
2359                 target-module@20000 {                   /* 0x48420000, ap 47 02.0 */
2360                         compatible = "ti,sysc-omap2", "ti,sysc";
2361                         reg = <0x20050 0x4>,
2362                               <0x20054 0x4>,
2363                               <0x20058 0x4>;
2364                         reg-names = "rev", "sysc", "syss";
2365                         ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2366                                          SYSC_OMAP2_SOFTRESET |
2367