arch/arm/boot/dts/dra7-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 /dts-v1/;
   9
  10 #include "dra74x.dtsi"
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/clk/ti-dra7-atl.h>
  13 #include <dt-bindings/input/input.h>
  14
  15 / {
  16         model = "TI DRA742";
  17         compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
  18
  19         memory@0 {
  20                 device_type = "memory";
  21                 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */
  22         };
  23
  24         chosen {
  25                 stdout-path = &uart1;
  26         };
  27
  28         evm_3v3_sd: fixedregulator-sd {
  29                 compatible = "regulator-fixed";
  30                 regulator-name = "evm_3v3_sd";
  31                 regulator-min-microvolt = <3300000>;
  32                 regulator-max-microvolt = <3300000>;
  33                 enable-active-high;
  34                 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
  35         };
  36
  37         evm_3v3_sw: fixedregulator-evm_3v3_sw {
  38                 compatible = "regulator-fixed";
  39                 regulator-name = "evm_3v3_sw";
  40                 vin-supply = <&sysen1>;
  41                 regulator-min-microvolt = <3300000>;
  42                 regulator-max-microvolt = <3300000>;
  43         };
  44
  45         aic_dvdd: fixedregulator-aic_dvdd {
  46                 /* TPS77018DBVT */
  47                 compatible = "regulator-fixed";
  48                 regulator-name = "aic_dvdd";
  49                 vin-supply = <&evm_3v3_sw>;
  50                 regulator-min-microvolt = <1800000>;
  51                 regulator-max-microvolt = <1800000>;
  52         };
  53
  54         extcon_usb1: extcon_usb1 {
  55                 compatible = "linux,extcon-usb-gpio";
  56                 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>;
  57         };
  58
  59         extcon_usb2: extcon_usb2 {
  60                 compatible = "linux,extcon-usb-gpio";
  61                 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>;
  62         };
  63
  64         vtt_fixed: fixedregulator-vtt {
  65                 compatible = "regulator-fixed";
  66                 regulator-name = "vtt_fixed";
  67                 regulator-min-microvolt = <1350000>;
  68                 regulator-max-microvolt = <1350000>;
  69                 regulator-always-on;
  70                 regulator-boot-on;
  71                 enable-active-high;
  72                 vin-supply = <&sysen2>;
  73                 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
  74         };
  75
  76         sound0: sound0 {
  77                 compatible = "simple-audio-card";
  78                 simple-audio-card,name = "DRA7xx-EVM";
  79                 simple-audio-card,widgets =
  80                         "Headphone", "Headphone Jack",
  81                         "Line", "Line Out",
  82                         "Microphone", "Mic Jack",
  83                         "Line", "Line In";
  84                 simple-audio-card,routing =
  85                         "Headphone Jack",       "HPLOUT",
  86                         "Headphone Jack",       "HPROUT",
  87                         "Line Out",             "LLOUT",
  88                         "Line Out",             "RLOUT",
  89                         "MIC3L",                "Mic Jack",
  90                         "MIC3R",                "Mic Jack",
  91                         "Mic Jack",             "Mic Bias",
  92                         "LINE1L",               "Line In",
  93                         "LINE1R",               "Line In";
  94                 simple-audio-card,format = "dsp_b";
  95                 simple-audio-card,bitclock-master = <&sound0_master>;
  96                 simple-audio-card,frame-master = <&sound0_master>;
  97                 simple-audio-card,bitclock-inversion;
  98
  99                 sound0_master: simple-audio-card,cpu {
 100                         sound-dai = <&mcasp3>;
 101                         system-clock-frequency = <5644800>;
 102                 };
 103
 104                 simple-audio-card,codec {
 105                         sound-dai = <&tlv320aic3106>;
 106                         clocks = <&atl_clkin2_ck>;
 107                 };
 108         };
 109
 110         leds {
 111                 compatible = "gpio-leds";
 112                 led0 {
 113                         label = "dra7:usr1";
 114                         gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>;
 115                         default-state = "off";
 116                 };
 117
 118                 led1 {
 119                         label = "dra7:usr2";
 120                         gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>;
 121                         default-state = "off";
 122                 };
 123
 124                 led2 {
 125                         label = "dra7:usr3";
 126                         gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>;
 127                         default-state = "off";
 128                 };
 129
 130                 led3 {
 131                         label = "dra7:usr4";
 132                         gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>;
 133                         default-state = "off";
 134                 };
 135         };
 136
 137         gpio_keys {
 138                 compatible = "gpio-keys";
 139                 #address-cells = <1>;
 140                 #size-cells = <0>;
 141                 autorepeat;
 142
 143                 USER1 {
 144                         label = "btnUser1";
 145                         linux,code = <BTN_0>;
 146                         gpios = <&pcf_lcd 2 GPIO_ACTIVE_LOW>;
 147                 };
 148
 149                 USER2 {
 150                         label = "btnUser2";
 151                         linux,code = <BTN_1>;
 152                         gpios = <&pcf_lcd 3 GPIO_ACTIVE_LOW>;
 153                 };
 154         };
 155 };
 156
 157 &dra7_pmx_core {
 158         dcan1_pins_default: dcan1_pins_default {
 159                 pinctrl-single,pins = <
 160                         DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */
 161                         DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */
 162                 >;
 163         };
 164
 165         dcan1_pins_sleep: dcan1_pins_sleep {
 166                 pinctrl-single,pins = <
 167                         DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */
 168                         DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */
 169                 >;
 170         };
 171
 172         mmc1_pins_default: mmc1_pins_default {
 173                 pinctrl-single,pins = <
 174                         DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14)       /* mmc1sdcd.gpio219 */
 175                         DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
 176                         DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
 177                         DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
 178                         DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
 179                         DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
 180                         DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
 181                 >;
 182         };
 183
 184         mmc2_pins_default: mmc2_pins_default {
 185                 pinctrl-single,pins = <
 186                         DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
 187                         DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
 188                         DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
 189                         DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
 190                         DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
 191                         DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
 192                         DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
 193                         DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
 194                         DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
 195                         DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
 196                 >;
 197         };
 198 };
 199
 200 &i2c1 {
 201         status = "okay";
 202         clock-frequency = <400000>;
 203
 204         tps659038: tps659038@58 {
 205                 compatible = "ti,tps659038";
 206                 reg = <0x58>;
 207                 ti,palmas-override-powerhold;
 208                 ti,system-power-controller;
 209
 210                 tps659038_pmic {
 211                         compatible = "ti,tps659038-pmic";
 212
 213                         regulators {
 214                                 smps123_reg: smps123 {
 215                                         /* VDD_MPU */
 216                                         regulator-name = "smps123";
 217                                         regulator-min-microvolt = < 850000>;
 218                                         regulator-max-microvolt = <1250000>;
 219                                         regulator-always-on;
 220                                         regulator-boot-on;
 221                                 };
 222
 223                                 smps45_reg: smps45 {
 224                                         /* VDD_DSPEVE */
 225                                         regulator-name = "smps45";
 226                                         regulator-min-microvolt = < 850000>;
 227                                         regulator-max-microvolt = <1250000>;
 228                                         regulator-always-on;
 229                                         regulator-boot-on;
 230                                 };
 231
 232                                 smps6_reg: smps6 {
 233                                         /* VDD_GPU - over VDD_SMPS6 */
 234                                         regulator-name = "smps6";
 235                                         regulator-min-microvolt = <850000>;
 236                                         regulator-max-microvolt = <1250000>;
 237                                         regulator-always-on;
 238                                         regulator-boot-on;
 239                                 };
 240
 241                                 smps7_reg: smps7 {
 242                                         /* CORE_VDD */
 243                                         regulator-name = "smps7";
 244                                         regulator-min-microvolt = <850000>;
 245                                         regulator-max-microvolt = <1150000>;
 246                                         regulator-always-on;
 247                                         regulator-boot-on;
 248                                 };
 249
 250                                 smps8_reg: smps8 {
 251                                         /* VDD_IVAHD */
 252                                         regulator-name = "smps8";
 253                                         regulator-min-microvolt = < 850000>;
 254                                         regulator-max-microvolt = <1250000>;
 255                                         regulator-always-on;
 256                                         regulator-boot-on;
 257                                 };
 258
 259                                 smps9_reg: smps9 {
 260                                         /* VDDS1V8 */
 261                                         regulator-name = "smps9";
 262                                         regulator-min-microvolt = <1800000>;
 263                                         regulator-max-microvolt = <1800000>;
 264                                         regulator-always-on;
 265                                         regulator-boot-on;
 266                                 };
 267
 268                                 ldo1_reg: ldo1 {
 269                                         /* LDO1_OUT --> SDIO  */
 270                                         regulator-name = "ldo1";
 271                                         regulator-min-microvolt = <1800000>;
 272                                         regulator-max-microvolt = <3300000>;
 273                                         regulator-always-on;
 274                                         regulator-boot-on;
 275                                 };
 276
 277                                 ldo2_reg: ldo2 {
 278                                         /* VDD_RTCIO */
 279                                         /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
 280                                         regulator-name = "ldo2";
 281                                         regulator-min-microvolt = <3300000>;
 282                                         regulator-max-microvolt = <3300000>;
 283                                         regulator-always-on;
 284                                         regulator-boot-on;
 285                                 };
 286
 287                                 ldo3_reg: ldo3 {
 288                                         /* VDDA_1V8_PHY */
 289                                         regulator-name = "ldo3";
 290                                         regulator-min-microvolt = <1800000>;
 291                                         regulator-max-microvolt = <1800000>;
 292                                         regulator-always-on;
 293                                         regulator-boot-on;
 294                                 };
 295
 296                                 ldo9_reg: ldo9 {
 297                                         /* VDD_RTC */
 298                                         regulator-name = "ldo9";
 299                                         regulator-min-microvolt = <1050000>;
 300                                         regulator-max-microvolt = <1050000>;
 301                                         regulator-always-on;
 302                                         regulator-boot-on;
 303                                         regulator-allow-bypass;
 304                                 };
 305
 306                                 ldoln_reg: ldoln {
 307                                         /* VDDA_1V8_PLL */
 308                                         regulator-name = "ldoln";
 309                                         regulator-min-microvolt = <1800000>;
 310                                         regulator-max-microvolt = <1800000>;
 311                                         regulator-always-on;
 312                                         regulator-boot-on;
 313                                 };
 314
 315                                 ldousb_reg: ldousb {
 316                                         /* VDDA_3V_USB: VDDA_USBHS33 */
 317                                         regulator-name = "ldousb";
 318                                         regulator-min-microvolt = <3300000>;
 319                                         regulator-max-microvolt = <3300000>;
 320                                         regulator-boot-on;
 321                                 };
 322
 323                                 /* REGEN1 is unused */
 324
 325                                 regen2: regen2 {
 326                                         /* Needed for PMIC internal resources */
 327                                         regulator-name = "regen2";
 328                                         regulator-boot-on;
 329                                         regulator-always-on;
 330                                 };
 331
 332                                 /* REGEN3 is unused */
 333
 334                                 sysen1: sysen1 {
 335                                         /* PMIC_REGEN_3V3 */
 336                                         regulator-name = "sysen1";
 337                                         regulator-boot-on;
 338                                         regulator-always-on;
 339                                 };
 340
 341                                 sysen2: sysen2 {
 342                                         /* PMIC_REGEN_DDR */
 343                                         regulator-name = "sysen2";
 344                                         regulator-boot-on;
 345                                         regulator-always-on;
 346                                 };
 347                         };
 348                 };
 349         };
 350
 351         pcf_lcd: gpio@20 {
 352                 compatible = "ti,pcf8575", "nxp,pcf8575";
 353                 reg = <0x20>;
 354                 gpio-controller;
 355                 #gpio-cells = <2>;
 356                 interrupt-parent = <&gpio6>;
 357                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 358                 interrupt-controller;
 359                 #interrupt-cells = <2>;
 360         };
 361
 362         pcf_gpio_21: gpio@21 {
 363                 compatible = "ti,pcf8575", "nxp,pcf8575";
 364                 reg = <0x21>;
 365                 lines-initial-states = <0x1408>;
 366                 gpio-controller;
 367                 #gpio-cells = <2>;
 368                 interrupt-parent = <&gpio6>;
 369                 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
 370                 interrupt-controller;
 371                 #interrupt-cells = <2>;
 372         };
 373
 374         tlv320aic3106: tlv320aic3106@19 {
 375                 #sound-dai-cells = <0>;
 376                 compatible = "ti,tlv320aic3106";
 377                 reg = <0x19>;
 378                 adc-settle-ms = <40>;
 379                 ai3x-micbias-vg = <1>;          /* 2.0V */
 380                 status = "okay";
 381
 382                 /* Regulators */
 383                 AVDD-supply = <&evm_3v3_sw>;
 384                 IOVDD-supply = <&evm_3v3_sw>;
 385                 DRVDD-supply = <&evm_3v3_sw>;
 386                 DVDD-supply = <&aic_dvdd>;
 387         };
 388 };
 389
 390 &i2c2 {
 391         status = "okay";
 392         clock-frequency = <400000>;
 393
 394         pcf_hdmi: gpio@26 {
 395                 compatible = "ti,pcf8575", "nxp,pcf8575";
 396                 reg = <0x26>;
 397                 gpio-controller;
 398                 #gpio-cells = <2>;
 399                 p1 {
 400                         /* vin6_sel_s0: high: VIN6, low: audio */
 401                         gpio-hog;
 402                         gpios = <1 GPIO_ACTIVE_HIGH>;
 403                         output-low;
 404                         line-name = "vin6_sel_s0";
 405                 };
 406         };
 407 };
 408
 409 &i2c3 {
 410         status = "okay";
 411         clock-frequency = <400000>;
 412 };
 413
 414 &mcspi1 {
 415         status = "okay";
 416 };
 417
 418 &mcspi2 {
 419         status = "okay";
 420 };
 421
 422 &uart1 {
 423         status = "okay";
 424         interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
 425                               <&dra7_pmx_core 0x3e0>;
 426 };
 427
 428 &uart2 {
 429         status = "okay";
 430 };
 431
 432 &uart3 {
 433         status = "okay";
 434 };
 435
 436 &mmc1 {
 437         status = "okay";
 438         pinctrl-names = "default";
 439         pinctrl-0 = <&mmc1_pins_default>;
 440         vmmc-supply = <&evm_3v3_sd>;
 441         vmmc_aux-supply = <&ldo1_reg>;
 442         bus-width = <4>;
 443         /*
 444          * SDCD signal is not being used here - using the fact that GPIO mode
 445          * is always hardwired.
 446          */
 447         cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
 448 };
 449
 450 &mmc2 {
 451         status = "okay";
 452         pinctrl-names = "default";
 453         pinctrl-0 = <&mmc2_pins_default>;
 454         vmmc-supply = <&evm_3v3_sw>;
 455         bus-width = <8>;
 456 };
 457
 458 &cpu0 {
 459         cpu0-supply = <&smps123_reg>;
 460 };
 461
 462 &qspi {
 463         status = "okay";
 464
 465         spi-max-frequency = <76800000>;
 466         m25p80@0 {
 467                 compatible = "s25fl256s1";
 468                 spi-max-frequency = <76800000>;
 469                 reg = <0>;
 470                 spi-tx-bus-width = <1>;
 471                 spi-rx-bus-width = <4>;
 472                 #address-cells = <1>;
 473                 #size-cells = <1>;
 474
 475                 /* MTD partition table.
 476                  * The ROM checks the first four physical blocks
 477                  * for a valid file to boot and the flash here is
 478                  * 64KiB block size.
 479                  */
 480                 partition@0 {
 481                         label = "QSPI.SPL";
 482                         reg = <0x00000000 0x000010000>;
 483                 };
 484                 partition@1 {
 485                         label = "QSPI.SPL.backup1";
 486                         reg = <0x00010000 0x00010000>;
 487                 };
 488                 partition@2 {
 489                         label = "QSPI.SPL.backup2";
 490                         reg = <0x00020000 0x00010000>;
 491                 };
 492                 partition@3 {
 493                         label = "QSPI.SPL.backup3";
 494                         reg = <0x00030000 0x00010000>;
 495                 };
 496                 partition@4 {
 497                         label = "QSPI.u-boot";
 498                         reg = <0x00040000 0x00100000>;
 499                 };
 500                 partition@5 {
 501                         label = "QSPI.u-boot-spl-os";
 502                         reg = <0x00140000 0x00080000>;
 503                 };
 504                 partition@6 {
 505                         label = "QSPI.u-boot-env";
 506                         reg = <0x001c0000 0x00010000>;
 507                 };
 508                 partition@7 {
 509                         label = "QSPI.u-boot-env.backup1";
 510                         reg = <0x001d0000 0x0010000>;
 511                 };
 512                 partition@8 {
 513                         label = "QSPI.kernel";
 514                         reg = <0x001e0000 0x0800000>;
 515                 };
 516                 partition@9 {
 517                         label = "QSPI.file-system";
 518                         reg = <0x009e0000 0x01620000>;
 519                 };
 520         };
 521 };
 522
 523 &omap_dwc3_1 {
 524         extcon = <&extcon_usb1>;
 525 };
 526
 527 &omap_dwc3_2 {
 528         extcon = <&extcon_usb2>;
 529 };
 530
 531 &usb1 {
 532         dr_mode = "otg";
 533         extcon = <&extcon_usb1>;
 534 };
 535
 536 &usb2 {
 537         dr_mode = "host";
 538 };
 539
 540 &elm {
 541         status = "okay";
 542 };
 543
 544 &gpmc {
 545         /*
 546         * For the existing IOdelay configuration via U-Boot we don't
 547         * support NAND on dra7-evm. Keep it disabled. Enabling it
 548         * requires a different configuration by U-Boot.
 549         */
 550         status = "disabled";
 551         ranges = <0 0 0x08000000 0x01000000>;   /* minimum GPMC partition = 16MB */
 552         nand@0,0 {
 553                 compatible = "ti,omap2-nand";
 554                 reg = <0 0 4>;          /* device IO registers */
 555                 interrupt-parent = <&gpmc>;
 556                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 557                              <1 IRQ_TYPE_NONE>; /* termcount */
 558                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
 559                 ti,nand-ecc-opt = "bch8";
 560                 ti,elm-id = <&elm>;
 561                 nand-bus-width = <16>;
 562                 gpmc,device-width = <2>;
 563                 gpmc,sync-clk-ps = <0>;
 564                 gpmc,cs-on-ns = <0>;
 565                 gpmc,cs-rd-off-ns = <80>;
 566                 gpmc,cs-wr-off-ns = <80>;
 567                 gpmc,adv-on-ns = <0>;
 568                 gpmc,adv-rd-off-ns = <60>;
 569                 gpmc,adv-wr-off-ns = <60>;
 570                 gpmc,we-on-ns = <10>;
 571                 gpmc,we-off-ns = <50>;
 572                 gpmc,oe-on-ns = <4>;
 573                 gpmc,oe-off-ns = <40>;
 574                 gpmc,access-ns = <40>;
 575                 gpmc,wr-access-ns = <80>;
 576                 gpmc,rd-cycle-ns = <80>;
 577                 gpmc,wr-cycle-ns = <80>;
 578                 gpmc,bus-turnaround-ns = <0>;
 579                 gpmc,cycle2cycle-delay-ns = <0>;
 580                 gpmc,clk-activation-ns = <0>;
 581                 gpmc,wr-data-mux-bus-ns = <0>;
 582                 /* MTD partition table */
 583                 /* All SPL-* partitions are sized to minimal length
 584                  * which can be independently programmable. For
 585                  * NAND flash this is equal to size of erase-block */
 586                 #address-cells = <1>;
 587                 #size-cells = <1>;
 588                 partition@0 {
 589                         label = "NAND.SPL";
 590                         reg = <0x00000000 0x000020000>;
 591                 };
 592                 partition@1 {
 593                         label = "NAND.SPL.backup1";
 594                         reg = <0x00020000 0x00020000>;
 595                 };
 596                 partition@2 {
 597                         label = "NAND.SPL.backup2";
 598                         reg = <0x00040000 0x00020000>;
 599                 };
 600                 partition@3 {
 601                         label = "NAND.SPL.backup3";
 602                         reg = <0x00060000 0x00020000>;
 603                 };
 604                 partition@4 {
 605                         label = "NAND.u-boot-spl-os";
 606                         reg = <0x00080000 0x00040000>;
 607                 };
 608                 partition@5 {
 609                         label = "NAND.u-boot";
 610                         reg = <0x000c0000 0x00100000>;
 611                 };
 612                 partition@6 {
 613                         label = "NAND.u-boot-env";
 614                         reg = <0x001c0000 0x00020000>;
 615                 };
 616                 partition@7 {
 617                         label = "NAND.u-boot-env.backup1";
 618                         reg = <0x001e0000 0x00020000>;
 619                 };
 620                 partition@8 {
 621                         label = "NAND.kernel";
 622                         reg = <0x00200000 0x00800000>;
 623                 };
 624                 partition@9 {
 625                         label = "NAND.file-system";
 626                         reg = <0x00a00000 0x0f600000>;
 627                 };
 628         };
 629 };
 630
 631 &usb2_phy1 {
 632         phy-supply = <&ldousb_reg>;
 633 };
 634
 635 &usb2_phy2 {
 636         phy-supply = <&ldousb_reg>;
 637 };
 638
 639 &gpio7 {
 640         ti,no-reset-on-init;
 641         ti,no-idle-on-init;
 642 };
 643
 644 &mac {
 645         status = "okay";
 646         dual_emac;
 647 };
 648
 649 &cpsw_emac0 {
 650         phy_id = <&davinci_mdio>, <2>;
 651         phy-mode = "rgmii";
 652         dual_emac_res_vlan = <1>;
 653 };
 654
 655 &cpsw_emac1 {
 656         phy_id = <&davinci_mdio>, <3>;
 657         phy-mode = "rgmii";
 658         dual_emac_res_vlan = <2>;
 659 };
 660
 661 &dcan1 {
 662         status = "ok";
 663         pinctrl-names = "default", "sleep", "active";
 664         pinctrl-0 = <&dcan1_pins_sleep>;
 665         pinctrl-1 = <&dcan1_pins_sleep>;
 666         pinctrl-2 = <&dcan1_pins_default>;
 667 };
 668
 669 &atl {
 670         assigned-clocks = <&abe_dpll_sys_clk_mux>,
 671                           <&atl_gfclk_mux>,
 672                           <&dpll_abe_ck>,
 673                           <&dpll_abe_m2x2_ck>,
 674                           <&atl_clkin2_ck>;
 675         assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>;
 676         assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>;
 677
 678         status = "okay";
 679
 680         atl2 {
 681                 bws = <DRA7_ATL_WS_MCASP2_FSX>;
 682                 aws = <DRA7_ATL_WS_MCASP3_FSX>;
 683         };
 684 };
 685
 686 &mcasp3 {
 687         #sound-dai-cells = <0>;
 688
 689         assigned-clocks = <&mcasp3_ahclkx_mux>;
 690         assigned-clock-parents = <&atl_clkin2_ck>;
 691
 692         status = "okay";
 693
 694         op-mode = <0>;          /* MCASP_IIS_MODE */
 695         tdm-slots = <2>;
 696         /* 4 serializer */
 697         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
 698                 1 2 0 0
 699         >;
 700         tx-num-evt = <32>;
 701         rx-num-evt = <32>;
 702 };
 703
 704 &mailbox5 {
 705         status = "okay";
 706         mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
 707                 status = "okay";
 708         };
 709         mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
 710                 status = "okay";
 711         };
 712 };
 713
 714 &mailbox6 {
 715         status = "okay";
 716         mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
 717                 status = "okay";
 718         };
 719         mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
 720                 status = "okay";
 721         };
 722 };