arch/arm/boot/dts/da850.dtsi

   1 /*
   2  * Copyright 2012 DENX Software Engineering GmbH
   3  * Heiko Schocher <hs@denx.de>
   4  *
   5  * This program is free software; you can redistribute  it and/or modify it
   6  * under  the terms of  the GNU General  Public License as published by the
   7  * Free Software Foundation;  either version 2 of the  License, or (at your
   8  * option) any later version.
   9  */
  10 #include "skeleton.dtsi"
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12
  13 / {
  14         arm {
  15                 #address-cells = <1>;
  16                 #size-cells = <1>;
  17                 ranges;
  18                 intc: interrupt-controller {
  19                         compatible = "ti,cp-intc";
  20                         interrupt-controller;
  21                         #interrupt-cells = <1>;
  22                         ti,intc-size = <100>;
  23                         reg = <0xfffee000 0x2000>;
  24                 };
  25         };
  26         soc {
  27                 compatible = "simple-bus";
  28                 model = "da850";
  29                 #address-cells = <1>;
  30                 #size-cells = <1>;
  31                 ranges = <0x0 0x01c00000 0x400000>;
  32                 interrupt-parent = <&intc>;
  33
  34                 pmx_core: pinmux@1c14120 {
  35                         compatible = "pinctrl-single";
  36                         reg = <0x14120 0x50>;
  37                         #address-cells = <1>;
  38                         #size-cells = <0>;
  39                         pinctrl-single,bit-per-mux;
  40                         pinctrl-single,register-width = <32>;
  41                         pinctrl-single,function-mask = <0xf>;
  42                         status = "disabled";
  43
  44                         nand_cs3_pins: pinmux_nand_pins {
  45                                 pinctrl-single,bits = <
  46                                         /* EMA_OE, EMA_WE */
  47                                         0x1c 0x00110000  0x00ff0000
  48                                         /* EMA_CS[4],EMA_CS[3]*/
  49                                         0x1c 0x00000110  0x00000ff0
  50                                         /*
  51                                          * EMA_D[0], EMA_D[1], EMA_D[2],
  52                                          * EMA_D[3], EMA_D[4], EMA_D[5],
  53                                          * EMA_D[6], EMA_D[7]
  54                                          */
  55                                         0x24 0x11111111  0xffffffff
  56                                         /* EMA_A[1], EMA_A[2] */
  57                                         0x30 0x01100000  0x0ff00000
  58                                 >;
  59                         };
  60                         i2c0_pins: pinmux_i2c0_pins {
  61                                 pinctrl-single,bits = <
  62                                         /* I2C0_SDA,I2C0_SCL */
  63                                         0x10 0x00002200 0x0000ff00
  64                                 >;
  65                         };
  66                         mmc0_pins: pinmux_mmc_pins {
  67                                 pinctrl-single,bits = <
  68                                         /* MMCSD0_DAT[3] MMCSD0_DAT[2]
  69                                          * MMCSD0_DAT[1] MMCSD0_DAT[0]
  70                                          * MMCSD0_CMD    MMCSD0_CLK
  71                                          */
  72                                         0x28 0x00222222  0x00ffffff
  73                                 >;
  74                         };
  75                         ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
  76                                 pinctrl-single,bits = <
  77                                         /* EPWM0A */
  78                                         0xc 0x00000002 0x0000000f
  79                                 >;
  80                         };
  81                         ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
  82                                 pinctrl-single,bits = <
  83                                         /* EPWM0B */
  84                                         0xc 0x00000020 0x000000f0
  85                                 >;
  86                         };
  87                         ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
  88                                 pinctrl-single,bits = <
  89                                         /* EPWM1A */
  90                                         0x14 0x00000002 0x0000000f
  91                                 >;
  92                         };
  93                         ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
  94                                 pinctrl-single,bits = <
  95                                         /* EPWM1B */
  96                                         0x14 0x00000020 0x000000f0
  97                                 >;
  98                         };
  99                         ecap0_pins: pinmux_ecap0_pins {
 100                                 pinctrl-single,bits = <
 101                                         /* ECAP0_APWM0 */
 102                                         0x8 0x20000000 0xf0000000
 103                                 >;
 104                         };
 105                         ecap1_pins: pinmux_ecap1_pins {
 106                                 pinctrl-single,bits = <
 107                                         /* ECAP1_APWM1 */
 108                                         0x4 0x40000000 0xf0000000
 109                                 >;
 110                         };
 111                         ecap2_pins: pinmux_ecap2_pins {
 112                                 pinctrl-single,bits = <
 113                                         /* ECAP2_APWM2 */
 114                                         0x4 0x00000004 0x0000000f
 115                                 >;
 116                         };
 117                         spi1_pins: pinmux_spi_pins {
 118                                 pinctrl-single,bits = <
 119                                         /* SIMO, SOMI, CLK */
 120                                         0x14 0x00110100 0x00ff0f00
 121                                 >;
 122                         };
 123                         spi1_cs0_pin: pinmux_spi1_cs0 {
 124                                 pinctrl-single,bits = <
 125                                         /* CS0 */
 126                                         0x14 0x00000010 0x000000f0
 127                                 >;
 128                         };
 129                         mdio_pins: pinmux_mdio_pins {
 130                                 pinctrl-single,bits = <
 131                                         /* MDIO_CLK, MDIO_D */
 132                                         0x10 0x00000088 0x000000ff
 133                                 >;
 134                         };
 135                         mii_pins: pinmux_mii_pins {
 136                                 pinctrl-single,bits = <
 137                                         /*
 138                                          * MII_TXEN, MII_TXCLK, MII_COL
 139                                          * MII_TXD_3, MII_TXD_2, MII_TXD_1
 140                                          * MII_TXD_0
 141                                          */
 142                                         0x8 0x88888880 0xfffffff0
 143                                         /*
 144                                          * MII_RXER, MII_CRS, MII_RXCLK
 145                                          * MII_RXDV, MII_RXD_3, MII_RXD_2
 146                                          * MII_RXD_1, MII_RXD_0
 147                                          */
 148                                         0xc 0x88888888 0xffffffff
 149                                 >;
 150                         };
 151
 152                 };
 153                 edma0: edma@01c00000 {
 154                         compatible = "ti,edma3-tpcc";
 155                         /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
 156                         reg =   <0x0 0x8000>;
 157                         reg-names = "edma3_cc";
 158                         interrupts = <11 12>;
 159                         interrupt-names = "edma3_ccint", "edma3_ccerrint";
 160                         #dma-cells = <2>;
 161
 162                         ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
 163                 };
 164                 edma0_tptc0: tptc@01c08000 {
 165                         compatible = "ti,edma3-tptc";
 166                         reg =   <0x8000 0x400>;
 167                         interrupts = <13>;
 168                         interrupt-names = "edm3_tcerrint";
 169                 };
 170                 edma0_tptc1: tptc@01c08400 {
 171                         compatible = "ti,edma3-tptc";
 172                         reg =   <0x8400 0x400>;
 173                         interrupts = <32>;
 174                         interrupt-names = "edm3_tcerrint";
 175                 };
 176                 edma1: edma@01e30000 {
 177                         compatible = "ti,edma3-tpcc";
 178                         /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
 179                         reg =   <0x230000 0x8000>;
 180                         reg-names = "edma3_cc";
 181                         interrupts = <93 94>;
 182                         interrupt-names = "edma3_ccint", "edma3_ccerrint";
 183                         #dma-cells = <2>;
 184
 185                         ti,tptcs = <&edma1_tptc0 7>;
 186                 };
 187                 edma1_tptc0: tptc@01e38000 {
 188                         compatible = "ti,edma3-tptc";
 189                         reg =   <0x238000 0x400>;
 190                         interrupts = <95>;
 191                         interrupt-names = "edm3_tcerrint";
 192                 };
 193                 serial0: serial@1c42000 {
 194                         compatible = "ns16550a";
 195                         reg = <0x42000 0x100>;
 196                         reg-shift = <2>;
 197                         interrupts = <25>;
 198                         status = "disabled";
 199                 };
 200                 serial1: serial@1d0c000 {
 201                         compatible = "ns16550a";
 202                         reg = <0x10c000 0x100>;
 203                         reg-shift = <2>;
 204                         interrupts = <53>;
 205                         status = "disabled";
 206                 };
 207                 serial2: serial@1d0d000 {
 208                         compatible = "ns16550a";
 209                         reg = <0x10d000 0x100>;
 210                         reg-shift = <2>;
 211                         interrupts = <61>;
 212                         status = "disabled";
 213                 };
 214                 rtc0: rtc@1c23000 {
 215                         compatible = "ti,da830-rtc";
 216                         reg = <0x23000 0x1000>;
 217                         interrupts = <19
 218                                       19>;
 219                         status = "disabled";
 220                 };
 221                 i2c0: i2c@1c22000 {
 222                         compatible = "ti,davinci-i2c";
 223                         reg = <0x22000 0x1000>;
 224                         interrupts = <15>;
 225                         #address-cells = <1>;
 226                         #size-cells = <0>;
 227                         status = "disabled";
 228                 };
 229                 wdt: wdt@1c21000 {
 230                         compatible = "ti,davinci-wdt";
 231                         reg = <0x21000 0x1000>;
 232                         status = "disabled";
 233                 };
 234                 mmc0: mmc@1c40000 {
 235                         compatible = "ti,da830-mmc";
 236                         reg = <0x40000 0x1000>;
 237                         interrupts = <16>;
 238                         dmas = <&edma0 16 0>, <&edma0 17 0>;
 239                         dma-names = "rx", "tx";
 240                         status = "disabled";
 241                 };
 242                 mmc1: mmc@1e1b000 {
 243                         compatible = "ti,da830-mmc";
 244                         reg = <0x21b000 0x1000>;
 245                         interrupts = <72>;
 246                         dmas = <&edma1 28 0>, <&edma1 29 0>;
 247                         dma-names = "rx", "tx";
 248                         status = "disabled";
 249                 };
 250                 ehrpwm0: ehrpwm@01f00000 {
 251                         compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
 252                         #pwm-cells = <3>;
 253                         reg = <0x300000 0x2000>;
 254                         status = "disabled";
 255                 };
 256                 ehrpwm1: ehrpwm@01f02000 {
 257                         compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
 258                         #pwm-cells = <3>;
 259                         reg = <0x302000 0x2000>;
 260                         status = "disabled";
 261                 };
 262                 ecap0: ecap@01f06000 {
 263                         compatible = "ti,da850-ecap", "ti,am33xx-ecap";
 264                         #pwm-cells = <3>;
 265                         reg = <0x306000 0x80>;
 266                         status = "disabled";
 267                 };
 268                 ecap1: ecap@01f07000 {
 269                         compatible = "ti,da850-ecap", "ti,am33xx-ecap";
 270                         #pwm-cells = <3>;
 271                         reg = <0x307000 0x80>;
 272                         status = "disabled";
 273                 };
 274                 ecap2: ecap@01f08000 {
 275                         compatible = "ti,da850-ecap", "ti,am33xx-ecap";
 276                         #pwm-cells = <3>;
 277                         reg = <0x308000 0x80>;
 278                         status = "disabled";
 279                 };
 280                 spi1: spi@1f0e000 {
 281                         #address-cells = <1>;
 282                         #size-cells = <0>;
 283                         compatible = "ti,da830-spi";
 284                         reg = <0x30e000 0x1000>;
 285                         num-cs = <4>;
 286                         ti,davinci-spi-intr-line = <1>;
 287                         interrupts = <56>;
 288                         dmas = <&edma0 18 0>, <&edma0 19 0>;
 289                         dma-names = "rx", "tx";
 290                         status = "disabled";
 291                 };
 292                 mdio: mdio@1e24000 {
 293                         compatible = "ti,davinci_mdio";
 294                         #address-cells = <1>;
 295                         #size-cells = <0>;
 296                         reg = <0x224000 0x1000>;
 297                 };
 298                 eth0: ethernet@1e20000 {
 299                         compatible = "ti,davinci-dm6467-emac";
 300                         reg = <0x220000 0x4000>;
 301                         ti,davinci-ctrl-reg-offset = <0x3000>;
 302                         ti,davinci-ctrl-mod-reg-offset = <0x2000>;
 303                         ti,davinci-ctrl-ram-offset = <0>;
 304                         ti,davinci-ctrl-ram-size = <0x2000>;
 305                         local-mac-address = [ 00 00 00 00 00 00 ];
 306                         interrupts = <33
 307                                         34
 308                                         35
 309                                         36
 310                                         >;
 311                 };
 312                 gpio: gpio@1e26000 {
 313                         compatible = "ti,dm6441-gpio";
 314                         gpio-controller;
 315                         reg = <0x226000 0x1000>;
 316                         interrupts = <42 IRQ_TYPE_EDGE_BOTH
 317                                 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
 318                                 45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
 319                                 47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
 320                                 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
 321                         ti,ngpio = <144>;
 322                         ti,davinci-gpio-unbanked = <0>;
 323                         status = "disabled";
 324                 };
 325
 326                 mcasp0: mcasp@01d00000 {
 327                         compatible = "ti,da830-mcasp-audio";
 328                         reg = <0x100000 0x2000>,
 329                               <0x102000 0x400000>;
 330                         reg-names = "mpu", "dat";
 331                         interrupts = <54>;
 332                         interrupt-names = "common";
 333                         status = "disabled";
 334                         dmas = <&edma0 1 1>,
 335                                 <&edma0 0 1>;
 336                         dma-names = "tx", "rx";
 337                 };
 338         };
 339         nand_cs3@62000000 {
 340                 compatible = "ti,davinci-nand";
 341                 reg = <0x62000000 0x807ff
 342                        0x68000000 0x8000>;
 343                 ti,davinci-chipselect = <1>;
 344                 ti,davinci-mask-ale = <0>;
 345                 ti,davinci-mask-cle = <0>;
 346                 ti,davinci-mask-chipsel = <0>;
 347                 ti,davinci-ecc-mode = "hw";
 348                 ti,davinci-ecc-bits = <4>;
 349                 ti,davinci-nand-use-bbt;
 350                 status = "disabled";
 351         };
 352 };