arch/arm/boot/dts/berlin2q.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
   4  */
   5
   6 #include <dt-bindings/clock/berlin2q.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8
   9 / {
  10         model = "Marvell Armada 1500 pro (BG2-Q) SoC";
  11         compatible = "marvell,berlin2q", "marvell,berlin";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         aliases {
  16                 serial0 = &uart0;
  17                 serial1 = &uart1;
  18         };
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23                 enable-method = "marvell,berlin-smp";
  24
  25                 cpu0: cpu@0 {
  26                         compatible = "arm,cortex-a9";
  27                         device_type = "cpu";
  28                         next-level-cache = <&l2>;
  29                         reg = <0>;
  30
  31                         clocks = <&chip_clk CLKID_CPU>;
  32                         clock-latency = <100000>;
  33                         /* Can be modified by the bootloader */
  34                         operating-points = <
  35                                 /* kHz    uV */
  36                                 1200000 1200000
  37                                 1000000 1200000
  38                                 800000  1200000
  39                                 600000  1200000
  40                         >;
  41                 };
  42
  43                 cpu1: cpu@1 {
  44                         compatible = "arm,cortex-a9";
  45                         device_type = "cpu";
  46                         next-level-cache = <&l2>;
  47                         reg = <1>;
  48
  49                         clocks = <&chip_clk CLKID_CPU>;
  50                         clock-latency = <100000>;
  51                         /* Can be modified by the bootloader */
  52                         operating-points = <
  53                                 /* kHz    uV */
  54                                 1200000 1200000
  55                                 1000000 1200000
  56                                 800000  1200000
  57                                 600000  1200000
  58                         >;
  59                 };
  60
  61                 cpu2: cpu@2 {
  62                         compatible = "arm,cortex-a9";
  63                         device_type = "cpu";
  64                         next-level-cache = <&l2>;
  65                         reg = <2>;
  66
  67                         clocks = <&chip_clk CLKID_CPU>;
  68                         clock-latency = <100000>;
  69                         /* Can be modified by the bootloader */
  70                         operating-points = <
  71                                 /* kHz    uV */
  72                                 1200000 1200000
  73                                 1000000 1200000
  74                                 800000  1200000
  75                                 600000  1200000
  76                         >;
  77                 };
  78
  79                 cpu3: cpu@3 {
  80                         compatible = "arm,cortex-a9";
  81                         device_type = "cpu";
  82                         next-level-cache = <&l2>;
  83                         reg = <3>;
  84
  85                         clocks = <&chip_clk CLKID_CPU>;
  86                         clock-latency = <100000>;
  87                         /* Can be modified by the bootloader */
  88                         operating-points = <
  89                                 /* kHz    uV */
  90                                 1200000 1200000
  91                                 1000000 1200000
  92                                 800000  1200000
  93                                 600000  1200000
  94                         >;
  95                 };
  96         };
  97
  98         pmu {
  99                 compatible = "arm,cortex-a9-pmu";
 100                 interrupt-parent = <&gic>;
 101                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
 102                              <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 103                              <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 104                              <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 105                 interrupt-affinity = <&cpu0>,
 106                                      <&cpu1>,
 107                                      <&cpu2>,
 108                                      <&cpu3>;
 109         };
 110
 111         refclk: oscillator {
 112                 compatible = "fixed-clock";
 113                 #clock-cells = <0>;
 114                 clock-frequency = <25000000>;
 115         };
 116
 117         soc@f7000000 {
 118                 compatible = "simple-bus";
 119                 #address-cells = <1>;
 120                 #size-cells = <1>;
 121
 122                 ranges = <0 0xf7000000 0x1000000>;
 123                 interrupt-parent = <&gic>;
 124
 125                 sdhci0: sdhci@ab0000 {
 126                         compatible = "mrvl,pxav3-mmc";
 127                         reg = <0xab0000 0x200>;
 128                         clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
 129                         clock-names = "io", "core";
 130                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 131                         status = "disabled";
 132                 };
 133
 134                 sdhci1: sdhci@ab0800 {
 135                         compatible = "mrvl,pxav3-mmc";
 136                         reg = <0xab0800 0x200>;
 137                         clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>;
 138                         clock-names = "io", "core";
 139                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 140                         status = "disabled";
 141                 };
 142
 143                 sdhci2: sdhci@ab1000 {
 144                         compatible = "mrvl,pxav3-mmc";
 145                         reg = <0xab1000 0x200>;
 146                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 147                         clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_SDIO>;
 148                         clock-names = "io", "core";
 149                         status = "disabled";
 150                 };
 151
 152                 l2: l2-cache-controller@ac0000 {
 153                         compatible = "arm,pl310-cache";
 154                         reg = <0xac0000 0x1000>;
 155                         cache-unified;
 156                         cache-level = <2>;
 157                         arm,data-latency = <2 2 2>;
 158                         arm,tag-latency = <2 2 2>;
 159                 };
 160
 161                 scu: snoop-control-unit@ad0000 {
 162                         compatible = "arm,cortex-a9-scu";
 163                         reg = <0xad0000 0x58>;
 164                 };
 165
 166                 local-timer@ad0600 {
 167                         compatible = "arm,cortex-a9-twd-timer";
 168                         reg = <0xad0600 0x20>;
 169                         clocks = <&chip_clk CLKID_TWD>;
 170                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 171                 };
 172
 173                 gic: interrupt-controller@ad1000 {
 174                         compatible = "arm,cortex-a9-gic";
 175                         reg = <0xad1000 0x1000>, <0xad0100 0x100>;
 176                         interrupt-controller;
 177                         #interrupt-cells = <3>;
 178                 };
 179
 180                 usb_phy2: phy@a2f400 {
 181                         compatible = "marvell,berlin2cd-usb-phy";
 182                         reg = <0xa2f400 0x128>;
 183                         #phy-cells = <0>;
 184                         resets = <&chip_rst 0x104 14>;
 185                         status = "disabled";
 186                 };
 187
 188                 usb2: usb@a30000 {
 189                         compatible = "chipidea,usb2";
 190                         reg = <0xa30000 0x10000>;
 191                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 192                         clocks = <&chip_clk CLKID_USB2>;
 193                         phys = <&usb_phy2>;
 194                         phy-names = "usb-phy";
 195                         status = "disabled";
 196                 };
 197
 198                 usb_phy0: phy@b74000 {
 199                         compatible = "marvell,berlin2cd-usb-phy";
 200                         reg = <0xb74000 0x128>;
 201                         #phy-cells = <0>;
 202                         resets = <&chip_rst 0x104 12>;
 203                         status = "disabled";
 204                 };
 205
 206                 usb_phy1: phy@b78000 {
 207                         compatible = "marvell,berlin2cd-usb-phy";
 208                         reg = <0xb78000 0x128>;
 209                         #phy-cells = <0>;
 210                         resets = <&chip_rst 0x104 13>;
 211                         status = "disabled";
 212                 };
 213
 214                 eth0: ethernet@b90000 {
 215                         compatible = "marvell,pxa168-eth";
 216                         reg = <0xb90000 0x10000>;
 217                         clocks = <&chip_clk CLKID_GETH0>;
 218                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 219                         /* set by bootloader */
 220                         local-mac-address = [00 00 00 00 00 00];
 221                         #address-cells = <1>;
 222                         #size-cells = <0>;
 223                         phy-connection-type = "mii";
 224                         phy-handle = <&ethphy0>;
 225                         status = "disabled";
 226
 227                         ethphy0: ethernet-phy@0 {
 228                                 reg = <0>;
 229                         };
 230                 };
 231
 232                 cpu-ctrl@dd0000 {
 233                         compatible = "marvell,berlin-cpu-ctrl";
 234                         reg = <0xdd0000 0x10000>;
 235                 };
 236
 237                 apb@e80000 {
 238                         compatible = "simple-bus";
 239                         #address-cells = <1>;
 240                         #size-cells = <1>;
 241
 242                         ranges = <0 0xe80000 0x10000>;
 243                         interrupt-parent = <&aic>;
 244
 245                         gpio0: gpio@400 {
 246                                 compatible = "snps,dw-apb-gpio";
 247                                 reg = <0x0400 0x400>;
 248                                 #address-cells = <1>;
 249                                 #size-cells = <0>;
 250
 251                                 porta: gpio-port@0 {
 252                                         compatible = "snps,dw-apb-gpio-port";
 253                                         gpio-controller;
 254                                         #gpio-cells = <2>;
 255                                         snps,nr-gpios = <32>;
 256                                         reg = <0>;
 257                                         interrupt-controller;
 258                                         #interrupt-cells = <2>;
 259                                         interrupts = <0>;
 260                                 };
 261                         };
 262
 263                         gpio1: gpio@800 {
 264                                 compatible = "snps,dw-apb-gpio";
 265                                 reg = <0x0800 0x400>;
 266                                 #address-cells = <1>;
 267                                 #size-cells = <0>;
 268
 269                                 portb: gpio-port@1 {
 270                                         compatible = "snps,dw-apb-gpio-port";
 271                                         gpio-controller;
 272                                         #gpio-cells = <2>;
 273                                         snps,nr-gpios = <32>;
 274                                         reg = <0>;
 275                                         interrupt-controller;
 276                                         #interrupt-cells = <2>;
 277                                         interrupts = <1>;
 278                                 };
 279                         };
 280
 281                         gpio2: gpio@c00 {
 282                                 compatible = "snps,dw-apb-gpio";
 283                                 reg = <0x0c00 0x400>;
 284                                 #address-cells = <1>;
 285                                 #size-cells = <0>;
 286
 287                                 portc: gpio-port@2 {
 288                                         compatible = "snps,dw-apb-gpio-port";
 289                                         gpio-controller;
 290                                         #gpio-cells = <2>;
 291                                         snps,nr-gpios = <32>;
 292                                         reg = <0>;
 293                                         interrupt-controller;
 294                                         #interrupt-cells = <2>;
 295                                         interrupts = <2>;
 296                                 };
 297                         };
 298
 299                         gpio3: gpio@1000 {
 300                                 compatible = "snps,dw-apb-gpio";
 301                                 reg = <0x1000 0x400>;
 302                                 #address-cells = <1>;
 303                                 #size-cells = <0>;
 304
 305                                 portd: gpio-port@3 {
 306                                         compatible = "snps,dw-apb-gpio-port";
 307                                         gpio-controller;
 308                                         #gpio-cells = <2>;
 309                                         snps,nr-gpios = <32>;
 310                                         reg = <0>;
 311                                         interrupt-controller;
 312                                         #interrupt-cells = <2>;
 313                                         interrupts = <3>;
 314                                 };
 315                         };
 316
 317                         i2c0: i2c@1400 {
 318                                 compatible = "snps,designware-i2c";
 319                                 #address-cells = <1>;
 320                                 #size-cells = <0>;
 321                                 reg = <0x1400 0x100>;
 322                                 interrupts = <4>;
 323                                 clocks = <&chip_clk CLKID_CFG>;
 324                                 pinctrl-0 = <&twsi0_pmux>;
 325                                 pinctrl-names = "default";
 326                                 status = "disabled";
 327                         };
 328
 329                         i2c1: i2c@1800 {
 330                                 compatible = "snps,designware-i2c";
 331                                 #address-cells = <1>;
 332                                 #size-cells = <0>;
 333                                 reg = <0x1800 0x100>;
 334                                 interrupts = <5>;
 335                                 clocks = <&chip_clk CLKID_CFG>;
 336                                 pinctrl-0 = <&twsi1_pmux>;
 337                                 pinctrl-names = "default";
 338                                 status = "disabled";
 339                         };
 340
 341                         timer0: timer@2c00 {
 342                                 compatible = "snps,dw-apb-timer";
 343                                 reg = <0x2c00 0x14>;
 344                                 clocks = <&chip_clk CLKID_CFG>;
 345                                 clock-names = "timer";
 346                                 interrupts = <8>;
 347                         };
 348
 349                         timer1: timer@2c14 {
 350                                 compatible = "snps,dw-apb-timer";
 351                                 reg = <0x2c14 0x14>;
 352                                 clocks = <&chip_clk CLKID_CFG>;
 353                                 clock-names = "timer";
 354                         };
 355
 356                         timer2: timer@2c28 {
 357                                 compatible = "snps,dw-apb-timer";
 358                                 reg = <0x2c28 0x14>;
 359                                 clocks = <&chip_clk CLKID_CFG>;
 360                                 clock-names = "timer";
 361                                 status = "disabled";
 362                         };
 363
 364                         timer3: timer@2c3c {
 365                                 compatible = "snps,dw-apb-timer";
 366                                 reg = <0x2c3c 0x14>;
 367                                 clocks = <&chip_clk CLKID_CFG>;
 368                                 clock-names = "timer";
 369                                 status = "disabled";
 370                         };
 371
 372                         timer4: timer@2c50 {
 373                                 compatible = "snps,dw-apb-timer";
 374                                 reg = <0x2c50 0x14>;
 375                                 clocks = <&chip_clk CLKID_CFG>;
 376                                 clock-names = "timer";
 377                                 status = "disabled";
 378                         };
 379
 380                         timer5: timer@2c64 {
 381                                 compatible = "snps,dw-apb-timer";
 382                                 reg = <0x2c64 0x14>;
 383                                 clocks = <&chip_clk CLKID_CFG>;
 384                                 clock-names = "timer";
 385                                 status = "disabled";
 386                         };
 387
 388                         timer6: timer@2c78 {
 389                                 compatible = "snps,dw-apb-timer";
 390                                 reg = <0x2c78 0x14>;
 391                                 clocks = <&chip_clk CLKID_CFG>;
 392                                 clock-names = "timer";
 393                                 status = "disabled";
 394                         };
 395
 396                         timer7: timer@2c8c {
 397                                 compatible = "snps,dw-apb-timer";
 398                                 reg = <0x2c8c 0x14>;
 399                                 clocks = <&chip_clk CLKID_CFG>;
 400                                 clock-names = "timer";
 401                                 status = "disabled";
 402                         };
 403
 404                         aic: interrupt-controller@3800 {
 405                                 compatible = "snps,dw-apb-ictl";
 406                                 reg = <0x3800 0x30>;
 407                                 interrupt-controller;
 408                                 #interrupt-cells = <1>;
 409                                 interrupt-parent = <&gic>;
 410                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 411                         };
 412                 };
 413
 414                 chip: chip-control@ea0000 {
 415                         compatible = "simple-mfd", "syscon";
 416                         reg = <0xea0000 0x400>, <0xdd0170 0x10>;
 417
 418                         chip_clk: clock {
 419                                 compatible = "marvell,berlin2q-clk";
 420                                 #clock-cells = <1>;
 421                                 clocks = <&refclk>;
 422                                 clock-names = "refclk";
 423                         };
 424
 425                         soc_pinctrl: pin-controller {
 426                                 compatible = "marvell,berlin2q-soc-pinctrl";
 427
 428                                 sd1_pmux: sd1-pmux {
 429                                         groups = "G31";
 430                                         function = "sd1";
 431                                 };
 432
 433                                 twsi0_pmux: twsi0-pmux {
 434                                         groups = "G6";
 435                                         function = "twsi0";
 436                                 };
 437
 438                                 twsi1_pmux: twsi1-pmux {
 439                                         groups = "G7";
 440                                         function = "twsi1";
 441                                 };
 442                         };
 443
 444                         chip_rst: reset {
 445                                 compatible = "marvell,berlin2-reset";
 446                                 #reset-cells = <2>;
 447                         };
 448                 };
 449
 450                 ahci: sata@e90000 {
 451                         compatible = "marvell,berlin2q-ahci", "generic-ahci";
 452                         reg = <0xe90000 0x1000>;
 453                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 454                         clocks = <&chip_clk CLKID_SATA>;
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457
 458                         sata0: sata-port@0 {
 459                                 reg = <0>;
 460                                 phys = <&sata_phy 0>;
 461                                 status = "disabled";
 462                         };
 463
 464                         sata1: sata-port@1 {
 465                                 reg = <1>;
 466                                 phys = <&sata_phy 1>;
 467                                 status = "disabled";
 468                         };
 469                 };
 470
 471                 sata_phy: phy@e900a0 {
 472                         compatible = "marvell,berlin2q-sata-phy";
 473                         reg = <0xe900a0 0x200>;
 474                         clocks = <&chip_clk CLKID_SATA>;
 475                         #address-cells = <1>;
 476                         #size-cells = <0>;
 477                         #phy-cells = <1>;
 478                         status = "disabled";
 479
 480                         sata-phy@0 {
 481                                 reg = <0>;
 482                         };
 483
 484                         sata-phy@1 {
 485                                 reg = <1>;
 486                         };
 487                 };
 488
 489                 usb0: usb@ed0000 {
 490                         compatible = "chipidea,usb2";
 491                         reg = <0xed0000 0x10000>;
 492                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 493                         clocks = <&chip_clk CLKID_USB0>;
 494                         phys = <&usb_phy0>;
 495                         phy-names = "usb-phy";
 496                         status = "disabled";
 497                 };
 498
 499                 usb1: usb@ee0000 {
 500                         compatible = "chipidea,usb2";
 501                         reg = <0xee0000 0x10000>;
 502                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 503                         clocks = <&chip_clk CLKID_USB1>;
 504                         phys = <&usb_phy1>;
 505                         phy-names = "usb-phy";
 506                         status = "disabled";
 507                 };
 508
 509                 pwm: pwm@f20000 {
 510                         compatible = "marvell,berlin-pwm";
 511                         reg = <0xf20000 0x40>;
 512                         clocks = <&chip_clk CLKID_CFG>;
 513                         #pwm-cells = <3>;
 514                 };
 515
 516                 apb@fc0000 {
 517                         compatible = "simple-bus";
 518                         #address-cells = <1>;
 519                         #size-cells = <1>;
 520
 521                         ranges = <0 0xfc0000 0x10000>;
 522                         interrupt-parent = <&sic>;
 523
 524                         wdt0: watchdog@1000 {
 525                                 compatible = "snps,dw-wdt";
 526                                 reg = <0x1000 0x100>;
 527                                 clocks = <&refclk>;
 528                                 interrupts = <0>;
 529                         };
 530
 531                         wdt1: watchdog@2000 {
 532                                 compatible = "snps,dw-wdt";
 533                                 reg = <0x2000 0x100>;
 534                                 clocks = <&refclk>;
 535                                 interrupts = <1>;
 536                         };
 537
 538                         wdt2: watchdog@3000 {
 539                                 compatible = "snps,dw-wdt";
 540                                 reg = <0x3000 0x100>;
 541                                 clocks = <&refclk>;
 542                                 interrupts = <2>;
 543                         };
 544
 545                         sm_gpio1: gpio@5000 {
 546                                 compatible = "snps,dw-apb-gpio";
 547                                 reg = <0x5000 0x400>;
 548                                 #address-cells = <1>;
 549                                 #size-cells = <0>;
 550
 551                                 portf: gpio-port@5 {
 552                                         compatible = "snps,dw-apb-gpio-port";
 553                                         gpio-controller;
 554                                         #gpio-cells = <2>;
 555                                         snps,nr-gpios = <32>;
 556                                         reg = <0>;
 557                                 };
 558                         };
 559
 560                         i2c2: i2c@7000 {
 561                                 compatible = "snps,designware-i2c";
 562                                 #address-cells = <1>;
 563                                 #size-cells = <0>;
 564                                 reg = <0x7000 0x100>;
 565                                 interrupts = <6>;
 566                                 clocks = <&refclk>;
 567                                 pinctrl-0 = <&twsi2_pmux>;
 568                                 pinctrl-names = "default";
 569                                 status = "disabled";
 570                         };
 571
 572                         i2c3: i2c@8000 {
 573                                 compatible = "snps,designware-i2c";
 574                                 #address-cells = <1>;
 575                                 #size-cells = <0>;
 576                                 reg = <0x8000 0x100>;
 577                                 interrupts = <7>;
 578                                 clocks = <&refclk>;
 579                                 pinctrl-0 = <&twsi3_pmux>;
 580                                 pinctrl-names = "default";
 581                                 status = "disabled";
 582                         };
 583
 584                         uart0: uart@9000 {
 585                                 compatible = "snps,dw-apb-uart";
 586                                 reg = <0x9000 0x100>;
 587                                 interrupts = <8>;
 588                                 clocks = <&refclk>;
 589                                 reg-shift = <2>;
 590                                 pinctrl-0 = <&uart0_pmux>;
 591                                 pinctrl-names = "default";
 592                                 status = "disabled";
 593                         };
 594
 595                         uart1: uart@a000 {
 596                                 compatible = "snps,dw-apb-uart";
 597                                 reg = <0xa000 0x100>;
 598                                 interrupts = <9>;
 599                                 clocks = <&refclk>;
 600                                 reg-shift = <2>;
 601                                 pinctrl-0 = <&uart1_pmux>;
 602                                 pinctrl-names = "default";
 603                                 status = "disabled";
 604                         };
 605
 606                         sm_gpio0: gpio@c000 {
 607                                 compatible = "snps,dw-apb-gpio";
 608                                 reg = <0xc000 0x400>;
 609                                 #address-cells = <1>;
 610                                 #size-cells = <0>;
 611
 612                                 porte: gpio-port@4 {
 613                                         compatible = "snps,dw-apb-gpio-port";
 614                                         gpio-controller;
 615                                         #gpio-cells = <2>;
 616                                         snps,nr-gpios = <32>;
 617                                         reg = <0>;
 618                                 };
 619                         };
 620
 621                         sysctrl: pin-controller@d000 {
 622                                 compatible = "simple-mfd", "syscon";
 623                                 reg = <0xd000 0x100>;
 624
 625                                 sys_pinctrl: pin-controller {
 626                                         compatible = "marvell,berlin2q-system-pinctrl";
 627
 628                                         uart0_pmux: uart0-pmux {
 629                                                 groups = "GSM12";
 630                                                 function = "uart0";
 631                                         };
 632
 633                                         uart1_pmux: uart1-pmux {
 634                                                 groups = "GSM14";
 635                                                 function = "uart1";
 636                                         };
 637
 638                                         twsi2_pmux: twsi2-pmux {
 639                                                 groups = "GSM13";
 640                                                 function = "twsi2";
 641                                         };
 642
 643                                         twsi3_pmux: twsi3-pmux {
 644                                                 groups = "GSM14";
 645                                                 function = "twsi3";
 646                                         };
 647                                 };
 648
 649                                 adc: adc {
 650                                         compatible = "marvell,berlin2-adc";
 651                                         interrupts = <12>, <14>;
 652                                         interrupt-names = "adc", "tsen";
 653                                 };
 654                         };
 655
 656                         sic: interrupt-controller@e000 {
 657                                 compatible = "snps,dw-apb-ictl";
 658                                 reg = <0xe000 0x30>;
 659                                 interrupt-controller;
 660                                 #interrupt-cells = <1>;
 661                                 interrupt-parent = <&gic>;
 662                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 663                         };
 664                 };
 665         };
 666 };