1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
7 * based on GPL'ed 2.6 kernel sources
8 * (c) Marvell International Ltd.
11 #include <dt-bindings/clock/berlin2.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Marvell Armada 1500 (BG2) SoC";
16 compatible = "marvell,berlin2", "marvell,berlin";
29 enable-method = "marvell,berlin-smp";
32 compatible = "marvell,pj4b";
34 next-level-cache = <&l2>;
37 clocks = <&chip_clk CLKID_CPU>;
38 clock-latency = <100000>;
49 compatible = "marvell,pj4b";
51 next-level-cache = <&l2>;
57 compatible = "fixed-clock";
59 clock-frequency = <25000000>;
63 compatible = "simple-bus";
66 interrupt-parent = <&gic>;
68 ranges = <0 0xf7000000 0x1000000>;
70 sdhci0: sdhci@ab0000 {
71 compatible = "mrvl,pxav3-mmc";
72 reg = <0xab0000 0x200>;
73 clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
74 clock-names = "io", "core";
75 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
79 sdhci1: sdhci@ab0800 {
80 compatible = "mrvl,pxav3-mmc";
81 reg = <0xab0800 0x200>;
82 clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
83 clock-names = "io", "core";
84 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
88 sdhci2: sdhci@ab1000 {
89 compatible = "mrvl,pxav3-mmc";
90 reg = <0xab1000 0x200>;
91 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
93 clock-names = "io", "core";
94 pinctrl-0 = <&emmc_pmux>;
95 pinctrl-names = "default";
99 l2: l2-cache-controller@ac0000 {
100 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
101 reg = <0xac0000 0x1000>;
106 scu: snoop-control-unit@ad0000 {
107 compatible = "arm,cortex-a9-scu";
108 reg = <0xad0000 0x58>;
111 gic: interrupt-controller@ad1000 {
112 compatible = "arm,cortex-a9-gic";
113 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
114 interrupt-controller;
115 #interrupt-cells = <3>;
119 compatible = "arm,cortex-a9-twd-timer";
120 reg = <0xad0600 0x20>;
121 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
122 clocks = <&chip_clk CLKID_TWD>;
125 eth1: ethernet@b90000 {
126 compatible = "marvell,pxa168-eth";
127 reg = <0xb90000 0x10000>;
128 clocks = <&chip_clk CLKID_GETH1>;
129 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
130 /* set by bootloader */
131 local-mac-address = [00 00 00 00 00 00];
132 #address-cells = <1>;
134 phy-connection-type = "mii";
135 phy-handle = <ðphy1>;
138 ethphy1: ethernet-phy@0 {
144 compatible = "marvell,berlin-cpu-ctrl";
145 reg = <0xdd0000 0x10000>;
148 eth0: ethernet@e50000 {
149 compatible = "marvell,pxa168-eth";
150 reg = <0xe50000 0x10000>;
151 clocks = <&chip_clk CLKID_GETH0>;
152 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
153 /* set by bootloader */
154 local-mac-address = [00 00 00 00 00 00];
155 #address-cells = <1>;
157 phy-connection-type = "mii";
158 phy-handle = <ðphy0>;
161 ethphy0: ethernet-phy@0 {
167 compatible = "simple-bus";
168 #address-cells = <1>;
171 ranges = <0 0xe80000 0x10000>;
172 interrupt-parent = <&aic>;
175 compatible = "snps,dw-apb-gpio";
176 reg = <0x0400 0x400>;
177 #address-cells = <1>;
181 compatible = "snps,dw-apb-gpio-port";
186 interrupt-controller;
187 #interrupt-cells = <2>;
193 compatible = "snps,dw-apb-gpio";
194 reg = <0x0800 0x400>;
195 #address-cells = <1>;
199 compatible = "snps,dw-apb-gpio-port";
204 interrupt-controller;
205 #interrupt-cells = <2>;
211 compatible = "snps,dw-apb-gpio";
212 reg = <0x0c00 0x400>;
213 #address-cells = <1>;
217 compatible = "snps,dw-apb-gpio-port";
222 interrupt-controller;
223 #interrupt-cells = <2>;
229 compatible = "snps,dw-apb-gpio";
230 reg = <0x1000 0x400>;
231 #address-cells = <1>;
235 compatible = "snps,dw-apb-gpio-port";
240 interrupt-controller;
241 #interrupt-cells = <2>;
247 compatible = "snps,dw-apb-timer";
250 clocks = <&chip_clk CLKID_CFG>;
251 clock-names = "timer";
256 compatible = "snps,dw-apb-timer";
259 clocks = <&chip_clk CLKID_CFG>;
260 clock-names = "timer";
265 compatible = "snps,dw-apb-timer";
268 clocks = <&chip_clk CLKID_CFG>;
269 clock-names = "timer";
274 compatible = "snps,dw-apb-timer";
277 clocks = <&chip_clk CLKID_CFG>;
278 clock-names = "timer";
283 compatible = "snps,dw-apb-timer";
286 clocks = <&chip_clk CLKID_CFG>;
287 clock-names = "timer";
292 compatible = "snps,dw-apb-timer";
295 clocks = <&chip_clk CLKID_CFG>;
296 clock-names = "timer";
301 compatible = "snps,dw-apb-timer";
304 clocks = <&chip_clk CLKID_CFG>;
305 clock-names = "timer";
310 compatible = "snps,dw-apb-timer";
313 clocks = <&chip_clk CLKID_CFG>;
314 clock-names = "timer";
318 aic: interrupt-controller@3000 {
319 compatible = "snps,dw-apb-ictl";
320 reg = <0x3000 0xc00>;
321 interrupt-controller;
322 #interrupt-cells = <1>;
323 interrupt-parent = <&gic>;
324 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
329 compatible = "marvell,berlin2-ahci", "generic-ahci";
330 reg = <0xe90000 0x1000>;
331 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&chip_clk CLKID_SATA>;
333 #address-cells = <1>;
338 phys = <&sata_phy 0>;
344 phys = <&sata_phy 1>;
349 sata_phy: phy@e900a0 {
350 compatible = "marvell,berlin2-sata-phy";
351 reg = <0xe900a0 0x200>;
352 clocks = <&chip_clk CLKID_SATA>;
353 #address-cells = <1>;
367 chip: chip-control@ea0000 {
368 compatible = "simple-mfd", "syscon";
369 reg = <0xea0000 0x400>;
372 compatible = "marvell,berlin2-clk";
375 clock-names = "refclk";
378 soc_pinctrl: pin-controller {
379 compatible = "marvell,berlin2-soc-pinctrl";
381 emmc_pmux: emmc-pmux {
388 compatible = "marvell,berlin2-reset";
394 compatible = "marvell,berlin-pwm";
395 reg = <0xf20000 0x40>;
396 clocks = <&chip_clk CLKID_CFG>;
401 compatible = "simple-bus";
402 #address-cells = <1>;
405 ranges = <0 0xfc0000 0x10000>;
406 interrupt-parent = <&sic>;
408 wdt0: watchdog@1000 {
409 compatible = "snps,dw-wdt";
410 reg = <0x1000 0x100>;
415 wdt1: watchdog@2000 {
416 compatible = "snps,dw-wdt";
417 reg = <0x2000 0x100>;
422 wdt2: watchdog@3000 {
423 compatible = "snps,dw-wdt";
424 reg = <0x3000 0x100>;
429 sm_gpio1: gpio@5000 {
430 compatible = "snps,dw-apb-gpio";
431 reg = <0x5000 0x400>;
432 #address-cells = <1>;
436 compatible = "snps,dw-apb-gpio-port";
444 sm_gpio0: gpio@c000 {
445 compatible = "snps,dw-apb-gpio";
446 reg = <0xc000 0x400>;
447 #address-cells = <1>;
451 compatible = "snps,dw-apb-gpio-port";
456 interrupt-controller;
457 #interrupt-cells = <2>;
463 compatible = "snps,dw-apb-uart";
464 reg = <0x9000 0x100>;
469 pinctrl-0 = <&uart0_pmux>;
470 pinctrl-names = "default";
475 compatible = "snps,dw-apb-uart";
476 reg = <0xa000 0x100>;
481 pinctrl-0 = <&uart1_pmux>;
482 pinctrl-names = "default";
487 compatible = "snps,dw-apb-uart";
488 reg = <0xb000 0x100>;
493 pinctrl-0 = <&uart2_pmux>;
494 pinctrl-names = "default";
498 sysctrl: system-controller@d000 {
499 compatible = "simple-mfd", "syscon";
500 reg = <0xd000 0x100>;
502 sys_pinctrl: pin-controller {
503 compatible = "marvell,berlin2-system-pinctrl";
504 uart0_pmux: uart0-pmux {
509 uart1_pmux: uart1-pmux {
513 uart2_pmux: uart2-pmux {
520 sic: interrupt-controller@e000 {
521 compatible = "snps,dw-apb-ictl";
522 reg = <0xe000 0x400>;
523 interrupt-controller;
524 #interrupt-cells = <1>;
525 interrupt-parent = <&gic>;
526 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;