arch/arm/boot/dts/berlin2.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
   4  *
   5  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
   6  *
   7  * based on GPL'ed 2.6 kernel sources
   8  *  (c) Marvell International Ltd.
   9  */
  10
  11 #include <dt-bindings/clock/berlin2.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13
  14 / {
  15         model = "Marvell Armada 1500 (BG2) SoC";
  16         compatible = "marvell,berlin2", "marvell,berlin";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 serial0 = &uart0;
  22                 serial1 = &uart1;
  23                 serial2 = &uart2;
  24         };
  25
  26         cpus {
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29                 enable-method = "marvell,berlin-smp";
  30
  31                 cpu@0 {
  32                         compatible = "marvell,pj4b";
  33                         device_type = "cpu";
  34                         next-level-cache = <&l2>;
  35                         reg = <0>;
  36
  37                         clocks = <&chip_clk CLKID_CPU>;
  38                         clock-latency = <100000>;
  39                         operating-points = <
  40                                 /* kHz    uV */
  41                                 1200000 1200000
  42                                 1000000 1200000
  43                                 800000  1200000
  44                                 600000  1200000
  45                         >;
  46                 };
  47
  48                 cpu@1 {
  49                         compatible = "marvell,pj4b";
  50                         device_type = "cpu";
  51                         next-level-cache = <&l2>;
  52                         reg = <1>;
  53
  54                         clocks = <&chip_clk CLKID_CPU>;
  55                         clock-latency = <100000>;
  56                         operating-points = <
  57                                 /* kHz    uV */
  58                                 1200000 1200000
  59                                 1000000 1200000
  60                                 800000  1200000
  61                                 600000  1200000
  62                         >;
  63                 };
  64         };
  65
  66         refclk: oscillator {
  67                 compatible = "fixed-clock";
  68                 #clock-cells = <0>;
  69                 clock-frequency = <25000000>;
  70         };
  71
  72         soc@f7000000 {
  73                 compatible = "simple-bus";
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 interrupt-parent = <&gic>;
  77
  78                 ranges = <0 0xf7000000 0x1000000>;
  79
  80                 sdhci0: sdhci@ab0000 {
  81                         compatible = "mrvl,pxav3-mmc";
  82                         reg = <0xab0000 0x200>;
  83                         clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
  84                         clock-names = "io", "core";
  85                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
  86                         status = "disabled";
  87                 };
  88
  89                 sdhci1: sdhci@ab0800 {
  90                         compatible = "mrvl,pxav3-mmc";
  91                         reg = <0xab0800 0x200>;
  92                         clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
  93                         clock-names = "io", "core";
  94                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  95                         status = "disabled";
  96                 };
  97
  98                 sdhci2: sdhci@ab1000 {
  99                         compatible = "mrvl,pxav3-mmc";
 100                         reg = <0xab1000 0x200>;
 101                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 102                         clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
 103                         clock-names = "io", "core";
 104                         pinctrl-0 = <&emmc_pmux>;
 105                         pinctrl-names = "default";
 106                         status = "disabled";
 107                 };
 108
 109                 l2: l2-cache-controller@ac0000 {
 110                         compatible = "marvell,tauros3-cache", "arm,pl310-cache";
 111                         reg = <0xac0000 0x1000>;
 112                         cache-unified;
 113                         cache-level = <2>;
 114                 };
 115
 116                 scu: snoop-control-unit@ad0000 {
 117                         compatible = "arm,cortex-a9-scu";
 118                         reg = <0xad0000 0x58>;
 119                 };
 120
 121                 gic: interrupt-controller@ad1000 {
 122                         compatible = "arm,cortex-a9-gic";
 123                         reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
 124                         interrupt-controller;
 125                         #interrupt-cells = <3>;
 126                 };
 127
 128                 local-timer@ad0600 {
 129                         compatible = "arm,cortex-a9-twd-timer";
 130                         reg = <0xad0600 0x20>;
 131                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 132                         clocks = <&chip_clk CLKID_TWD>;
 133                 };
 134
 135                 eth1: ethernet@b90000 {
 136                         compatible = "marvell,pxa168-eth";
 137                         reg = <0xb90000 0x10000>;
 138                         clocks = <&chip_clk CLKID_GETH1>;
 139                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 140                         /* set by bootloader */
 141                         local-mac-address = [00 00 00 00 00 00];
 142                         #address-cells = <1>;
 143                         #size-cells = <0>;
 144                         phy-connection-type = "mii";
 145                         phy-handle = <&ethphy1>;
 146                         status = "disabled";
 147
 148                         ethphy1: ethernet-phy@0 {
 149                                 reg = <0>;
 150                         };
 151                 };
 152
 153                 cpu-ctrl@dd0000 {
 154                         compatible = "marvell,berlin-cpu-ctrl";
 155                         reg = <0xdd0000 0x10000>;
 156                 };
 157
 158                 eth0: ethernet@e50000 {
 159                         compatible = "marvell,pxa168-eth";
 160                         reg = <0xe50000 0x10000>;
 161                         clocks = <&chip_clk CLKID_GETH0>;
 162                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 163                         /* set by bootloader */
 164                         local-mac-address = [00 00 00 00 00 00];
 165                         #address-cells = <1>;
 166                         #size-cells = <0>;
 167                         phy-connection-type = "mii";
 168                         phy-handle = <&ethphy0>;
 169                         status = "disabled";
 170
 171                         ethphy0: ethernet-phy@0 {
 172                                 reg = <0>;
 173                         };
 174                 };
 175
 176                 apb@e80000 {
 177                         compatible = "simple-bus";
 178                         #address-cells = <1>;
 179                         #size-cells = <1>;
 180
 181                         ranges = <0 0xe80000 0x10000>;
 182                         interrupt-parent = <&aic>;
 183
 184                         gpio0: gpio@400 {
 185                                 compatible = "snps,dw-apb-gpio";
 186                                 reg = <0x0400 0x400>;
 187                                 #address-cells = <1>;
 188                                 #size-cells = <0>;
 189
 190                                 porta: gpio-port@0 {
 191                                         compatible = "snps,dw-apb-gpio-port";
 192                                         gpio-controller;
 193                                         #gpio-cells = <2>;
 194                                         snps,nr-gpios = <8>;
 195                                         reg = <0>;
 196                                         interrupt-controller;
 197                                         #interrupt-cells = <2>;
 198                                         interrupts = <0>;
 199                                 };
 200                         };
 201
 202                         gpio1: gpio@800 {
 203                                 compatible = "snps,dw-apb-gpio";
 204                                 reg = <0x0800 0x400>;
 205                                 #address-cells = <1>;
 206                                 #size-cells = <0>;
 207
 208                                 portb: gpio-port@1 {
 209                                         compatible = "snps,dw-apb-gpio-port";
 210                                         gpio-controller;
 211                                         #gpio-cells = <2>;
 212                                         snps,nr-gpios = <8>;
 213                                         reg = <0>;
 214                                         interrupt-controller;
 215                                         #interrupt-cells = <2>;
 216                                         interrupts = <1>;
 217                                 };
 218                         };
 219
 220                         gpio2: gpio@c00 {
 221                                 compatible = "snps,dw-apb-gpio";
 222                                 reg = <0x0c00 0x400>;
 223                                 #address-cells = <1>;
 224                                 #size-cells = <0>;
 225
 226                                 portc: gpio-port@2 {
 227                                         compatible = "snps,dw-apb-gpio-port";
 228                                         gpio-controller;
 229                                         #gpio-cells = <2>;
 230                                         snps,nr-gpios = <8>;
 231                                         reg = <0>;
 232                                         interrupt-controller;
 233                                         #interrupt-cells = <2>;
 234                                         interrupts = <2>;
 235                                 };
 236                         };
 237
 238                         gpio3: gpio@1000 {
 239                                 compatible = "snps,dw-apb-gpio";
 240                                 reg = <0x1000 0x400>;
 241                                 #address-cells = <1>;
 242                                 #size-cells = <0>;
 243
 244                                 portd: gpio-port@3 {
 245                                         compatible = "snps,dw-apb-gpio-port";
 246                                         gpio-controller;
 247                                         #gpio-cells = <2>;
 248                                         snps,nr-gpios = <8>;
 249                                         reg = <0>;
 250                                         interrupt-controller;
 251                                         #interrupt-cells = <2>;
 252                                         interrupts = <3>;
 253                                 };
 254                         };
 255
 256                         timer0: timer@2c00 {
 257                                 compatible = "snps,dw-apb-timer";
 258                                 reg = <0x2c00 0x14>;
 259                                 interrupts = <8>;
 260                                 clocks = <&chip_clk CLKID_CFG>;
 261                                 clock-names = "timer";
 262                                 status = "okay";
 263                         };
 264
 265                         timer1: timer@2c14 {
 266                                 compatible = "snps,dw-apb-timer";
 267                                 reg = <0x2c14 0x14>;
 268                                 interrupts = <9>;
 269                                 clocks = <&chip_clk CLKID_CFG>;
 270                                 clock-names = "timer";
 271                                 status = "okay";
 272                         };
 273
 274                         timer2: timer@2c28 {
 275                                 compatible = "snps,dw-apb-timer";
 276                                 reg = <0x2c28 0x14>;
 277                                 interrupts = <10>;
 278                                 clocks = <&chip_clk CLKID_CFG>;
 279                                 clock-names = "timer";
 280                                 status = "disabled";
 281                         };
 282
 283                         timer3: timer@2c3c {
 284                                 compatible = "snps,dw-apb-timer";
 285                                 reg = <0x2c3c 0x14>;
 286                                 interrupts = <11>;
 287                                 clocks = <&chip_clk CLKID_CFG>;
 288                                 clock-names = "timer";
 289                                 status = "disabled";
 290                         };
 291
 292                         timer4: timer@2c50 {
 293                                 compatible = "snps,dw-apb-timer";
 294                                 reg = <0x2c50 0x14>;
 295                                 interrupts = <12>;
 296                                 clocks = <&chip_clk CLKID_CFG>;
 297                                 clock-names = "timer";
 298                                 status = "disabled";
 299                         };
 300
 301                         timer5: timer@2c64 {
 302                                 compatible = "snps,dw-apb-timer";
 303                                 reg = <0x2c64 0x14>;
 304                                 interrupts = <13>;
 305                                 clocks = <&chip_clk CLKID_CFG>;
 306                                 clock-names = "timer";
 307                                 status = "disabled";
 308                         };
 309
 310                         timer6: timer@2c78 {
 311                                 compatible = "snps,dw-apb-timer";
 312                                 reg = <0x2c78 0x14>;
 313                                 interrupts = <14>;
 314                                 clocks = <&chip_clk CLKID_CFG>;
 315                                 clock-names = "timer";
 316                                 status = "disabled";
 317                         };
 318
 319                         timer7: timer@2c8c {
 320                                 compatible = "snps,dw-apb-timer";
 321                                 reg = <0x2c8c 0x14>;
 322                                 interrupts = <15>;
 323                                 clocks = <&chip_clk CLKID_CFG>;
 324                                 clock-names = "timer";
 325                                 status = "disabled";
 326                         };
 327
 328                         aic: interrupt-controller@3000 {
 329                                 compatible = "snps,dw-apb-ictl";
 330                                 reg = <0x3000 0xc00>;
 331                                 interrupt-controller;
 332                                 #interrupt-cells = <1>;
 333                                 interrupt-parent = <&gic>;
 334                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 335                         };
 336                 };
 337
 338                 ahci: sata@e90000 {
 339                         compatible = "marvell,berlin2-ahci", "generic-ahci";
 340                         reg = <0xe90000 0x1000>;
 341                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 342                         clocks = <&chip_clk CLKID_SATA>;
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345
 346                         sata0: sata-port@0 {
 347                                 reg = <0>;
 348                                 phys = <&sata_phy 0>;
 349                                 status = "disabled";
 350                         };
 351
 352                         sata1: sata-port@1 {
 353                                 reg = <1>;
 354                                 phys = <&sata_phy 1>;
 355                                 status = "disabled";
 356                         };
 357                 };
 358
 359                 sata_phy: phy@e900a0 {
 360                         compatible = "marvell,berlin2-sata-phy";
 361                         reg = <0xe900a0 0x200>;
 362                         clocks = <&chip_clk CLKID_SATA>;
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         #phy-cells = <1>;
 366                         status = "disabled";
 367
 368                         sata-phy@0 {
 369                                 reg = <0>;
 370                         };
 371
 372                         sata-phy@1 {
 373                                 reg = <1>;
 374                         };
 375                 };
 376
 377                 chip: chip-control@ea0000 {
 378                         compatible = "simple-mfd", "syscon";
 379                         reg = <0xea0000 0x400>;
 380
 381                         chip_clk: clock {
 382                                 compatible = "marvell,berlin2-clk";
 383                                 #clock-cells = <1>;
 384                                 clocks = <&refclk>;
 385                                 clock-names = "refclk";
 386                         };
 387
 388                         soc_pinctrl: pin-controller {
 389                                 compatible = "marvell,berlin2-soc-pinctrl";
 390
 391                                 emmc_pmux: emmc-pmux {
 392                                         groups = "G26";
 393                                         function = "emmc";
 394                                 };
 395                         };
 396
 397                         chip_rst: reset {
 398                                 compatible = "marvell,berlin2-reset";
 399                                 #reset-cells = <2>;
 400                         };
 401                 };
 402
 403                 pwm: pwm@f20000 {
 404                         compatible = "marvell,berlin-pwm";
 405                         reg = <0xf20000 0x40>;
 406                         clocks = <&chip_clk CLKID_CFG>;
 407                         #pwm-cells = <3>;
 408                 };
 409
 410                 apb@fc0000 {
 411                         compatible = "simple-bus";
 412                         #address-cells = <1>;
 413                         #size-cells = <1>;
 414
 415                         ranges = <0 0xfc0000 0x10000>;
 416                         interrupt-parent = <&sic>;
 417
 418                         wdt0: watchdog@1000 {
 419                                 compatible = "snps,dw-wdt";
 420                                 reg = <0x1000 0x100>;
 421                                 clocks = <&refclk>;
 422                                 interrupts = <0>;
 423                         };
 424
 425                         wdt1: watchdog@2000 {
 426                                 compatible = "snps,dw-wdt";
 427                                 reg = <0x2000 0x100>;
 428                                 clocks = <&refclk>;
 429                                 interrupts = <1>;
 430                         };
 431
 432                         wdt2: watchdog@3000 {
 433                                 compatible = "snps,dw-wdt";
 434                                 reg = <0x3000 0x100>;
 435                                 clocks = <&refclk>;
 436                                 interrupts = <2>;
 437                         };
 438
 439                         sm_gpio1: gpio@5000 {
 440                                 compatible = "snps,dw-apb-gpio";
 441                                 reg = <0x5000 0x400>;
 442                                 #address-cells = <1>;
 443                                 #size-cells = <0>;
 444
 445                                 portf: gpio-port@5 {
 446                                         compatible = "snps,dw-apb-gpio-port";
 447                                         gpio-controller;
 448                                         #gpio-cells = <2>;
 449                                         snps,nr-gpios = <8>;
 450                                         reg = <0>;
 451                                 };
 452                         };
 453
 454                         sm_gpio0: gpio@c000 {
 455                                 compatible = "snps,dw-apb-gpio";
 456                                 reg = <0xc000 0x400>;
 457                                 #address-cells = <1>;
 458                                 #size-cells = <0>;
 459
 460                                 porte: gpio-port@4 {
 461                                         compatible = "snps,dw-apb-gpio-port";
 462                                         gpio-controller;
 463                                         #gpio-cells = <2>;
 464                                         snps,nr-gpios = <8>;
 465                                         reg = <0>;
 466                                         interrupt-controller;
 467                                         #interrupt-cells = <2>;
 468                                         interrupts = <11>;
 469                                 };
 470                         };
 471
 472                         uart0: serial@9000 {
 473                                 compatible = "snps,dw-apb-uart";
 474                                 reg = <0x9000 0x100>;
 475                                 reg-shift = <2>;
 476                                 reg-io-width = <1>;
 477                                 interrupts = <8>;
 478                                 clocks = <&refclk>;
 479                                 pinctrl-0 = <&uart0_pmux>;
 480                                 pinctrl-names = "default";
 481                                 status = "disabled";
 482                         };
 483
 484                         uart1: serial@a000 {
 485                                 compatible = "snps,dw-apb-uart";
 486                                 reg = <0xa000 0x100>;
 487                                 reg-shift = <2>;
 488                                 reg-io-width = <1>;
 489                                 interrupts = <9>;
 490                                 clocks = <&refclk>;
 491                                 pinctrl-0 = <&uart1_pmux>;
 492                                 pinctrl-names = "default";
 493                                 status = "disabled";
 494                         };
 495
 496                         uart2: serial@b000 {
 497                                 compatible = "snps,dw-apb-uart";
 498                                 reg = <0xb000 0x100>;
 499                                 reg-shift = <2>;
 500                                 reg-io-width = <1>;
 501                                 interrupts = <10>;
 502                                 clocks = <&refclk>;
 503                                 pinctrl-0 = <&uart2_pmux>;
 504                                 pinctrl-names = "default";
 505                                 status = "disabled";
 506                         };
 507
 508                         sysctrl: system-controller@d000 {
 509                                 compatible = "simple-mfd", "syscon";
 510                                 reg = <0xd000 0x100>;
 511
 512                                 sys_pinctrl: pin-controller {
 513                                         compatible = "marvell,berlin2-system-pinctrl";
 514                                         uart0_pmux: uart0-pmux {
 515                                                 groups = "GSM4";
 516                                                 function = "uart0";
 517                                         };
 518
 519                                         uart1_pmux: uart1-pmux {
 520                                                 groups = "GSM5";
 521                                                 function = "uart1";
 522                                         };
 523                                         uart2_pmux: uart2-pmux {
 524                                                 groups = "GSM3";
 525                                                 function = "uart2";
 526                                         };
 527                                 };
 528                         };
 529
 530                         sic: interrupt-controller@e000 {
 531                                 compatible = "snps,dw-apb-ictl";
 532                                 reg = <0xe000 0x400>;
 533                                 interrupt-controller;
 534                                 #interrupt-cells = <1>;
 535                                 interrupt-parent = <&gic>;
 536                                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 537                         };
 538                 };
 539         };
 540 };