arch/arm/boot/dts/bcm63138.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Broadcom BCM63138 DSL SoCs Device Tree
   4  */
   5
   6 #include <dt-bindings/interrupt-controller/arm-gic.h>
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8
   9 #include "skeleton.dtsi"
  10
  11 / {
  12         compatible = "brcm,bcm63138";
  13         model = "Broadcom BCM63138 DSL SoC";
  14         interrupt-parent = <&gic>;
  15
  16         aliases {
  17                 uart0 = &serial0;
  18                 uart1 = &serial1;
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         next-level-cache = <&L2>;
  29                         reg = <0>;
  30                         enable-method = "brcm,bcm63138";
  31                 };
  32
  33                 cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a9";
  36                         next-level-cache = <&L2>;
  37                         reg = <1>;
  38                         enable-method = "brcm,bcm63138";
  39                         resets = <&pmb0 4 1>;
  40                 };
  41         };
  42
  43         clocks {
  44                 #address-cells = <1>;
  45                 #size-cells = <0>;
  46
  47                 /* UBUS peripheral clock */
  48                 periph_clk: periph_clk {
  49                         #clock-cells = <0>;
  50                         compatible = "fixed-clock";
  51                         clock-frequency = <50000000>;
  52                         clock-output-names = "periph";
  53                 };
  54
  55                 /* peripheral clock for system timer */
  56                 axi_clk: axi_clk {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-factor-clock";
  59                         clocks = <&armpll>;
  60                         clock-div = <2>;
  61                         clock-mult = <1>;
  62                 };
  63
  64                 /* APB bus clock */
  65                 apb_clk: apb_clk {
  66                         #clock-cells = <0>;
  67                         compatible = "fixed-factor-clock";
  68                         clocks = <&armpll>;
  69                         clock-div = <4>;
  70                         clock-mult = <1>;
  71                 };
  72         };
  73
  74         /* ARM bus */
  75         axi@80000000 {
  76                 compatible = "simple-bus";
  77                 ranges = <0 0x80000000 0x784000>;
  78                 #address-cells = <1>;
  79                 #size-cells = <1>;
  80
  81                 L2: cache-controller@1d000 {
  82                         compatible = "arm,pl310-cache";
  83                         reg = <0x1d000 0x1000>;
  84                         cache-unified;
  85                         cache-level = <2>;
  86                         cache-size = <524288>;
  87                         cache-sets = <1024>;
  88                         cache-line-size = <32>;
  89                         interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
  90                 };
  91
  92                 scu: scu@1e000 {
  93                         compatible = "arm,cortex-a9-scu";
  94                         reg = <0x1e000 0x100>;
  95                 };
  96
  97                 gic: interrupt-controller@1e100 {
  98                         compatible = "arm,cortex-a9-gic";
  99                         reg = <0x1f000 0x1000
 100                                 0x1e100 0x100>;
 101                         #interrupt-cells = <3>;
 102                         #address-cells = <0>;
 103                         interrupt-controller;
 104                 };
 105
 106                 global_timer: timer@1e200 {
 107                         compatible = "arm,cortex-a9-global-timer";
 108                         reg = <0x1e200 0x20>;
 109                         interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
 110                         clocks = <&axi_clk>;
 111                 };
 112
 113                 local_timer: local-timer@1e600 {
 114                         compatible = "arm,cortex-a9-twd-timer";
 115                         reg = <0x1e600 0x20>;
 116                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 117                                                   IRQ_TYPE_EDGE_RISING)>;
 118                         clocks = <&axi_clk>;
 119                 };
 120
 121                 twd_watchdog: watchdog@1e620 {
 122                         compatible = "arm,cortex-a9-twd-wdt";
 123                         reg = <0x1e620 0x20>;
 124                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 125                                                   IRQ_TYPE_LEVEL_HIGH)>;
 126                 };
 127
 128                 armpll: armpll {
 129                         #clock-cells = <0>;
 130                         compatible = "brcm,bcm63138-armpll";
 131                         clocks = <&periph_clk>;
 132                         reg = <0x20000 0xf00>;
 133                 };
 134
 135                 pmb0: reset-controller@4800c0 {
 136                         compatible = "brcm,bcm63138-pmb";
 137                         reg = <0x4800c0 0x10>;
 138                         #reset-cells = <2>;
 139                 };
 140
 141                 pmb1: reset-controller@4800e0 {
 142                         compatible = "brcm,bcm63138-pmb";
 143                         reg = <0x4800e0 0x10>;
 144                         #reset-cells = <2>;
 145                 };
 146         };
 147
 148         /* Legacy UBUS base */
 149         ubus@fffe8000 {
 150                 compatible = "simple-bus";
 151                 #address-cells = <1>;
 152                 #size-cells = <1>;
 153                 ranges = <0 0xfffe8000 0x8100>;
 154
 155                 timer: timer@80 {
 156                         compatible = "brcm,bcm6328-timer", "syscon";
 157                         reg = <0x80 0x3c>;
 158                 };
 159
 160                 serial0: serial@600 {
 161                         compatible = "brcm,bcm6345-uart";
 162                         reg = <0x600 0x1b>;
 163                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 164                         clocks = <&periph_clk>;
 165                         clock-names = "periph";
 166                         status = "disabled";
 167                 };
 168
 169                 serial1: serial@620 {
 170                         compatible = "brcm,bcm6345-uart";
 171                         reg = <0x620 0x1b>;
 172                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 173                         clocks = <&periph_clk>;
 174                         clock-names = "periph";
 175                         status = "disabled";
 176                 };
 177
 178                 nand: nand@2000 {
 179                         #address-cells = <1>;
 180                         #size-cells = <0>;
 181                         compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.0", "brcm,brcmnand";
 182                         reg = <0x2000 0x600>, <0xf0 0x10>;
 183                         reg-names = "nand", "nand-int-base";
 184                         status = "disabled";
 185                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 186                         interrupt-names = "nand";
 187                 };
 188
 189                 bootlut: bootlut@8000 {
 190                         compatible = "brcm,bcm63138-bootlut";
 191                         reg = <0x8000 0x50>;
 192                 };
 193
 194                 reboot {
 195                         compatible = "syscon-reboot";
 196                         regmap = <&timer>;
 197                         offset = <0x34>;
 198                         mask = <1>;
 199                 };
 200         };
 201 };