arch/arm/boot/dts/bcm283x.dtsi

   1 #include <dt-bindings/pinctrl/bcm2835.h>
   2 #include <dt-bindings/clock/bcm2835.h>
   3 #include <dt-bindings/clock/bcm2835-aux.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/interrupt-controller/irq.h>
   6
   7 /* firmware-provided startup stubs live here, where the secondary CPUs are
   8  * spinning.
   9  */
  10 /memreserve/ 0x00000000 0x00001000;
  11
  12 /* This include file covers the common peripherals and configuration between
  13  * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
  14  * bcm2835.dtsi and bcm2836.dtsi.
  15  */
  16
  17 / {
  18         compatible = "brcm,bcm2835";
  19         model = "BCM2835";
  20         interrupt-parent = <&intc>;
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         aliases {
  25                 serial0 = &uart0;
  26                 serial1 = &uart1;
  27         };
  28
  29         chosen {
  30                 stdout-path = "serial0:115200n8";
  31         };
  32
  33         thermal-zones {
  34                 cpu_thermal: cpu-thermal {
  35                         polling-delay-passive = <0>;
  36                         polling-delay = <1000>;
  37
  38                         thermal-sensors = <&thermal>;
  39
  40                         trips {
  41                                 cpu-crit {
  42                                         temperature     = <80000>;
  43                                         hysteresis      = <0>;
  44                                         type            = "critical";
  45                                 };
  46                         };
  47
  48                         cooling-maps {
  49                         };
  50                 };
  51         };
  52
  53         soc {
  54                 compatible = "simple-bus";
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57
  58                 timer@7e003000 {
  59                         compatible = "brcm,bcm2835-system-timer";
  60                         reg = <0x7e003000 0x1000>;
  61                         interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
  62                         /* This could be a reference to BCM2835_CLOCK_TIMER,
  63                          * but we don't have the driver using the common clock
  64                          * support yet.
  65                          */
  66                         clock-frequency = <1000000>;
  67                 };
  68
  69                 dma: dma@7e007000 {
  70                         compatible = "brcm,bcm2835-dma";
  71                         reg = <0x7e007000 0xf00>;
  72                         interrupts = <1 16>,
  73                                      <1 17>,
  74                                      <1 18>,
  75                                      <1 19>,
  76                                      <1 20>,
  77                                      <1 21>,
  78                                      <1 22>,
  79                                      <1 23>,
  80                                      <1 24>,
  81                                      <1 25>,
  82                                      <1 26>,
  83                                      /* dma channel 11-14 share one irq */
  84                                      <1 27>,
  85                                      <1 27>,
  86                                      <1 27>,
  87                                      <1 27>,
  88                                      /* unused shared irq for all channels */
  89                                      <1 28>;
  90                         interrupt-names = "dma0",
  91                                           "dma1",
  92                                           "dma2",
  93                                           "dma3",
  94                                           "dma4",
  95                                           "dma5",
  96                                           "dma6",
  97                                           "dma7",
  98                                           "dma8",
  99                                           "dma9",
 100                                           "dma10",
 101                                           "dma11",
 102                                           "dma12",
 103                                           "dma13",
 104                                           "dma14",
 105                                           "dma-shared-all";
 106                         #dma-cells = <1>;
 107                         brcm,dma-channel-mask = <0x7f35>;
 108                 };
 109
 110                 intc: interrupt-controller@7e00b200 {
 111                         compatible = "brcm,bcm2835-armctrl-ic";
 112                         reg = <0x7e00b200 0x200>;
 113                         interrupt-controller;
 114                         #interrupt-cells = <2>;
 115                 };
 116
 117                 watchdog@7e100000 {
 118                         compatible = "brcm,bcm2835-pm-wdt";
 119                         reg = <0x7e100000 0x28>;
 120                 };
 121
 122                 clocks: cprman@7e101000 {
 123                         compatible = "brcm,bcm2835-cprman";
 124                         #clock-cells = <1>;
 125                         reg = <0x7e101000 0x2000>;
 126
 127                         /* CPRMAN derives almost everything from the
 128                          * platform's oscillator.  However, the DSI
 129                          * pixel clocks come from the DSI analog PHY.
 130                          */
 131                         clocks = <&clk_osc>,
 132                                 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
 133                                 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
 134                 };
 135
 136                 rng@7e104000 {
 137                         compatible = "brcm,bcm2835-rng";
 138                         reg = <0x7e104000 0x10>;
 139                         interrupts = <2 29>;
 140                 };
 141
 142                 mailbox: mailbox@7e00b880 {
 143                         compatible = "brcm,bcm2835-mbox";
 144                         reg = <0x7e00b880 0x40>;
 145                         interrupts = <0 1>;
 146                         #mbox-cells = <0>;
 147                 };
 148
 149                 gpio: gpio@7e200000 {
 150                         compatible = "brcm,bcm2835-gpio";
 151                         reg = <0x7e200000 0xb4>;
 152                         /*
 153                          * The GPIO IP block is designed for 3 banks of GPIOs.
 154                          * Each bank has a GPIO interrupt for itself.
 155                          * There is an overall "any bank" interrupt.
 156                          * In order, these are GIC interrupts 17, 18, 19, 20.
 157                          * Since the BCM2835 only has 2 banks, the 2nd bank
 158                          * interrupt output appears to be mirrored onto the
 159                          * 3rd bank's interrupt signal.
 160                          * So, a bank0 interrupt shows up on 17, 20, and
 161                          * a bank1 interrupt shows up on 18, 19, 20!
 162                          */
 163                         interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
 164
 165                         gpio-controller;
 166                         #gpio-cells = <2>;
 167
 168                         interrupt-controller;
 169                         #interrupt-cells = <2>;
 170
 171                         /* Defines pin muxing groups according to
 172                          * BCM2835-ARM-Peripherals.pdf page 102.
 173                          *
 174                          * While each pin can have its mux selected
 175                          * for various functions individually, some
 176                          * groups only make sense to switch to a
 177                          * particular function together.
 178                          */
 179                         dpi_gpio0: dpi_gpio0 {
 180                                 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
 181                                              12 13 14 15 16 17 18 19
 182                                              20 21 22 23 24 25 26 27>;
 183                                 brcm,function = <BCM2835_FSEL_ALT2>;
 184                         };
 185                         emmc_gpio22: emmc_gpio22 {
 186                                 brcm,pins = <22 23 24 25 26 27>;
 187                                 brcm,function = <BCM2835_FSEL_ALT3>;
 188                         };
 189                         emmc_gpio34: emmc_gpio34 {
 190                                 brcm,pins = <34 35 36 37 38 39>;
 191                                 brcm,function = <BCM2835_FSEL_ALT3>;
 192                                 brcm,pull = <BCM2835_PUD_OFF
 193                                              BCM2835_PUD_UP
 194                                              BCM2835_PUD_UP
 195                                              BCM2835_PUD_UP
 196                                              BCM2835_PUD_UP
 197                                              BCM2835_PUD_UP>;
 198                         };
 199                         emmc_gpio48: emmc_gpio48 {
 200                                 brcm,pins = <48 49 50 51 52 53>;
 201                                 brcm,function = <BCM2835_FSEL_ALT3>;
 202                         };
 203
 204                         gpclk0_gpio4: gpclk0_gpio4 {
 205                                 brcm,pins = <4>;
 206                                 brcm,function = <BCM2835_FSEL_ALT0>;
 207                         };
 208                         gpclk1_gpio5: gpclk1_gpio5 {
 209                                 brcm,pins = <5>;
 210                                 brcm,function = <BCM2835_FSEL_ALT0>;
 211                         };
 212                         gpclk1_gpio42: gpclk1_gpio42 {
 213                                 brcm,pins = <42>;
 214                                 brcm,function = <BCM2835_FSEL_ALT0>;
 215                         };
 216                         gpclk1_gpio44: gpclk1_gpio44 {
 217                                 brcm,pins = <44>;
 218                                 brcm,function = <BCM2835_FSEL_ALT0>;
 219                         };
 220                         gpclk2_gpio6: gpclk2_gpio6 {
 221                                 brcm,pins = <6>;
 222                                 brcm,function = <BCM2835_FSEL_ALT0>;
 223                         };
 224                         gpclk2_gpio43: gpclk2_gpio43 {
 225                                 brcm,pins = <43>;
 226                                 brcm,function = <BCM2835_FSEL_ALT0>;
 227                                 brcm,pull = <BCM2835_PUD_OFF>;
 228                         };
 229
 230                         i2c0_gpio0: i2c0_gpio0 {
 231                                 brcm,pins = <0 1>;
 232                                 brcm,function = <BCM2835_FSEL_ALT0>;
 233                         };
 234                         i2c0_gpio28: i2c0_gpio28 {
 235                                 brcm,pins = <28 29>;
 236                                 brcm,function = <BCM2835_FSEL_ALT0>;
 237                         };
 238                         i2c0_gpio44: i2c0_gpio44 {
 239                                 brcm,pins = <44 45>;
 240                                 brcm,function = <BCM2835_FSEL_ALT1>;
 241                         };
 242                         i2c1_gpio2: i2c1_gpio2 {
 243                                 brcm,pins = <2 3>;
 244                                 brcm,function = <BCM2835_FSEL_ALT0>;
 245                         };
 246                         i2c1_gpio44: i2c1_gpio44 {
 247                                 brcm,pins = <44 45>;
 248                                 brcm,function = <BCM2835_FSEL_ALT2>;
 249                         };
 250                         i2c_slave_gpio18: i2c_slave_gpio18 {
 251                                 brcm,pins = <18 19 20 21>;
 252                                 brcm,function = <BCM2835_FSEL_ALT3>;
 253                         };
 254
 255                         jtag_gpio4: jtag_gpio4 {
 256                                 brcm,pins = <4 5 6 12 13>;
 257                                 brcm,function = <BCM2835_FSEL_ALT5>;
 258                         };
 259                         jtag_gpio22: jtag_gpio22 {
 260                                 brcm,pins = <22 23 24 25 26 27>;
 261                                 brcm,function = <BCM2835_FSEL_ALT4>;
 262                         };
 263
 264                         pcm_gpio18: pcm_gpio18 {
 265                                 brcm,pins = <18 19 20 21>;
 266                                 brcm,function = <BCM2835_FSEL_ALT0>;
 267                         };
 268                         pcm_gpio28: pcm_gpio28 {
 269                                 brcm,pins = <28 29 30 31>;
 270                                 brcm,function = <BCM2835_FSEL_ALT2>;
 271                         };
 272
 273                         pwm0_gpio12: pwm0_gpio12 {
 274                                 brcm,pins = <12>;
 275                                 brcm,function = <BCM2835_FSEL_ALT0>;
 276                         };
 277                         pwm0_gpio18: pwm0_gpio18 {
 278                                 brcm,pins = <18>;
 279                                 brcm,function = <BCM2835_FSEL_ALT5>;
 280                         };
 281                         pwm0_gpio40: pwm0_gpio40 {
 282                                 brcm,pins = <40>;
 283                                 brcm,function = <BCM2835_FSEL_ALT0>;
 284                         };
 285                         pwm1_gpio13: pwm1_gpio13 {
 286                                 brcm,pins = <13>;
 287                                 brcm,function = <BCM2835_FSEL_ALT0>;
 288                         };
 289                         pwm1_gpio19: pwm1_gpio19 {
 290                                 brcm,pins = <19>;
 291                                 brcm,function = <BCM2835_FSEL_ALT5>;
 292                         };
 293                         pwm1_gpio41: pwm1_gpio41 {
 294                                 brcm,pins = <41>;
 295                                 brcm,function = <BCM2835_FSEL_ALT0>;
 296                         };
 297                         pwm1_gpio45: pwm1_gpio45 {
 298                                 brcm,pins = <45>;
 299                                 brcm,function = <BCM2835_FSEL_ALT0>;
 300                         };
 301
 302                         sdhost_gpio48: sdhost_gpio48 {
 303                                 brcm,pins = <48 49 50 51 52 53>;
 304                                 brcm,function = <BCM2835_FSEL_ALT0>;
 305                         };
 306
 307                         spi0_gpio7: spi0_gpio7 {
 308                                 brcm,pins = <7 8 9 10 11>;
 309                                 brcm,function = <BCM2835_FSEL_ALT0>;
 310                         };
 311                         spi0_gpio35: spi0_gpio35 {
 312                                 brcm,pins = <35 36 37 38 39>;
 313                                 brcm,function = <BCM2835_FSEL_ALT0>;
 314                         };
 315                         spi1_gpio16: spi1_gpio16 {
 316                                 brcm,pins = <16 17 18 19 20 21>;
 317                                 brcm,function = <BCM2835_FSEL_ALT4>;
 318                         };
 319                         spi2_gpio40: spi2_gpio40 {
 320                                 brcm,pins = <40 41 42 43 44 45>;
 321                                 brcm,function = <BCM2835_FSEL_ALT4>;
 322                         };
 323
 324                         uart0_gpio14: uart0_gpio14 {
 325                                 brcm,pins = <14 15>;
 326                                 brcm,function = <BCM2835_FSEL_ALT0>;
 327                         };
 328                         /* Separate from the uart0_gpio14 group
 329                          * because it conflicts with spi1_gpio16, and
 330                          * people often run uart0 on the two pins
 331                          * without flow control.
 332                          */
 333                         uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
 334                                 brcm,pins = <16 17>;
 335                                 brcm,function = <BCM2835_FSEL_ALT3>;
 336                         };
 337                         uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
 338                                 brcm,pins = <30 31>;
 339                                 brcm,function = <BCM2835_FSEL_ALT3>;
 340                                 brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
 341                         };
 342                         uart0_gpio32: uart0_gpio32 {
 343                                 brcm,pins = <32 33>;
 344                                 brcm,function = <BCM2835_FSEL_ALT3>;
 345                                 brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
 346                         };
 347                         uart0_gpio36: uart0_gpio36 {
 348                                 brcm,pins = <36 37>;
 349                                 brcm,function = <BCM2835_FSEL_ALT2>;
 350                         };
 351                         uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
 352                                 brcm,pins = <38 39>;
 353                                 brcm,function = <BCM2835_FSEL_ALT2>;
 354                         };
 355
 356                         uart1_gpio14: uart1_gpio14 {
 357                                 brcm,pins = <14 15>;
 358                                 brcm,function = <BCM2835_FSEL_ALT5>;
 359                         };
 360                         uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
 361                                 brcm,pins = <16 17>;
 362                                 brcm,function = <BCM2835_FSEL_ALT5>;
 363                         };
 364                         uart1_gpio32: uart1_gpio32 {
 365                                 brcm,pins = <32 33>;
 366                                 brcm,function = <BCM2835_FSEL_ALT5>;
 367                         };
 368                         uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
 369                                 brcm,pins = <30 31>;
 370                                 brcm,function = <BCM2835_FSEL_ALT5>;
 371                         };
 372                         uart1_gpio40: uart1_gpio40 {
 373                                 brcm,pins = <40 41>;
 374                                 brcm,function = <BCM2835_FSEL_ALT5>;
 375                         };
 376                         uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
 377                                 brcm,pins = <42 43>;
 378                                 brcm,function = <BCM2835_FSEL_ALT5>;
 379                         };
 380                 };
 381
 382                 uart0: serial@7e201000 {
 383                         compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
 384                         reg = <0x7e201000 0x1000>;
 385                         interrupts = <2 25>;
 386                         clocks = <&clocks BCM2835_CLOCK_UART>,
 387                                  <&clocks BCM2835_CLOCK_VPU>;
 388                         clock-names = "uartclk", "apb_pclk";
 389                         arm,primecell-periphid = <0x00241011>;
 390                 };
 391
 392                 sdhost: mmc@7e202000 {
 393                         compatible = "brcm,bcm2835-sdhost";
 394                         reg = <0x7e202000 0x100>;
 395                         interrupts = <2 24>;
 396                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 397                         dmas = <&dma 13>;
 398                         dma-names = "rx-tx";
 399                         status = "disabled";
 400                 };
 401
 402                 i2s: i2s@7e203000 {
 403                         compatible = "brcm,bcm2835-i2s";
 404                         reg = <0x7e203000 0x24>;
 405                         clocks = <&clocks BCM2835_CLOCK_PCM>;
 406
 407                         dmas = <&dma 2>,
 408                                <&dma 3>;
 409                         dma-names = "tx", "rx";
 410                         status = "disabled";
 411                 };
 412
 413                 spi: spi@7e204000 {
 414                         compatible = "brcm,bcm2835-spi";
 415                         reg = <0x7e204000 0x1000>;
 416                         interrupts = <2 22>;
 417                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         status = "disabled";
 421                 };
 422
 423                 i2c0: i2c@7e205000 {
 424                         compatible = "brcm,bcm2835-i2c";
 425                         reg = <0x7e205000 0x1000>;
 426                         interrupts = <2 21>;
 427                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 428                         #address-cells = <1>;
 429                         #size-cells = <0>;
 430                         status = "disabled";
 431                 };
 432
 433                 pixelvalve@7e206000 {
 434                         compatible = "brcm,bcm2835-pixelvalve0";
 435                         reg = <0x7e206000 0x100>;
 436                         interrupts = <2 13>; /* pwa0 */
 437                 };
 438
 439                 pixelvalve@7e207000 {
 440                         compatible = "brcm,bcm2835-pixelvalve1";
 441                         reg = <0x7e207000 0x100>;
 442                         interrupts = <2 14>; /* pwa1 */
 443                 };
 444
 445                 dpi: dpi@7e208000 {
 446                         compatible = "brcm,bcm2835-dpi";
 447                         reg = <0x7e208000 0x8c>;
 448                         clocks = <&clocks BCM2835_CLOCK_VPU>,
 449                                  <&clocks BCM2835_CLOCK_DPI>;
 450                         clock-names = "core", "pixel";
 451                         #address-cells = <1>;
 452                         #size-cells = <0>;
 453                         status = "disabled";
 454                 };
 455
 456                 dsi0: dsi@7e209000 {
 457                         compatible = "brcm,bcm2835-dsi0";
 458                         reg = <0x7e209000 0x78>;
 459                         interrupts = <2 4>;
 460                         #address-cells = <1>;
 461                         #size-cells = <0>;
 462                         #clock-cells = <1>;
 463
 464                         clocks = <&clocks BCM2835_PLLA_DSI0>,
 465                                  <&clocks BCM2835_CLOCK_DSI0E>,
 466                                  <&clocks BCM2835_CLOCK_DSI0P>;
 467                         clock-names = "phy", "escape", "pixel";
 468
 469                         clock-output-names = "dsi0_byte",
 470                                              "dsi0_ddr2",
 471                                              "dsi0_ddr";
 472
 473                 };
 474
 475                 thermal: thermal@7e212000 {
 476                         compatible = "brcm,bcm2835-thermal";
 477                         reg = <0x7e212000 0x8>;
 478                         clocks = <&clocks BCM2835_CLOCK_TSENS>;
 479                         #thermal-sensor-cells = <0>;
 480                         status = "disabled";
 481                 };
 482
 483                 aux: aux@7e215000 {
 484                         compatible = "brcm,bcm2835-aux";
 485                         #clock-cells = <1>;
 486                         reg = <0x7e215000 0x8>;
 487                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 488                 };
 489
 490                 uart1: serial@7e215040 {
 491                         compatible = "brcm,bcm2835-aux-uart";
 492                         reg = <0x7e215040 0x40>;
 493                         interrupts = <1 29>;
 494                         clocks = <&aux BCM2835_AUX_CLOCK_UART>;
 495                         status = "disabled";
 496                 };
 497
 498                 spi1: spi@7e215080 {
 499                         compatible = "brcm,bcm2835-aux-spi";
 500                         reg = <0x7e215080 0x40>;
 501                         interrupts = <1 29>;
 502                         clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
 503                         #address-cells = <1>;
 504                         #size-cells = <0>;
 505                         status = "disabled";
 506                 };
 507
 508                 spi2: spi@7e2150c0 {
 509                         compatible = "brcm,bcm2835-aux-spi";
 510                         reg = <0x7e2150c0 0x40>;
 511                         interrupts = <1 29>;
 512                         clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         status = "disabled";
 516                 };
 517
 518                 pwm: pwm@7e20c000 {
 519                         compatible = "brcm,bcm2835-pwm";
 520                         reg = <0x7e20c000 0x28>;
 521                         clocks = <&clocks BCM2835_CLOCK_PWM>;
 522                         assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
 523                         assigned-clock-rates = <10000000>;
 524                         #pwm-cells = <2>;
 525                         status = "disabled";
 526                 };
 527
 528                 sdhci: sdhci@7e300000 {
 529                         compatible = "brcm,bcm2835-sdhci";
 530                         reg = <0x7e300000 0x100>;
 531                         interrupts = <2 30>;
 532                         clocks = <&clocks BCM2835_CLOCK_EMMC>;
 533                         status = "disabled";
 534                 };
 535
 536                 hvs@7e400000 {
 537                         compatible = "brcm,bcm2835-hvs";
 538                         reg = <0x7e400000 0x6000>;
 539                         interrupts = <2 1>;
 540                 };
 541
 542                 dsi1: dsi@7e700000 {
 543                         compatible = "brcm,bcm2835-dsi1";
 544                         reg = <0x7e700000 0x8c>;
 545                         interrupts = <2 12>;
 546                         #address-cells = <1>;
 547                         #size-cells = <0>;
 548                         #clock-cells = <1>;
 549
 550                         clocks = <&clocks BCM2835_PLLD_DSI1>,
 551                                  <&clocks BCM2835_CLOCK_DSI1E>,
 552                                  <&clocks BCM2835_CLOCK_DSI1P>;
 553                         clock-names = "phy", "escape", "pixel";
 554
 555                         clock-output-names = "dsi1_byte",
 556                                              "dsi1_ddr2",
 557                                              "dsi1_ddr";
 558
 559                         status = "disabled";
 560                 };
 561
 562                 i2c1: i2c@7e804000 {
 563                         compatible = "brcm,bcm2835-i2c";
 564                         reg = <0x7e804000 0x1000>;
 565                         interrupts = <2 21>;
 566                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 567                         #address-cells = <1>;
 568                         #size-cells = <0>;
 569                         status = "disabled";
 570                 };
 571
 572                 i2c2: i2c@7e805000 {
 573                         compatible = "brcm,bcm2835-i2c";
 574                         reg = <0x7e805000 0x1000>;
 575                         interrupts = <2 21>;
 576                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 577                         #address-cells = <1>;
 578                         #size-cells = <0>;
 579                         status = "disabled";
 580                 };
 581
 582                 vec: vec@7e806000 {
 583                         compatible = "brcm,bcm2835-vec";
 584                         reg = <0x7e806000 0x1000>;
 585                         clocks = <&clocks BCM2835_CLOCK_VEC>;
 586                         interrupts = <2 27>;
 587                         status = "disabled";
 588                 };
 589
 590                 pixelvalve@7e807000 {
 591                         compatible = "brcm,bcm2835-pixelvalve2";
 592                         reg = <0x7e807000 0x100>;
 593                         interrupts = <2 10>; /* pixelvalve */
 594                 };
 595
 596                 hdmi: hdmi@7e902000 {
 597                         compatible = "brcm,bcm2835-hdmi";
 598                         reg = <0x7e902000 0x600>,
 599                               <0x7e808000 0x100>;
 600                         interrupts = <2 8>, <2 9>;
 601                         ddc = <&i2c2>;
 602                         clocks = <&clocks BCM2835_PLLH_PIX>,
 603                                  <&clocks BCM2835_CLOCK_HSM>;
 604                         clock-names = "pixel", "hdmi";
 605                         dmas = <&dma 17>;
 606                         dma-names = "audio-rx";
 607                         status = "disabled";
 608                 };
 609
 610                 usb: usb@7e980000 {
 611                         compatible = "brcm,bcm2835-usb";
 612                         reg = <0x7e980000 0x10000>;
 613                         interrupts = <1 9>;
 614                         #address-cells = <1>;
 615                         #size-cells = <0>;
 616                         clocks = <&clk_usb>;
 617                         clock-names = "otg";
 618                         phys = <&usbphy>;
 619                         phy-names = "usb2-phy";
 620                 };
 621
 622                 v3d: v3d@7ec00000 {
 623                         compatible = "brcm,bcm2835-v3d";
 624                         reg = <0x7ec00000 0x1000>;
 625                         interrupts = <1 10>;
 626                 };
 627
 628                 vc4: gpu {
 629                         compatible = "brcm,bcm2835-vc4";
 630                 };
 631         };
 632
 633         clocks {
 634                 compatible = "simple-bus";
 635                 #address-cells = <1>;
 636                 #size-cells = <0>;
 637
 638                 /* The oscillator is the root of the clock tree. */
 639                 clk_osc: clock@3 {
 640                         compatible = "fixed-clock";
 641                         reg = <3>;
 642                         #clock-cells = <0>;
 643                         clock-output-names = "osc";
 644                         clock-frequency = <19200000>;
 645                 };
 646
 647                 clk_usb: clock@4 {
 648                         compatible = "fixed-clock";
 649                         reg = <4>;
 650                         #clock-cells = <0>;
 651                         clock-output-names = "otg";
 652                         clock-frequency = <480000000>;
 653                 };
 654         };
 655
 656         usbphy: phy {
 657                 compatible = "usb-nop-xceiv";
 658                 #phy-cells = <0>;
 659         };
 660 };