arch/arm/boot/dts/bcm283x.dtsi

   1 #include <dt-bindings/pinctrl/bcm2835.h>
   2 #include <dt-bindings/clock/bcm2835.h>
   3 #include <dt-bindings/clock/bcm2835-aux.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5
   6 /* firmware-provided startup stubs live here, where the secondary CPUs are
   7  * spinning.
   8  */
   9 /memreserve/ 0x00000000 0x00001000;
  10
  11 /* This include file covers the common peripherals and configuration between
  12  * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
  13  * bcm2835.dtsi and bcm2836.dtsi.
  14  */
  15
  16 / {
  17         compatible = "brcm,bcm2835";
  18         model = "BCM2835";
  19         interrupt-parent = <&intc>;
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         chosen {
  24                 bootargs = "earlyprintk console=ttyAMA0";
  25         };
  26
  27         thermal-zones {
  28                 cpu_thermal: cpu-thermal {
  29                         polling-delay-passive = <0>;
  30                         polling-delay = <1000>;
  31
  32                         thermal-sensors = <&thermal>;
  33
  34                         trips {
  35                                 cpu-crit {
  36                                         temperature     = <80000>;
  37                                         hysteresis      = <0>;
  38                                         type            = "critical";
  39                                 };
  40                         };
  41
  42                         cooling-maps {
  43                         };
  44                 };
  45         };
  46
  47         soc {
  48                 compatible = "simple-bus";
  49                 #address-cells = <1>;
  50                 #size-cells = <1>;
  51
  52                 timer@7e003000 {
  53                         compatible = "brcm,bcm2835-system-timer";
  54                         reg = <0x7e003000 0x1000>;
  55                         interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
  56                         /* This could be a reference to BCM2835_CLOCK_TIMER,
  57                          * but we don't have the driver using the common clock
  58                          * support yet.
  59                          */
  60                         clock-frequency = <1000000>;
  61                 };
  62
  63                 dma: dma@7e007000 {
  64                         compatible = "brcm,bcm2835-dma";
  65                         reg = <0x7e007000 0xf00>;
  66                         interrupts = <1 16>,
  67                                      <1 17>,
  68                                      <1 18>,
  69                                      <1 19>,
  70                                      <1 20>,
  71                                      <1 21>,
  72                                      <1 22>,
  73                                      <1 23>,
  74                                      <1 24>,
  75                                      <1 25>,
  76                                      <1 26>,
  77                                      /* dma channel 11-14 share one irq */
  78                                      <1 27>,
  79                                      <1 27>,
  80                                      <1 27>,
  81                                      <1 27>,
  82                                      /* unused shared irq for all channels */
  83                                      <1 28>;
  84                         interrupt-names = "dma0",
  85                                           "dma1",
  86                                           "dma2",
  87                                           "dma3",
  88                                           "dma4",
  89                                           "dma5",
  90                                           "dma6",
  91                                           "dma7",
  92                                           "dma8",
  93                                           "dma9",
  94                                           "dma10",
  95                                           "dma11",
  96                                           "dma12",
  97                                           "dma13",
  98                                           "dma14",
  99                                           "dma-shared-all";
 100                         #dma-cells = <1>;
 101                         brcm,dma-channel-mask = <0x7f35>;
 102                 };
 103
 104                 intc: interrupt-controller@7e00b200 {
 105                         compatible = "brcm,bcm2835-armctrl-ic";
 106                         reg = <0x7e00b200 0x200>;
 107                         interrupt-controller;
 108                         #interrupt-cells = <2>;
 109                 };
 110
 111                 watchdog@7e100000 {
 112                         compatible = "brcm,bcm2835-pm-wdt";
 113                         reg = <0x7e100000 0x28>;
 114                 };
 115
 116                 clocks: cprman@7e101000 {
 117                         compatible = "brcm,bcm2835-cprman";
 118                         #clock-cells = <1>;
 119                         reg = <0x7e101000 0x2000>;
 120
 121                         /* CPRMAN derives almost everything from the
 122                          * platform's oscillator.  However, the DSI
 123                          * pixel clocks come from the DSI analog PHY.
 124                          */
 125                         clocks = <&clk_osc>,
 126                                 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
 127                                 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
 128                 };
 129
 130                 rng@7e104000 {
 131                         compatible = "brcm,bcm2835-rng";
 132                         reg = <0x7e104000 0x10>;
 133                 };
 134
 135                 mailbox: mailbox@7e00b880 {
 136                         compatible = "brcm,bcm2835-mbox";
 137                         reg = <0x7e00b880 0x40>;
 138                         interrupts = <0 1>;
 139                         #mbox-cells = <0>;
 140                 };
 141
 142                 gpio: gpio@7e200000 {
 143                         compatible = "brcm,bcm2835-gpio";
 144                         reg = <0x7e200000 0xb4>;
 145                         /*
 146                          * The GPIO IP block is designed for 3 banks of GPIOs.
 147                          * Each bank has a GPIO interrupt for itself.
 148                          * There is an overall "any bank" interrupt.
 149                          * In order, these are GIC interrupts 17, 18, 19, 20.
 150                          * Since the BCM2835 only has 2 banks, the 2nd bank
 151                          * interrupt output appears to be mirrored onto the
 152                          * 3rd bank's interrupt signal.
 153                          * So, a bank0 interrupt shows up on 17, 20, and
 154                          * a bank1 interrupt shows up on 18, 19, 20!
 155                          */
 156                         interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
 157
 158                         gpio-controller;
 159                         #gpio-cells = <2>;
 160
 161                         interrupt-controller;
 162                         #interrupt-cells = <2>;
 163
 164                         /* Defines pin muxing groups according to
 165                          * BCM2835-ARM-Peripherals.pdf page 102.
 166                          *
 167                          * While each pin can have its mux selected
 168                          * for various functions individually, some
 169                          * groups only make sense to switch to a
 170                          * particular function together.
 171                          */
 172                         dpi_gpio0: dpi_gpio0 {
 173                                 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
 174                                              12 13 14 15 16 17 18 19
 175                                              20 21 22 23 24 25 26 27>;
 176                                 brcm,function = <BCM2835_FSEL_ALT2>;
 177                         };
 178                         emmc_gpio22: emmc_gpio22 {
 179                                 brcm,pins = <22 23 24 25 26 27>;
 180                                 brcm,function = <BCM2835_FSEL_ALT3>;
 181                         };
 182                         emmc_gpio34: emmc_gpio34 {
 183                                 brcm,pins = <34 35 36 37 38 39>;
 184                                 brcm,function = <BCM2835_FSEL_ALT3>;
 185                                 brcm,pull = <BCM2835_PUD_OFF
 186                                              BCM2835_PUD_UP
 187                                              BCM2835_PUD_UP
 188                                              BCM2835_PUD_UP
 189                                              BCM2835_PUD_UP
 190                                              BCM2835_PUD_UP>;
 191                         };
 192                         emmc_gpio48: emmc_gpio48 {
 193                                 brcm,pins = <48 49 50 51 52 53>;
 194                                 brcm,function = <BCM2835_FSEL_ALT3>;
 195                         };
 196
 197                         gpclk0_gpio4: gpclk0_gpio4 {
 198                                 brcm,pins = <4>;
 199                                 brcm,function = <BCM2835_FSEL_ALT0>;
 200                         };
 201                         gpclk1_gpio5: gpclk1_gpio5 {
 202                                 brcm,pins = <5>;
 203                                 brcm,function = <BCM2835_FSEL_ALT0>;
 204                         };
 205                         gpclk1_gpio42: gpclk1_gpio42 {
 206                                 brcm,pins = <42>;
 207                                 brcm,function = <BCM2835_FSEL_ALT0>;
 208                         };
 209                         gpclk1_gpio44: gpclk1_gpio44 {
 210                                 brcm,pins = <44>;
 211                                 brcm,function = <BCM2835_FSEL_ALT0>;
 212                         };
 213                         gpclk2_gpio6: gpclk2_gpio6 {
 214                                 brcm,pins = <6>;
 215                                 brcm,function = <BCM2835_FSEL_ALT0>;
 216                         };
 217                         gpclk2_gpio43: gpclk2_gpio43 {
 218                                 brcm,pins = <43>;
 219                                 brcm,function = <BCM2835_FSEL_ALT0>;
 220                         };
 221
 222                         i2c0_gpio0: i2c0_gpio0 {
 223                                 brcm,pins = <0 1>;
 224                                 brcm,function = <BCM2835_FSEL_ALT0>;
 225                         };
 226                         i2c0_gpio28: i2c0_gpio28 {
 227                                 brcm,pins = <28 29>;
 228                                 brcm,function = <BCM2835_FSEL_ALT0>;
 229                         };
 230                         i2c0_gpio44: i2c0_gpio44 {
 231                                 brcm,pins = <44 45>;
 232                                 brcm,function = <BCM2835_FSEL_ALT1>;
 233                         };
 234                         i2c1_gpio2: i2c1_gpio2 {
 235                                 brcm,pins = <2 3>;
 236                                 brcm,function = <BCM2835_FSEL_ALT0>;
 237                         };
 238                         i2c1_gpio44: i2c1_gpio44 {
 239                                 brcm,pins = <44 45>;
 240                                 brcm,function = <BCM2835_FSEL_ALT2>;
 241                         };
 242                         i2c_slave_gpio18: i2c_slave_gpio18 {
 243                                 brcm,pins = <18 19 20 21>;
 244                                 brcm,function = <BCM2835_FSEL_ALT3>;
 245                         };
 246
 247                         jtag_gpio4: jtag_gpio4 {
 248                                 brcm,pins = <4 5 6 12 13>;
 249                                 brcm,function = <BCM2835_FSEL_ALT4>;
 250                         };
 251                         jtag_gpio22: jtag_gpio22 {
 252                                 brcm,pins = <22 23 24 25 26 27>;
 253                                 brcm,function = <BCM2835_FSEL_ALT4>;
 254                         };
 255
 256                         pcm_gpio18: pcm_gpio18 {
 257                                 brcm,pins = <18 19 20 21>;
 258                                 brcm,function = <BCM2835_FSEL_ALT0>;
 259                         };
 260                         pcm_gpio28: pcm_gpio28 {
 261                                 brcm,pins = <28 29 30 31>;
 262                                 brcm,function = <BCM2835_FSEL_ALT2>;
 263                         };
 264
 265                         pwm0_gpio12: pwm0_gpio12 {
 266                                 brcm,pins = <12>;
 267                                 brcm,function = <BCM2835_FSEL_ALT0>;
 268                         };
 269                         pwm0_gpio18: pwm0_gpio18 {
 270                                 brcm,pins = <18>;
 271                                 brcm,function = <BCM2835_FSEL_ALT5>;
 272                         };
 273                         pwm0_gpio40: pwm0_gpio40 {
 274                                 brcm,pins = <40>;
 275                                 brcm,function = <BCM2835_FSEL_ALT0>;
 276                         };
 277                         pwm1_gpio13: pwm1_gpio13 {
 278                                 brcm,pins = <13>;
 279                                 brcm,function = <BCM2835_FSEL_ALT0>;
 280                         };
 281                         pwm1_gpio19: pwm1_gpio19 {
 282                                 brcm,pins = <19>;
 283                                 brcm,function = <BCM2835_FSEL_ALT5>;
 284                         };
 285                         pwm1_gpio41: pwm1_gpio41 {
 286                                 brcm,pins = <41>;
 287                                 brcm,function = <BCM2835_FSEL_ALT0>;
 288                         };
 289                         pwm1_gpio45: pwm1_gpio45 {
 290                                 brcm,pins = <45>;
 291                                 brcm,function = <BCM2835_FSEL_ALT0>;
 292                         };
 293
 294                         sdhost_gpio48: sdhost_gpio48 {
 295                                 brcm,pins = <48 49 50 51 52 53>;
 296                                 brcm,function = <BCM2835_FSEL_ALT0>;
 297                         };
 298
 299                         spi0_gpio7: spi0_gpio7 {
 300                                 brcm,pins = <7 8 9 10 11>;
 301                                 brcm,function = <BCM2835_FSEL_ALT0>;
 302                         };
 303                         spi0_gpio35: spi0_gpio35 {
 304                                 brcm,pins = <35 36 37 38 39>;
 305                                 brcm,function = <BCM2835_FSEL_ALT0>;
 306                         };
 307                         spi1_gpio16: spi1_gpio16 {
 308                                 brcm,pins = <16 17 18 19 20 21>;
 309                                 brcm,function = <BCM2835_FSEL_ALT4>;
 310                         };
 311                         spi2_gpio40: spi2_gpio40 {
 312                                 brcm,pins = <40 41 42 43 44 45>;
 313                                 brcm,function = <BCM2835_FSEL_ALT4>;
 314                         };
 315
 316                         uart0_gpio14: uart0_gpio14 {
 317                                 brcm,pins = <14 15>;
 318                                 brcm,function = <BCM2835_FSEL_ALT0>;
 319                         };
 320                         /* Separate from the uart0_gpio14 group
 321                          * because it conflicts with spi1_gpio16, and
 322                          * people often run uart0 on the two pins
 323                          * without flow control.
 324                          */
 325                         uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
 326                                 brcm,pins = <16 17>;
 327                                 brcm,function = <BCM2835_FSEL_ALT3>;
 328                         };
 329                         uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
 330                                 brcm,pins = <30 31>;
 331                                 brcm,function = <BCM2835_FSEL_ALT3>;
 332                         };
 333                         uart0_gpio32: uart0_gpio32 {
 334                                 brcm,pins = <32 33>;
 335                                 brcm,function = <BCM2835_FSEL_ALT3>;
 336                         };
 337                         uart0_gpio36: uart0_gpio36 {
 338                                 brcm,pins = <36 37>;
 339                                 brcm,function = <BCM2835_FSEL_ALT2>;
 340                         };
 341                         uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
 342                                 brcm,pins = <38 39>;
 343                                 brcm,function = <BCM2835_FSEL_ALT2>;
 344                         };
 345
 346                         uart1_gpio14: uart1_gpio14 {
 347                                 brcm,pins = <14 15>;
 348                                 brcm,function = <BCM2835_FSEL_ALT5>;
 349                         };
 350                         uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
 351                                 brcm,pins = <16 17>;
 352                                 brcm,function = <BCM2835_FSEL_ALT5>;
 353                         };
 354                         uart1_gpio32: uart1_gpio32 {
 355                                 brcm,pins = <32 33>;
 356                                 brcm,function = <BCM2835_FSEL_ALT5>;
 357                         };
 358                         uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
 359                                 brcm,pins = <30 31>;
 360                                 brcm,function = <BCM2835_FSEL_ALT5>;
 361                         };
 362                         uart1_gpio40: uart1_gpio40 {
 363                                 brcm,pins = <40 41>;
 364                                 brcm,function = <BCM2835_FSEL_ALT5>;
 365                         };
 366                         uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
 367                                 brcm,pins = <42 43>;
 368                                 brcm,function = <BCM2835_FSEL_ALT5>;
 369                         };
 370                 };
 371
 372                 uart0: serial@7e201000 {
 373                         compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
 374                         reg = <0x7e201000 0x1000>;
 375                         interrupts = <2 25>;
 376                         clocks = <&clocks BCM2835_CLOCK_UART>,
 377                                  <&clocks BCM2835_CLOCK_VPU>;
 378                         clock-names = "uartclk", "apb_pclk";
 379                         arm,primecell-periphid = <0x00241011>;
 380                 };
 381
 382                 sdhost: mmc@7e202000 {
 383                         compatible = "brcm,bcm2835-sdhost";
 384                         reg = <0x7e202000 0x100>;
 385                         interrupts = <2 24>;
 386                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 387                         dmas = <&dma 13>;
 388                         dma-names = "rx-tx";
 389                         status = "disabled";
 390                 };
 391
 392                 i2s: i2s@7e203000 {
 393                         compatible = "brcm,bcm2835-i2s";
 394                         reg = <0x7e203000 0x20>,
 395                               <0x7e101098 0x02>;
 396
 397                         dmas = <&dma 2>,
 398                                <&dma 3>;
 399                         dma-names = "tx", "rx";
 400                         status = "disabled";
 401                 };
 402
 403                 spi: spi@7e204000 {
 404                         compatible = "brcm,bcm2835-spi";
 405                         reg = <0x7e204000 0x1000>;
 406                         interrupts = <2 22>;
 407                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         status = "disabled";
 411                 };
 412
 413                 i2c0: i2c@7e205000 {
 414                         compatible = "brcm,bcm2835-i2c";
 415                         reg = <0x7e205000 0x1000>;
 416                         interrupts = <2 21>;
 417                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 418                         #address-cells = <1>;
 419                         #size-cells = <0>;
 420                         status = "disabled";
 421                 };
 422
 423                 pixelvalve@7e206000 {
 424                         compatible = "brcm,bcm2835-pixelvalve0";
 425                         reg = <0x7e206000 0x100>;
 426                         interrupts = <2 13>; /* pwa0 */
 427                 };
 428
 429                 pixelvalve@7e207000 {
 430                         compatible = "brcm,bcm2835-pixelvalve1";
 431                         reg = <0x7e207000 0x100>;
 432                         interrupts = <2 14>; /* pwa1 */
 433                 };
 434
 435                 dsi0: dsi@7e209000 {
 436                         compatible = "brcm,bcm2835-dsi0";
 437                         reg = <0x7e209000 0x78>;
 438                         interrupts = <2 4>;
 439                         #address-cells = <1>;
 440                         #size-cells = <0>;
 441                         #clock-cells = <1>;
 442
 443                         clocks = <&clocks BCM2835_PLLA_DSI0>,
 444                                  <&clocks BCM2835_CLOCK_DSI0E>,
 445                                  <&clocks BCM2835_CLOCK_DSI0P>;
 446                         clock-names = "phy", "escape", "pixel";
 447
 448                         clock-output-names = "dsi0_byte",
 449                                              "dsi0_ddr2",
 450                                              "dsi0_ddr";
 451
 452                 };
 453
 454                 thermal: thermal@7e212000 {
 455                         compatible = "brcm,bcm2835-thermal";
 456                         reg = <0x7e212000 0x8>;
 457                         clocks = <&clocks BCM2835_CLOCK_TSENS>;
 458                         #thermal-sensor-cells = <0>;
 459                         status = "disabled";
 460                 };
 461
 462                 aux: aux@0x7e215000 {
 463                         compatible = "brcm,bcm2835-aux";
 464                         #clock-cells = <1>;
 465                         reg = <0x7e215000 0x8>;
 466                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 467                 };
 468
 469                 uart1: serial@7e215040 {
 470                         compatible = "brcm,bcm2835-aux-uart";
 471                         reg = <0x7e215040 0x40>;
 472                         interrupts = <1 29>;
 473                         clocks = <&aux BCM2835_AUX_CLOCK_UART>;
 474                         status = "disabled";
 475                 };
 476
 477                 spi1: spi@7e215080 {
 478                         compatible = "brcm,bcm2835-aux-spi";
 479                         reg = <0x7e215080 0x40>;
 480                         interrupts = <1 29>;
 481                         clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
 482                         #address-cells = <1>;
 483                         #size-cells = <0>;
 484                         status = "disabled";
 485                 };
 486
 487                 spi2: spi@7e2150c0 {
 488                         compatible = "brcm,bcm2835-aux-spi";
 489                         reg = <0x7e2150c0 0x40>;
 490                         interrupts = <1 29>;
 491                         clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494                         status = "disabled";
 495                 };
 496
 497                 pwm: pwm@7e20c000 {
 498                         compatible = "brcm,bcm2835-pwm";
 499                         reg = <0x7e20c000 0x28>;
 500                         clocks = <&clocks BCM2835_CLOCK_PWM>;
 501                         assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
 502                         assigned-clock-rates = <10000000>;
 503                         #pwm-cells = <2>;
 504                         status = "disabled";
 505                 };
 506
 507                 sdhci: sdhci@7e300000 {
 508                         compatible = "brcm,bcm2835-sdhci";
 509                         reg = <0x7e300000 0x100>;
 510                         interrupts = <2 30>;
 511                         clocks = <&clocks BCM2835_CLOCK_EMMC>;
 512                         status = "disabled";
 513                 };
 514
 515                 hvs@7e400000 {
 516                         compatible = "brcm,bcm2835-hvs";
 517                         reg = <0x7e400000 0x6000>;
 518                         interrupts = <2 1>;
 519                 };
 520
 521                 dsi1: dsi@7e700000 {
 522                         compatible = "brcm,bcm2835-dsi1";
 523                         reg = <0x7e700000 0x8c>;
 524                         interrupts = <2 12>;
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527                         #clock-cells = <1>;
 528
 529                         clocks = <&clocks BCM2835_PLLD_DSI1>,
 530                                  <&clocks BCM2835_CLOCK_DSI1E>,
 531                                  <&clocks BCM2835_CLOCK_DSI1P>;
 532                         clock-names = "phy", "escape", "pixel";
 533
 534                         clock-output-names = "dsi1_byte",
 535                                              "dsi1_ddr2",
 536                                              "dsi1_ddr";
 537
 538                         status = "disabled";
 539                 };
 540
 541                 i2c1: i2c@7e804000 {
 542                         compatible = "brcm,bcm2835-i2c";
 543                         reg = <0x7e804000 0x1000>;
 544                         interrupts = <2 21>;
 545                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 546                         #address-cells = <1>;
 547                         #size-cells = <0>;
 548                         status = "disabled";
 549                 };
 550
 551                 i2c2: i2c@7e805000 {
 552                         compatible = "brcm,bcm2835-i2c";
 553                         reg = <0x7e805000 0x1000>;
 554                         interrupts = <2 21>;
 555                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 556                         #address-cells = <1>;
 557                         #size-cells = <0>;
 558                         status = "disabled";
 559                 };
 560
 561                 vec: vec@7e806000 {
 562                         compatible = "brcm,bcm2835-vec";
 563                         reg = <0x7e806000 0x1000>;
 564                         clocks = <&clocks BCM2835_CLOCK_VEC>;
 565                         interrupts = <2 27>;
 566                         status = "disabled";
 567                 };
 568
 569                 pixelvalve@7e807000 {
 570                         compatible = "brcm,bcm2835-pixelvalve2";
 571                         reg = <0x7e807000 0x100>;
 572                         interrupts = <2 10>; /* pixelvalve */
 573                 };
 574
 575                 hdmi: hdmi@7e902000 {
 576                         compatible = "brcm,bcm2835-hdmi";
 577                         reg = <0x7e902000 0x600>,
 578                               <0x7e808000 0x100>;
 579                         interrupts = <2 8>, <2 9>;
 580                         ddc = <&i2c2>;
 581                         clocks = <&clocks BCM2835_PLLH_PIX>,
 582                                  <&clocks BCM2835_CLOCK_HSM>;
 583                         clock-names = "pixel", "hdmi";
 584                         dmas = <&dma 17>;
 585                         dma-names = "audio-rx";
 586                         status = "disabled";
 587                 };
 588
 589                 usb: usb@7e980000 {
 590                         compatible = "brcm,bcm2835-usb";
 591                         reg = <0x7e980000 0x10000>;
 592                         interrupts = <1 9>;
 593                         #address-cells = <1>;
 594                         #size-cells = <0>;
 595                         clocks = <&clk_usb>;
 596                         clock-names = "otg";
 597                         phys = <&usbphy>;
 598                         phy-names = "usb2-phy";
 599                 };
 600
 601                 v3d: v3d@7ec00000 {
 602                         compatible = "brcm,bcm2835-v3d";
 603                         reg = <0x7ec00000 0x1000>;
 604                         interrupts = <1 10>;
 605                 };
 606
 607                 vc4: gpu {
 608                         compatible = "brcm,bcm2835-vc4";
 609                 };
 610         };
 611
 612         clocks {
 613                 compatible = "simple-bus";
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616
 617                 /* The oscillator is the root of the clock tree. */
 618                 clk_osc: clock@3 {
 619                         compatible = "fixed-clock";
 620                         reg = <3>;
 621                         #clock-cells = <0>;
 622                         clock-output-names = "osc";
 623                         clock-frequency = <19200000>;
 624                 };
 625
 626                 clk_usb: clock@4 {
 627                         compatible = "fixed-clock";
 628                         reg = <4>;
 629                         #clock-cells = <0>;
 630                         clock-output-names = "otg";
 631                         clock-frequency = <480000000>;
 632                 };
 633         };
 634
 635         usbphy: phy {
 636                 compatible = "usb-nop-xceiv";
 637         };
 638 };