arch/arm/boot/dts/bcm283x.dtsi

   1 #include <dt-bindings/pinctrl/bcm2835.h>
   2 #include <dt-bindings/clock/bcm2835.h>
   3 #include <dt-bindings/clock/bcm2835-aux.h>
   4 #include <dt-bindings/gpio/gpio.h>
   5
   6 /* firmware-provided startup stubs live here, where the secondary CPUs are
   7  * spinning.
   8  */
   9 /memreserve/ 0x00000000 0x00001000;
  10
  11 /* This include file covers the common peripherals and configuration between
  12  * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
  13  * bcm2835.dtsi and bcm2836.dtsi.
  14  */
  15
  16 / {
  17         compatible = "brcm,bcm2835";
  18         model = "BCM2835";
  19         interrupt-parent = <&intc>;
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         aliases {
  24                 serial0 = &uart0;
  25                 serial1 = &uart1;
  26         };
  27
  28         chosen {
  29                 stdout-path = "serial0:115200n8";
  30         };
  31
  32         thermal-zones {
  33                 cpu_thermal: cpu-thermal {
  34                         polling-delay-passive = <0>;
  35                         polling-delay = <1000>;
  36
  37                         thermal-sensors = <&thermal>;
  38
  39                         trips {
  40                                 cpu-crit {
  41                                         temperature     = <80000>;
  42                                         hysteresis      = <0>;
  43                                         type            = "critical";
  44                                 };
  45                         };
  46
  47                         cooling-maps {
  48                         };
  49                 };
  50         };
  51
  52         soc {
  53                 compatible = "simple-bus";
  54                 #address-cells = <1>;
  55                 #size-cells = <1>;
  56
  57                 timer@7e003000 {
  58                         compatible = "brcm,bcm2835-system-timer";
  59                         reg = <0x7e003000 0x1000>;
  60                         interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
  61                         /* This could be a reference to BCM2835_CLOCK_TIMER,
  62                          * but we don't have the driver using the common clock
  63                          * support yet.
  64                          */
  65                         clock-frequency = <1000000>;
  66                 };
  67
  68                 dma: dma@7e007000 {
  69                         compatible = "brcm,bcm2835-dma";
  70                         reg = <0x7e007000 0xf00>;
  71                         interrupts = <1 16>,
  72                                      <1 17>,
  73                                      <1 18>,
  74                                      <1 19>,
  75                                      <1 20>,
  76                                      <1 21>,
  77                                      <1 22>,
  78                                      <1 23>,
  79                                      <1 24>,
  80                                      <1 25>,
  81                                      <1 26>,
  82                                      /* dma channel 11-14 share one irq */
  83                                      <1 27>,
  84                                      <1 27>,
  85                                      <1 27>,
  86                                      <1 27>,
  87                                      /* unused shared irq for all channels */
  88                                      <1 28>;
  89                         interrupt-names = "dma0",
  90                                           "dma1",
  91                                           "dma2",
  92                                           "dma3",
  93                                           "dma4",
  94                                           "dma5",
  95                                           "dma6",
  96                                           "dma7",
  97                                           "dma8",
  98                                           "dma9",
  99                                           "dma10",
 100                                           "dma11",
 101                                           "dma12",
 102                                           "dma13",
 103                                           "dma14",
 104                                           "dma-shared-all";
 105                         #dma-cells = <1>;
 106                         brcm,dma-channel-mask = <0x7f35>;
 107                 };
 108
 109                 intc: interrupt-controller@7e00b200 {
 110                         compatible = "brcm,bcm2835-armctrl-ic";
 111                         reg = <0x7e00b200 0x200>;
 112                         interrupt-controller;
 113                         #interrupt-cells = <2>;
 114                 };
 115
 116                 watchdog@7e100000 {
 117                         compatible = "brcm,bcm2835-pm-wdt";
 118                         reg = <0x7e100000 0x28>;
 119                 };
 120
 121                 clocks: cprman@7e101000 {
 122                         compatible = "brcm,bcm2835-cprman";
 123                         #clock-cells = <1>;
 124                         reg = <0x7e101000 0x2000>;
 125
 126                         /* CPRMAN derives almost everything from the
 127                          * platform's oscillator.  However, the DSI
 128                          * pixel clocks come from the DSI analog PHY.
 129                          */
 130                         clocks = <&clk_osc>,
 131                                 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
 132                                 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
 133                 };
 134
 135                 rng@7e104000 {
 136                         compatible = "brcm,bcm2835-rng";
 137                         reg = <0x7e104000 0x10>;
 138                 };
 139
 140                 mailbox: mailbox@7e00b880 {
 141                         compatible = "brcm,bcm2835-mbox";
 142                         reg = <0x7e00b880 0x40>;
 143                         interrupts = <0 1>;
 144                         #mbox-cells = <0>;
 145                 };
 146
 147                 gpio: gpio@7e200000 {
 148                         compatible = "brcm,bcm2835-gpio";
 149                         reg = <0x7e200000 0xb4>;
 150                         /*
 151                          * The GPIO IP block is designed for 3 banks of GPIOs.
 152                          * Each bank has a GPIO interrupt for itself.
 153                          * There is an overall "any bank" interrupt.
 154                          * In order, these are GIC interrupts 17, 18, 19, 20.
 155                          * Since the BCM2835 only has 2 banks, the 2nd bank
 156                          * interrupt output appears to be mirrored onto the
 157                          * 3rd bank's interrupt signal.
 158                          * So, a bank0 interrupt shows up on 17, 20, and
 159                          * a bank1 interrupt shows up on 18, 19, 20!
 160                          */
 161                         interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
 162
 163                         gpio-controller;
 164                         #gpio-cells = <2>;
 165
 166                         interrupt-controller;
 167                         #interrupt-cells = <2>;
 168
 169                         /* Defines pin muxing groups according to
 170                          * BCM2835-ARM-Peripherals.pdf page 102.
 171                          *
 172                          * While each pin can have its mux selected
 173                          * for various functions individually, some
 174                          * groups only make sense to switch to a
 175                          * particular function together.
 176                          */
 177                         dpi_gpio0: dpi_gpio0 {
 178                                 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
 179                                              12 13 14 15 16 17 18 19
 180                                              20 21 22 23 24 25 26 27>;
 181                                 brcm,function = <BCM2835_FSEL_ALT2>;
 182                         };
 183                         emmc_gpio22: emmc_gpio22 {
 184                                 brcm,pins = <22 23 24 25 26 27>;
 185                                 brcm,function = <BCM2835_FSEL_ALT3>;
 186                         };
 187                         emmc_gpio34: emmc_gpio34 {
 188                                 brcm,pins = <34 35 36 37 38 39>;
 189                                 brcm,function = <BCM2835_FSEL_ALT3>;
 190                                 brcm,pull = <BCM2835_PUD_OFF
 191                                              BCM2835_PUD_UP
 192                                              BCM2835_PUD_UP
 193                                              BCM2835_PUD_UP
 194                                              BCM2835_PUD_UP
 195                                              BCM2835_PUD_UP>;
 196                         };
 197                         emmc_gpio48: emmc_gpio48 {
 198                                 brcm,pins = <48 49 50 51 52 53>;
 199                                 brcm,function = <BCM2835_FSEL_ALT3>;
 200                         };
 201
 202                         gpclk0_gpio4: gpclk0_gpio4 {
 203                                 brcm,pins = <4>;
 204                                 brcm,function = <BCM2835_FSEL_ALT0>;
 205                         };
 206                         gpclk1_gpio5: gpclk1_gpio5 {
 207                                 brcm,pins = <5>;
 208                                 brcm,function = <BCM2835_FSEL_ALT0>;
 209                         };
 210                         gpclk1_gpio42: gpclk1_gpio42 {
 211                                 brcm,pins = <42>;
 212                                 brcm,function = <BCM2835_FSEL_ALT0>;
 213                         };
 214                         gpclk1_gpio44: gpclk1_gpio44 {
 215                                 brcm,pins = <44>;
 216                                 brcm,function = <BCM2835_FSEL_ALT0>;
 217                         };
 218                         gpclk2_gpio6: gpclk2_gpio6 {
 219                                 brcm,pins = <6>;
 220                                 brcm,function = <BCM2835_FSEL_ALT0>;
 221                         };
 222                         gpclk2_gpio43: gpclk2_gpio43 {
 223                                 brcm,pins = <43>;
 224                                 brcm,function = <BCM2835_FSEL_ALT0>;
 225                         };
 226
 227                         i2c0_gpio0: i2c0_gpio0 {
 228                                 brcm,pins = <0 1>;
 229                                 brcm,function = <BCM2835_FSEL_ALT0>;
 230                         };
 231                         i2c0_gpio28: i2c0_gpio28 {
 232                                 brcm,pins = <28 29>;
 233                                 brcm,function = <BCM2835_FSEL_ALT0>;
 234                         };
 235                         i2c0_gpio44: i2c0_gpio44 {
 236                                 brcm,pins = <44 45>;
 237                                 brcm,function = <BCM2835_FSEL_ALT1>;
 238                         };
 239                         i2c1_gpio2: i2c1_gpio2 {
 240                                 brcm,pins = <2 3>;
 241                                 brcm,function = <BCM2835_FSEL_ALT0>;
 242                         };
 243                         i2c1_gpio44: i2c1_gpio44 {
 244                                 brcm,pins = <44 45>;
 245                                 brcm,function = <BCM2835_FSEL_ALT2>;
 246                         };
 247                         i2c_slave_gpio18: i2c_slave_gpio18 {
 248                                 brcm,pins = <18 19 20 21>;
 249                                 brcm,function = <BCM2835_FSEL_ALT3>;
 250                         };
 251
 252                         jtag_gpio4: jtag_gpio4 {
 253                                 brcm,pins = <4 5 6 12 13>;
 254                                 brcm,function = <BCM2835_FSEL_ALT4>;
 255                         };
 256                         jtag_gpio22: jtag_gpio22 {
 257                                 brcm,pins = <22 23 24 25 26 27>;
 258                                 brcm,function = <BCM2835_FSEL_ALT4>;
 259                         };
 260
 261                         pcm_gpio18: pcm_gpio18 {
 262                                 brcm,pins = <18 19 20 21>;
 263                                 brcm,function = <BCM2835_FSEL_ALT0>;
 264                         };
 265                         pcm_gpio28: pcm_gpio28 {
 266                                 brcm,pins = <28 29 30 31>;
 267                                 brcm,function = <BCM2835_FSEL_ALT2>;
 268                         };
 269
 270                         pwm0_gpio12: pwm0_gpio12 {
 271                                 brcm,pins = <12>;
 272                                 brcm,function = <BCM2835_FSEL_ALT0>;
 273                         };
 274                         pwm0_gpio18: pwm0_gpio18 {
 275                                 brcm,pins = <18>;
 276                                 brcm,function = <BCM2835_FSEL_ALT5>;
 277                         };
 278                         pwm0_gpio40: pwm0_gpio40 {
 279                                 brcm,pins = <40>;
 280                                 brcm,function = <BCM2835_FSEL_ALT0>;
 281                         };
 282                         pwm1_gpio13: pwm1_gpio13 {
 283                                 brcm,pins = <13>;
 284                                 brcm,function = <BCM2835_FSEL_ALT0>;
 285                         };
 286                         pwm1_gpio19: pwm1_gpio19 {
 287                                 brcm,pins = <19>;
 288                                 brcm,function = <BCM2835_FSEL_ALT5>;
 289                         };
 290                         pwm1_gpio41: pwm1_gpio41 {
 291                                 brcm,pins = <41>;
 292                                 brcm,function = <BCM2835_FSEL_ALT0>;
 293                         };
 294                         pwm1_gpio45: pwm1_gpio45 {
 295                                 brcm,pins = <45>;
 296                                 brcm,function = <BCM2835_FSEL_ALT0>;
 297                         };
 298
 299                         sdhost_gpio48: sdhost_gpio48 {
 300                                 brcm,pins = <48 49 50 51 52 53>;
 301                                 brcm,function = <BCM2835_FSEL_ALT0>;
 302                         };
 303
 304                         spi0_gpio7: spi0_gpio7 {
 305                                 brcm,pins = <7 8 9 10 11>;
 306                                 brcm,function = <BCM2835_FSEL_ALT0>;
 307                         };
 308                         spi0_gpio35: spi0_gpio35 {
 309                                 brcm,pins = <35 36 37 38 39>;
 310                                 brcm,function = <BCM2835_FSEL_ALT0>;
 311                         };
 312                         spi1_gpio16: spi1_gpio16 {
 313                                 brcm,pins = <16 17 18 19 20 21>;
 314                                 brcm,function = <BCM2835_FSEL_ALT4>;
 315                         };
 316                         spi2_gpio40: spi2_gpio40 {
 317                                 brcm,pins = <40 41 42 43 44 45>;
 318                                 brcm,function = <BCM2835_FSEL_ALT4>;
 319                         };
 320
 321                         uart0_gpio14: uart0_gpio14 {
 322                                 brcm,pins = <14 15>;
 323                                 brcm,function = <BCM2835_FSEL_ALT0>;
 324                         };
 325                         /* Separate from the uart0_gpio14 group
 326                          * because it conflicts with spi1_gpio16, and
 327                          * people often run uart0 on the two pins
 328                          * without flow control.
 329                          */
 330                         uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
 331                                 brcm,pins = <16 17>;
 332                                 brcm,function = <BCM2835_FSEL_ALT3>;
 333                         };
 334                         uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
 335                                 brcm,pins = <30 31>;
 336                                 brcm,function = <BCM2835_FSEL_ALT3>;
 337                         };
 338                         uart0_gpio32: uart0_gpio32 {
 339                                 brcm,pins = <32 33>;
 340                                 brcm,function = <BCM2835_FSEL_ALT3>;
 341                         };
 342                         uart0_gpio36: uart0_gpio36 {
 343                                 brcm,pins = <36 37>;
 344                                 brcm,function = <BCM2835_FSEL_ALT2>;
 345                         };
 346                         uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
 347                                 brcm,pins = <38 39>;
 348                                 brcm,function = <BCM2835_FSEL_ALT2>;
 349                         };
 350
 351                         uart1_gpio14: uart1_gpio14 {
 352                                 brcm,pins = <14 15>;
 353                                 brcm,function = <BCM2835_FSEL_ALT5>;
 354                         };
 355                         uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
 356                                 brcm,pins = <16 17>;
 357                                 brcm,function = <BCM2835_FSEL_ALT5>;
 358                         };
 359                         uart1_gpio32: uart1_gpio32 {
 360                                 brcm,pins = <32 33>;
 361                                 brcm,function = <BCM2835_FSEL_ALT5>;
 362                         };
 363                         uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
 364                                 brcm,pins = <30 31>;
 365                                 brcm,function = <BCM2835_FSEL_ALT5>;
 366                         };
 367                         uart1_gpio40: uart1_gpio40 {
 368                                 brcm,pins = <40 41>;
 369                                 brcm,function = <BCM2835_FSEL_ALT5>;
 370                         };
 371                         uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
 372                                 brcm,pins = <42 43>;
 373                                 brcm,function = <BCM2835_FSEL_ALT5>;
 374                         };
 375                 };
 376
 377                 uart0: serial@7e201000 {
 378                         compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
 379                         reg = <0x7e201000 0x1000>;
 380                         interrupts = <2 25>;
 381                         clocks = <&clocks BCM2835_CLOCK_UART>,
 382                                  <&clocks BCM2835_CLOCK_VPU>;
 383                         clock-names = "uartclk", "apb_pclk";
 384                         arm,primecell-periphid = <0x00241011>;
 385                 };
 386
 387                 sdhost: mmc@7e202000 {
 388                         compatible = "brcm,bcm2835-sdhost";
 389                         reg = <0x7e202000 0x100>;
 390                         interrupts = <2 24>;
 391                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 392                         dmas = <&dma 13>;
 393                         dma-names = "rx-tx";
 394                         status = "disabled";
 395                 };
 396
 397                 i2s: i2s@7e203000 {
 398                         compatible = "brcm,bcm2835-i2s";
 399                         reg = <0x7e203000 0x20>,
 400                               <0x7e101098 0x02>;
 401
 402                         dmas = <&dma 2>,
 403                                <&dma 3>;
 404                         dma-names = "tx", "rx";
 405                         status = "disabled";
 406                 };
 407
 408                 spi: spi@7e204000 {
 409                         compatible = "brcm,bcm2835-spi";
 410                         reg = <0x7e204000 0x1000>;
 411                         interrupts = <2 22>;
 412                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         status = "disabled";
 416                 };
 417
 418                 i2c0: i2c@7e205000 {
 419                         compatible = "brcm,bcm2835-i2c";
 420                         reg = <0x7e205000 0x1000>;
 421                         interrupts = <2 21>;
 422                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 423                         #address-cells = <1>;
 424                         #size-cells = <0>;
 425                         status = "disabled";
 426                 };
 427
 428                 pixelvalve@7e206000 {
 429                         compatible = "brcm,bcm2835-pixelvalve0";
 430                         reg = <0x7e206000 0x100>;
 431                         interrupts = <2 13>; /* pwa0 */
 432                 };
 433
 434                 pixelvalve@7e207000 {
 435                         compatible = "brcm,bcm2835-pixelvalve1";
 436                         reg = <0x7e207000 0x100>;
 437                         interrupts = <2 14>; /* pwa1 */
 438                 };
 439
 440                 dsi0: dsi@7e209000 {
 441                         compatible = "brcm,bcm2835-dsi0";
 442                         reg = <0x7e209000 0x78>;
 443                         interrupts = <2 4>;
 444                         #address-cells = <1>;
 445                         #size-cells = <0>;
 446                         #clock-cells = <1>;
 447
 448                         clocks = <&clocks BCM2835_PLLA_DSI0>,
 449                                  <&clocks BCM2835_CLOCK_DSI0E>,
 450                                  <&clocks BCM2835_CLOCK_DSI0P>;
 451                         clock-names = "phy", "escape", "pixel";
 452
 453                         clock-output-names = "dsi0_byte",
 454                                              "dsi0_ddr2",
 455                                              "dsi0_ddr";
 456
 457                 };
 458
 459                 thermal: thermal@7e212000 {
 460                         compatible = "brcm,bcm2835-thermal";
 461                         reg = <0x7e212000 0x8>;
 462                         clocks = <&clocks BCM2835_CLOCK_TSENS>;
 463                         #thermal-sensor-cells = <0>;
 464                         status = "disabled";
 465                 };
 466
 467                 aux: aux@0x7e215000 {
 468                         compatible = "brcm,bcm2835-aux";
 469                         #clock-cells = <1>;
 470                         reg = <0x7e215000 0x8>;
 471                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 472                 };
 473
 474                 uart1: serial@7e215040 {
 475                         compatible = "brcm,bcm2835-aux-uart";
 476                         reg = <0x7e215040 0x40>;
 477                         interrupts = <1 29>;
 478                         clocks = <&aux BCM2835_AUX_CLOCK_UART>;
 479                         status = "disabled";
 480                 };
 481
 482                 spi1: spi@7e215080 {
 483                         compatible = "brcm,bcm2835-aux-spi";
 484                         reg = <0x7e215080 0x40>;
 485                         interrupts = <1 29>;
 486                         clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
 487                         #address-cells = <1>;
 488                         #size-cells = <0>;
 489                         status = "disabled";
 490                 };
 491
 492                 spi2: spi@7e2150c0 {
 493                         compatible = "brcm,bcm2835-aux-spi";
 494                         reg = <0x7e2150c0 0x40>;
 495                         interrupts = <1 29>;
 496                         clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
 497                         #address-cells = <1>;
 498                         #size-cells = <0>;
 499                         status = "disabled";
 500                 };
 501
 502                 pwm: pwm@7e20c000 {
 503                         compatible = "brcm,bcm2835-pwm";
 504                         reg = <0x7e20c000 0x28>;
 505                         clocks = <&clocks BCM2835_CLOCK_PWM>;
 506                         assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
 507                         assigned-clock-rates = <10000000>;
 508                         #pwm-cells = <2>;
 509                         status = "disabled";
 510                 };
 511
 512                 sdhci: sdhci@7e300000 {
 513                         compatible = "brcm,bcm2835-sdhci";
 514                         reg = <0x7e300000 0x100>;
 515                         interrupts = <2 30>;
 516                         clocks = <&clocks BCM2835_CLOCK_EMMC>;
 517                         status = "disabled";
 518                 };
 519
 520                 hvs@7e400000 {
 521                         compatible = "brcm,bcm2835-hvs";
 522                         reg = <0x7e400000 0x6000>;
 523                         interrupts = <2 1>;
 524                 };
 525
 526                 dsi1: dsi@7e700000 {
 527                         compatible = "brcm,bcm2835-dsi1";
 528                         reg = <0x7e700000 0x8c>;
 529                         interrupts = <2 12>;
 530                         #address-cells = <1>;
 531                         #size-cells = <0>;
 532                         #clock-cells = <1>;
 533
 534                         clocks = <&clocks BCM2835_PLLD_DSI1>,
 535                                  <&clocks BCM2835_CLOCK_DSI1E>,
 536                                  <&clocks BCM2835_CLOCK_DSI1P>;
 537                         clock-names = "phy", "escape", "pixel";
 538
 539                         clock-output-names = "dsi1_byte",
 540                                              "dsi1_ddr2",
 541                                              "dsi1_ddr";
 542
 543                         status = "disabled";
 544                 };
 545
 546                 i2c1: i2c@7e804000 {
 547                         compatible = "brcm,bcm2835-i2c";
 548                         reg = <0x7e804000 0x1000>;
 549                         interrupts = <2 21>;
 550                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 551                         #address-cells = <1>;
 552                         #size-cells = <0>;
 553                         status = "disabled";
 554                 };
 555
 556                 i2c2: i2c@7e805000 {
 557                         compatible = "brcm,bcm2835-i2c";
 558                         reg = <0x7e805000 0x1000>;
 559                         interrupts = <2 21>;
 560                         clocks = <&clocks BCM2835_CLOCK_VPU>;
 561                         #address-cells = <1>;
 562                         #size-cells = <0>;
 563                         status = "disabled";
 564                 };
 565
 566                 vec: vec@7e806000 {
 567                         compatible = "brcm,bcm2835-vec";
 568                         reg = <0x7e806000 0x1000>;
 569                         clocks = <&clocks BCM2835_CLOCK_VEC>;
 570                         interrupts = <2 27>;
 571                         status = "disabled";
 572                 };
 573
 574                 pixelvalve@7e807000 {
 575                         compatible = "brcm,bcm2835-pixelvalve2";
 576                         reg = <0x7e807000 0x100>;
 577                         interrupts = <2 10>; /* pixelvalve */
 578                 };
 579
 580                 hdmi: hdmi@7e902000 {
 581                         compatible = "brcm,bcm2835-hdmi";
 582                         reg = <0x7e902000 0x600>,
 583                               <0x7e808000 0x100>;
 584                         interrupts = <2 8>, <2 9>;
 585                         ddc = <&i2c2>;
 586                         clocks = <&clocks BCM2835_PLLH_PIX>,
 587                                  <&clocks BCM2835_CLOCK_HSM>;
 588                         clock-names = "pixel", "hdmi";
 589                         dmas = <&dma 17>;
 590                         dma-names = "audio-rx";
 591                         status = "disabled";
 592                 };
 593
 594                 usb: usb@7e980000 {
 595                         compatible = "brcm,bcm2835-usb";
 596                         reg = <0x7e980000 0x10000>;
 597                         interrupts = <1 9>;
 598                         #address-cells = <1>;
 599                         #size-cells = <0>;
 600                         clocks = <&clk_usb>;
 601                         clock-names = "otg";
 602                         phys = <&usbphy>;
 603                         phy-names = "usb2-phy";
 604                 };
 605
 606                 v3d: v3d@7ec00000 {
 607                         compatible = "brcm,bcm2835-v3d";
 608                         reg = <0x7ec00000 0x1000>;
 609                         interrupts = <1 10>;
 610                 };
 611
 612                 vc4: gpu {
 613                         compatible = "brcm,bcm2835-vc4";
 614                 };
 615         };
 616
 617         clocks {
 618                 compatible = "simple-bus";
 619                 #address-cells = <1>;
 620                 #size-cells = <0>;
 621
 622                 /* The oscillator is the root of the clock tree. */
 623                 clk_osc: clock@3 {
 624                         compatible = "fixed-clock";
 625                         reg = <3>;
 626                         #clock-cells = <0>;
 627                         clock-output-names = "osc";
 628                         clock-frequency = <19200000>;
 629                 };
 630
 631                 clk_usb: clock@4 {
 632                         compatible = "fixed-clock";
 633                         reg = <4>;
 634                         #clock-cells = <0>;
 635                         clock-output-names = "otg";
 636                         clock-frequency = <480000000>;
 637                 };
 638         };
 639
 640         usbphy: phy {
 641                 compatible = "usb-nop-xceiv";
 642         };
 643 };