arch/arm/boot/dts/bcm-nsp.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34 #include <dt-bindings/interrupt-controller/irq.h>
  35 #include <dt-bindings/clock/bcm-nsp.h>
  36
  37 #include "skeleton.dtsi"
  38
  39 / {
  40         compatible = "brcm,nsp";
  41         model = "Broadcom Northstar Plus SoC";
  42         interrupt-parent = <&gic>;
  43
  44         cpus {
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 cpu0: cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a9";
  51                         next-level-cache = <&L2>;
  52                         reg = <0x0>;
  53                 };
  54
  55                 cpu1: cpu@1 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a9";
  58                         next-level-cache = <&L2>;
  59                         enable-method = "brcm,bcm-nsp-smp";
  60                         secondary-boot-reg = <0xffff0fec>;
  61                         reg = <0x1>;
  62                 };
  63         };
  64
  65         pmu {
  66                 compatible = "arm,cortex-a9-pmu";
  67                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
  68                               GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
  69                 interrupt-affinity = <&cpu0>, <&cpu1>;
  70         };
  71
  72         mpcore {
  73                 compatible = "simple-bus";
  74                 ranges = <0x00000000 0x19000000 0x00023000>;
  75                 #address-cells = <1>;
  76                 #size-cells = <1>;
  77
  78                 a9pll: arm_clk@0 {
  79                         #clock-cells = <0>;
  80                         compatible = "brcm,nsp-armpll";
  81                         clocks = <&osc>;
  82                         reg = <0x00000 0x1000>;
  83                 };
  84
  85                 timer@20200 {
  86                         compatible = "arm,cortex-a9-global-timer";
  87                         reg = <0x20200 0x100>;
  88                         interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
  89                         clocks = <&periph_clk>;
  90                 };
  91
  92                 twd-timer@20600 {
  93                         compatible = "arm,cortex-a9-twd-timer";
  94                         reg = <0x20600 0x20>;
  95                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  96                                                   IRQ_TYPE_EDGE_RISING)>;
  97                         clocks = <&periph_clk>;
  98                 };
  99
 100                 twd-watchdog@20620 {
 101                         compatible = "arm,cortex-a9-twd-wdt";
 102                         reg = <0x20620 0x20>;
 103                         interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 104                                                   IRQ_TYPE_LEVEL_HIGH)>;
 105                         clocks = <&periph_clk>;
 106                 };
 107
 108                 gic: interrupt-controller@21000 {
 109                         compatible = "arm,cortex-a9-gic";
 110                         #interrupt-cells = <3>;
 111                         #address-cells = <0>;
 112                         interrupt-controller;
 113                         reg = <0x21000 0x1000>,
 114                               <0x20100 0x100>;
 115                 };
 116
 117                 L2: l2-cache {
 118                         compatible = "arm,pl310-cache";
 119                         reg = <0x22000 0x1000>;
 120                         cache-unified;
 121                         cache-level = <2>;
 122                 };
 123         };
 124
 125         clocks {
 126                 #address-cells = <1>;
 127                 #size-cells = <1>;
 128                 ranges;
 129
 130                 osc: oscillator {
 131                         #clock-cells = <0>;
 132                         compatible = "fixed-clock";
 133                         clock-frequency = <25000000>;
 134                 };
 135
 136                 iprocmed: iprocmed {
 137                         #clock-cells = <0>;
 138                         compatible = "fixed-factor-clock";
 139                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 140                         clock-div = <2>;
 141                         clock-mult = <1>;
 142                 };
 143
 144                 iprocslow: iprocslow {
 145                         #clock-cells = <0>;
 146                         compatible = "fixed-factor-clock";
 147                         clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
 148                         clock-div = <4>;
 149                         clock-mult = <1>;
 150                 };
 151
 152                 periph_clk: periph_clk {
 153                         #clock-cells = <0>;
 154                         compatible = "fixed-factor-clock";
 155                         clocks = <&a9pll>;
 156                         clock-div = <2>;
 157                         clock-mult = <1>;
 158                 };
 159         };
 160
 161         axi {
 162                 compatible = "simple-bus";
 163                 ranges = <0x00000000 0x18000000 0x0011c40c>;
 164                 #address-cells = <1>;
 165                 #size-cells = <1>;
 166
 167                 gpioa: gpio@20 {
 168                         compatible = "brcm,nsp-gpio-a";
 169                         reg = <0x0020 0x70>,
 170                               <0x3f1c4 0x1c>;
 171                         #gpio-cells = <2>;
 172                         gpio-controller;
 173                         ngpios = <32>;
 174                         interrupt-controller;
 175                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 176                         gpio-ranges = <&pinctrl 0 0 32>;
 177                 };
 178
 179                 uart0: serial@300 {
 180                         compatible = "ns16550a";
 181                         reg = <0x0300 0x100>;
 182                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 183                         clocks = <&osc>;
 184                         status = "disabled";
 185                 };
 186
 187                 uart1: serial@400 {
 188                         compatible = "ns16550a";
 189                         reg = <0x0400 0x100>;
 190                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 191                         clocks = <&osc>;
 192                         status = "disabled";
 193                 };
 194
 195                 dma@20000 {
 196                         compatible = "arm,pl330", "arm,primecell";
 197                         reg = <0x20000 0x1000>;
 198                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 201                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 202                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 203                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 204                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 206                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 207                         clocks = <&iprocslow>;
 208                         clock-names = "apb_pclk";
 209                         #dma-cells = <1>;
 210                 };
 211
 212                 sdio: sdhci@21000 {
 213                         compatible = "brcm,sdhci-iproc-cygnus";
 214                         reg = <0x21000 0x100>;
 215                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 216                         sdhci,auto-cmd12;
 217                         clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
 218                         dma-coherent;
 219                         status = "disabled";
 220                 };
 221
 222                 amac0: ethernet@22000 {
 223                         compatible = "brcm,nsp-amac";
 224                         reg = <0x022000 0x1000>,
 225                               <0x110000 0x1000>;
 226                         reg-names = "amac_base", "idm_base";
 227                         interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
 228                         dma-coherent;
 229                         status = "disabled";
 230                 };
 231
 232                 amac1: ethernet@23000 {
 233                         compatible = "brcm,nsp-amac";
 234                         reg = <0x023000 0x1000>,
 235                               <0x111000 0x1000>;
 236                         reg-names = "amac_base", "idm_base";
 237                         interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 238                         dma-coherent;
 239                         status = "disabled";
 240                 };
 241
 242                 amac2: ethernet@24000 {
 243                         compatible = "brcm,nsp-amac";
 244                         reg = <0x024000 0x1000>,
 245                               <0x112000 0x1000>;
 246                         reg-names = "amac_base", "idm_base";
 247                         interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 248                         dma-coherent;
 249                         status = "disabled";
 250                 };
 251
 252                 mailbox: mailbox@25000 {
 253                         compatible = "brcm,iproc-fa2-mbox";
 254                         reg = <0x25000 0x445>;
 255                         interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
 256                         #mbox-cells = <1>;
 257                         brcm,rx-status-len = <32>;
 258                         brcm,use-bcm-hdr;
 259                         dma-coherent;
 260                 };
 261
 262                 nand: nand@26000 {
 263                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 264                         reg = <0x026000 0x600>,
 265                               <0x11b408 0x600>,
 266                               <0x026f00 0x20>;
 267                         reg-names = "nand", "iproc-idm", "iproc-ext";
 268                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 269
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272
 273                         brcm,nand-has-wp;
 274                 };
 275
 276                 qspi: spi@27200 {
 277                         compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
 278                         reg = <0x027200 0x184>,
 279                               <0x027000 0x124>,
 280                               <0x11c408 0x004>,
 281                               <0x0273a0 0x01c>;
 282                         reg-names = "mspi", "bspi", "intr_regs",
 283                                     "intr_status_reg";
 284                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
 286                                      <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 287                                      <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
 288                                      <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 289                                      <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 290                                      <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 291                         interrupt-names = "spi_lr_fullness_reached",
 292                                           "spi_lr_session_aborted",
 293                                           "spi_lr_impatient",
 294                                           "spi_lr_session_done",
 295                                           "spi_lr_overhead",
 296                                           "mspi_done",
 297                                           "mspi_halted";
 298                         clocks = <&iprocmed>;
 299                         clock-names = "iprocmed";
 300                         num-cs = <2>;
 301                         #address-cells = <1>;
 302                         #size-cells = <0>;
 303                 };
 304
 305                 xhci: usb@29000 {
 306                         compatible = "generic-xhci";
 307                         reg = <0x29000 0x1000>;
 308                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 309                         phys = <&usb3_phy>;
 310                         phy-names = "usb3-phy";
 311                         dma-coherent;
 312                         status = "disabled";
 313                 };
 314
 315                 ehci0: usb@2a000 {
 316                         compatible = "generic-ehci";
 317                         reg = <0x2a000 0x100>;
 318                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 319                         dma-coherent;
 320                         status = "disabled";
 321                 };
 322
 323                 ohci0: usb@2b000 {
 324                         compatible = "generic-ohci";
 325                         reg = <0x2b000 0x100>;
 326                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 327                         dma-coherent;
 328                         status = "disabled";
 329                 };
 330
 331                 crypto@2f000 {
 332                         compatible = "brcm,spum-nsp-crypto";
 333                         reg = <0x2f000 0x900>;
 334                         mboxes = <&mailbox 0>;
 335                 };
 336
 337                 gpiob: gpio@30000 {
 338                         compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
 339                         reg = <0x30000 0x50>;
 340                         #gpio-cells = <2>;
 341                         gpio-controller;
 342                         ngpios = <4>;
 343                         interrupt-controller;
 344                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 345                 };
 346
 347                 pwm: pwm@31000 {
 348                         compatible = "brcm,iproc-pwm";
 349                         reg = <0x31000 0x28>;
 350                         clocks = <&osc>;
 351                         #pwm-cells = <3>;
 352                         status = "disabled";
 353                 };
 354
 355                 rng: rng@33000 {
 356                         compatible = "brcm,bcm-nsp-rng";
 357                         reg = <0x33000 0x14>;
 358                 };
 359
 360                 ccbtimer0: timer@34000 {
 361                         compatible = "arm,sp804";
 362                         reg = <0x34000 0x1000>;
 363                         interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 364                                      <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 365                         clocks = <&iprocslow>;
 366                         clock-names = "apb_pclk";
 367                 };
 368
 369                 ccbtimer1: timer@35000 {
 370                         compatible = "arm,sp804";
 371                         reg = <0x35000 0x1000>;
 372                         interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 373                                      <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 374                         clocks = <&iprocslow>;
 375                         clock-names = "apb_pclk";
 376                 };
 377
 378                 srab: srab@36000 {
 379                         compatible = "brcm,nsp-srab";
 380                         reg = <0x36000 0x1000>,
 381                               <0x3f308 0x8>,
 382                               <0x3f410 0xc>;
 383                         reg-names = "srab", "mux_config", "sgmii";
 384                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 385                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 386                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 387                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 388                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 389                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 390                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 391                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 392                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 393                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 394                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
 395                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
 396                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 397                         interrupt-names = "link_state_p0",
 398                                           "link_state_p1",
 399                                           "link_state_p2",
 400                                           "link_state_p3",
 401                                           "link_state_p4",
 402                                           "link_state_p5",
 403                                           "link_state_p7",
 404                                           "link_state_p8",
 405                                           "phy",
 406                                           "ts",
 407                                           "imp_sleep_timer_p5",
 408                                           "imp_sleep_timer_p7",
 409                                           "imp_sleep_timer_p8";
 410                         #address-cells = <1>;
 411                         #size-cells = <0>;
 412
 413                         status = "disabled";
 414
 415                         /* ports are defined in board DTS */
 416                 };
 417
 418                 i2c0: i2c@38000 {
 419                         compatible = "brcm,iproc-i2c";
 420                         reg = <0x38000 0x50>;
 421                         #address-cells = <1>;
 422                         #size-cells = <0>;
 423                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 424                         clock-frequency = <100000>;
 425                         dma-coherent;
 426                         status = "disabled";
 427                 };
 428
 429                 watchdog@39000 {
 430                         compatible = "arm,sp805", "arm,primecell";
 431                         reg = <0x39000 0x1000>;
 432                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 433                         clocks = <&iprocslow>, <&iprocslow>;
 434                         clock-names = "wdogclk", "apb_pclk";
 435                 };
 436
 437                 lcpll0: lcpll0@3f100 {
 438                         #clock-cells = <1>;
 439                         compatible = "brcm,nsp-lcpll0";
 440                         reg = <0x3f100 0x14>;
 441                         clocks = <&osc>;
 442                         clock-output-names = "lcpll0", "pcie_phy", "sdio",
 443                                              "ddr_phy";
 444                 };
 445
 446                 genpll: genpll@3f140 {
 447                         #clock-cells = <1>;
 448                         compatible = "brcm,nsp-genpll";
 449                         reg = <0x3f140 0x24>;
 450                         clocks = <&osc>;
 451                         clock-output-names = "genpll", "phy", "ethernetclk",
 452                                              "usbclk", "iprocfast", "sata1",
 453                                              "sata2";
 454                 };
 455
 456                 pinctrl: pinctrl@3f1c0 {
 457                         compatible = "brcm,nsp-pinmux";
 458                         reg = <0x3f1c0 0x04>,
 459                               <0x30028 0x04>,
 460                               <0x3f408 0x04>;
 461                 };
 462
 463                 thermal: thermal@3f2c0 {
 464                         compatible = "brcm,ns-thermal";
 465                         reg = <0x3f2c0 0x10>;
 466                         #thermal-sensor-cells = <0>;
 467                 };
 468
 469                 sata_phy: sata_phy@40100 {
 470                         compatible = "brcm,iproc-nsp-sata-phy";
 471                         reg = <0x40100 0x340>;
 472                         reg-names = "phy";
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475
 476                         sata_phy0: sata-phy@0 {
 477                                 reg = <0>;
 478                                 #phy-cells = <0>;
 479                                 status = "disabled";
 480                         };
 481
 482                         sata_phy1: sata-phy@1 {
 483                                 reg = <1>;
 484                                 #phy-cells = <0>;
 485                                 status = "disabled";
 486                         };
 487                 };
 488
 489                 sata: ahci@41000 {
 490                         compatible = "brcm,bcm-nsp-ahci";
 491                         reg-names = "ahci", "top-ctrl";
 492                         reg = <0x41000 0x1000>, <0x40020 0x1c>;
 493                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
 494                         #address-cells = <1>;
 495                         #size-cells = <0>;
 496                         dma-coherent;
 497                         status = "disabled";
 498
 499                         sata0: sata-port@0 {
 500                                 reg = <0>;
 501                                 phys = <&sata_phy0>;
 502                                 phy-names = "sata-phy";
 503                         };
 504
 505                         sata1: sata-port@1 {
 506                                 reg = <1>;
 507                                 phys = <&sata_phy1>;
 508                                 phy-names = "sata-phy";
 509                         };
 510                 };
 511
 512                 usb3_phy: usb3-phy@104000 {
 513                         compatible = "brcm,ns-bx-usb3-phy";
 514                         reg = <0x104000 0x1000>,
 515                               <0x032000 0x1000>;
 516                         reg-names = "dmp", "ccb-mii";
 517                         #phy-cells = <0>;
 518                         status = "disabled";
 519                 };
 520         };
 521
 522         pcie0: pcie@18012000 {
 523                 compatible = "brcm,iproc-pcie";
 524                 reg = <0x18012000 0x1000>;
 525
 526                 #interrupt-cells = <1>;
 527                 interrupt-map-mask = <0 0 0 0>;
 528                 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 529
 530                 linux,pci-domain = <0>;
 531
 532                 bus-range = <0x00 0xff>;
 533
 534                 #address-cells = <3>;
 535                 #size-cells = <2>;
 536                 device_type = "pci";
 537
 538                 /* Note: The HW does not support I/O resources.  So,
 539                  * only the memory resource range is being specified.
 540                  */
 541                 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
 542
 543                 dma-coherent;
 544                 status = "disabled";
 545
 546                 msi-parent = <&msi0>;
 547                 msi0: msi-controller {
 548                         compatible = "brcm,iproc-msi";
 549                         msi-controller;
 550                         interrupt-parent = <&gic>;
 551                         interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
 552                                      <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
 553                                      <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
 554                                      <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
 555                         brcm,pcie-msi-inten;
 556                 };
 557         };
 558
 559         pcie1: pcie@18013000 {
 560                 compatible = "brcm,iproc-pcie";
 561                 reg = <0x18013000 0x1000>;
 562
 563                 #interrupt-cells = <1>;
 564                 interrupt-map-mask = <0 0 0 0>;
 565                 interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
 566
 567                 linux,pci-domain = <1>;
 568
 569                 bus-range = <0x00 0xff>;
 570
 571                 #address-cells = <3>;
 572                 #size-cells = <2>;
 573                 device_type = "pci";
 574
 575                 /* Note: The HW does not support I/O resources.  So,
 576                  * only the memory resource range is being specified.
 577                  */
 578                 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
 579
 580                 dma-coherent;
 581                 status = "disabled";
 582
 583                 msi-parent = <&msi1>;
 584                 msi1: msi-controller {
 585                         compatible = "brcm,iproc-msi";
 586                         msi-controller;
 587                         interrupt-parent = <&gic>;
 588                         interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
 589                                      <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
 590                                      <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
 591                                      <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 592                         brcm,pcie-msi-inten;
 593                 };
 594         };
 595
 596         pcie2: pcie@18014000 {
 597                 compatible = "brcm,iproc-pcie";
 598                 reg = <0x18014000 0x1000>;
 599
 600                 #interrupt-cells = <1>;
 601                 interrupt-map-mask = <0 0 0 0>;
 602                 interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
 603
 604                 linux,pci-domain = <2>;
 605
 606                 bus-range = <0x00 0xff>;
 607
 608                 #address-cells = <3>;
 609                 #size-cells = <2>;
 610                 device_type = "pci";
 611
 612                 /* Note: The HW does not support I/O resources.  So,
 613                  * only the memory resource range is being specified.
 614                  */
 615                 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
 616
 617                 dma-coherent;
 618                 status = "disabled";
 619
 620                 msi-parent = <&msi2>;
 621                 msi2: msi-controller {
 622                         compatible = "brcm,iproc-msi";
 623                         msi-controller;
 624                         interrupt-parent = <&gic>;
 625                         interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
 626                                      <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
 627                                      <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
 628                                      <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
 629                         brcm,pcie-msi-inten;
 630                 };
 631         };
 632
 633         thermal-zones {
 634                 cpu-thermal {
 635                         polling-delay-passive = <0>;
 636                         polling-delay = <1000>;
 637                         coefficients = <(-556) 418000>;
 638                         thermal-sensors = <&thermal>;
 639
 640                         trips {
 641                                 cpu-crit {
 642                                         temperature     = <125000>;
 643                                         hysteresis      = <0>;
 644                                         type            = "critical";
 645                                 };
 646                         };
 647
 648                         cooling-maps {
 649                         };
 650                 };
 651         };
 652 };