Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / atlas7.dtsi
1 /*
2  * DTS file for CSR SiRFatlas7 SoC
3  *
4  * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
5  *
6  * Licensed under GPLv2 or later.
7  */
8
9 / {
10         compatible = "sirf,atlas7";
11         #address-cells = <1>;
12         #size-cells = <1>;
13         interrupt-parent = <&gic>;
14         aliases {
15                 serial0 = &uart0;
16                 serial1 = &uart1;
17                 serial2 = &uart2;
18                 serial3 = &uart3;
19                 serial4 = &uart4;
20                 serial5 = &uart5;
21                 serial6 = &uart6;
22                 serial9 = &usp2;
23                 spi1 = &spi1;
24                 spi2 = &usp1;
25                 spi3 = &usp2;
26                 spi4 = &usp3;
27         };
28         cpus {
29                 #address-cells = <1>;
30                 #size-cells = <0>;
31
32                 cpu@0 {
33                         device_type = "cpu";
34                         compatible = "arm,cortex-a7";
35                         reg = <0>;
36                 };
37                 cpu@1 {
38                         device_type = "cpu";
39                         compatible = "arm,cortex-a7";
40                         reg = <1>;
41                 };
42         };
43
44         clocks {
45                 xinw {
46                         compatible = "fixed-clock";
47                         #clock-cells = <0>;
48                         clock-frequency = <32768>;
49                         clock-output-names = "xinw";
50                 };
51                 xin {
52                         compatible = "fixed-clock";
53                         #clock-cells = <0>;
54                         clock-frequency = <26000000>;
55                         clock-output-names = "xin";
56                 };
57         };
58
59         arm-pmu {
60                 compatible = "arm,cortex-a7-pmu";
61                 interrupts = <0 29 4>, <0 82 4>;
62         };
63
64         noc {
65                 compatible = "simple-bus";
66                 #address-cells = <1>;
67                 #size-cells = <1>;
68                 ranges = <0x10000000 0x10000000 0xc0000000>;
69
70                 gic: interrupt-controller@10301000 {
71                         compatible = "arm,cortex-a9-gic";
72                         interrupt-controller;
73                         #interrupt-cells = <3>;
74                         reg = <0x10301000 0x1000>,
75                              <0x10302000 0x0100>;
76                 };
77
78                 pmu_regulator: pmu_regulator@10E30020 {
79                         compatible = "sirf,atlas7-pmu-ldo";
80                         reg = <0x10E30020 0x4>;
81                         ldo: ldo {
82                                 regulator-name = "ldo";
83                         };
84                 };
85
86                 atlas7_codec: atlas7_codec@10E30000 {
87                         #sound-dai-cells = <0>;
88                         compatible = "sirf,atlas7-codec";
89                         reg = <0x10E30000 0x400>;
90                         clocks = <&car 62>;
91                         ldo-supply = <&ldo>;
92                 };
93
94                 atlas7_iacc: atlas7_iacc@10D01000 {
95                         #sound-dai-cells = <0>;
96                         compatible = "sirf,atlas7-iacc";
97                         reg = <0x10D01000 0x100>;
98                         dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>,
99                                 <&dmac3 3>, <&dmac3 9>;
100                         dma-names = "rx", "tx0", "tx1", "tx2", "tx3";
101                         clocks = <&car 62>;
102                 };
103
104                 ipc@13240000 {
105                         compatible = "sirf,atlas7-ipc";
106                         ranges = <0x13240000 0x13240000 0x00010000>;
107                         #address-cells = <1>;
108                         #size-cells = <1>;
109
110                         hwspinlock {
111                                 compatible = "sirf,hwspinlock";
112                                 reg = <0x13240000 0x00010000>;
113
114                                 num-spinlocks = <30>;
115                         };
116
117                         ns_m3_rproc@0 {
118                                 compatible = "sirf,ns2m30-rproc";
119                                 reg = <0x13240000 0x00010000>;
120                                 interrupts = <0 123 0>;
121                         };
122
123                         ns_m3_rproc@1 {
124                                 compatible = "sirf,ns2m31-rproc";
125                                 reg = <0x13240000 0x00010000>;
126                                 interrupts = <0 126 0>;
127                         };
128
129                         ns_kal_rproc@0 {
130                                 compatible = "sirf,ns2kal0-rproc";
131                                 reg = <0x13240000 0x00010000>;
132                                 interrupts = <0 124 0>;
133                         };
134
135                         ns_kal_rproc@1 {
136                                 compatible = "sirf,ns2kal1-rproc";
137                                 reg = <0x13240000 0x00010000>;
138                                 interrupts = <0 127 0>;
139                         };
140                 };
141
142                 pinctrl: ioc@18880000 {
143                         compatible = "sirf,atlas7-ioc";
144                         reg = <0x18880000 0x1000>,
145                                 <0x10E40000 0x1000>;
146
147                         audio_ac97_pmx: audio_ac97@0 {
148                                 audio_ac97 {
149                                         groups = "audio_ac97_grp";
150                                         function = "audio_ac97";
151                                 };
152                         };
153
154                         audio_func_dbg_pmx: audio_func_dbg@0 {
155                                 audio_func_dbg {
156                                         groups = "audio_func_dbg_grp";
157                                         function = "audio_func_dbg";
158                                 };
159                         };
160
161                         audio_i2s_pmx: audio_i2s@0 {
162                                 audio_i2s {
163                                         groups = "audio_i2s_grp";
164                                         function = "audio_i2s";
165                                 };
166                         };
167
168                         audio_i2s_2ch_pmx: audio_i2s_2ch@0 {
169                                 audio_i2s_2ch {
170                                         groups = "audio_i2s_2ch_grp";
171                                         function = "audio_i2s_2ch";
172                                 };
173                         };
174
175                         audio_i2s_extclk_pmx: audio_i2s_extclk@0 {
176                                 audio_i2s_extclk {
177                                         groups = "audio_i2s_extclk_grp";
178                                         function = "audio_i2s_extclk";
179                                 };
180                         };
181
182                         audio_uart0_pmx: audio_uart0@0 {
183                                 audio_uart0 {
184                                         groups = "audio_uart0_grp";
185                                         function = "audio_uart0";
186                                 };
187                         };
188
189                         audio_uart1_pmx: audio_uart1@0 {
190                                 audio_uart1 {
191                                         groups = "audio_uart1_grp";
192                                         function = "audio_uart1";
193                                 };
194                         };
195
196                         audio_uart2_pmx0: audio_uart2@0 {
197                                 audio_uart2_0 {
198                                         groups = "audio_uart2_grp0";
199                                         function = "audio_uart2_m0";
200                                 };
201                         };
202
203                         audio_uart2_pmx1: audio_uart2@1 {
204                                 audio_uart2_1 {
205                                         groups = "audio_uart2_grp1";
206                                         function = "audio_uart2_m1";
207                                 };
208                         };
209
210                         c_can_trnsvr_pmx: c_can_trnsvr@0 {
211                                 c_can_trnsvr {
212                                         groups = "c_can_trnsvr_grp";
213                                         function = "c_can_trnsvr";
214                                 };
215                         };
216
217                         c0_can_pmx0: c0_can@0 {
218                                 c0_can_0 {
219                                         groups = "c0_can_grp0";
220                                         function = "c0_can_m0";
221                                 };
222                         };
223
224                         c0_can_pmx1: c0_can@1 {
225                                 c0_can_1 {
226                                         groups = "c0_can_grp1";
227                                         function = "c0_can_m1";
228                                 };
229                         };
230
231                         c1_can_pmx0: c1_can@0 {
232                                 c1_can_0 {
233                                         groups = "c1_can_grp0";
234                                         function = "c1_can_m0";
235                                 };
236                         };
237
238                         c1_can_pmx1: c1_can@1 {
239                                 c1_can_1 {
240                                         groups = "c1_can_grp1";
241                                         function = "c1_can_m1";
242                                 };
243                         };
244
245                         c1_can_pmx2: c1_can@2 {
246                                 c1_can_2 {
247                                         groups = "c1_can_grp2";
248                                         function = "c1_can_m2";
249                                 };
250                         };
251
252                         ca_audio_lpc_pmx: ca_audio_lpc@0 {
253                                 ca_audio_lpc {
254                                         groups = "ca_audio_lpc_grp";
255                                         function = "ca_audio_lpc";
256                                 };
257                         };
258
259                         ca_bt_lpc_pmx: ca_bt_lpc@0 {
260                                 ca_bt_lpc {
261                                         groups = "ca_bt_lpc_grp";
262                                         function = "ca_bt_lpc";
263                                 };
264                         };
265
266                         ca_coex_pmx: ca_coex@0 {
267                                 ca_coex {
268                                         groups = "ca_coex_grp";
269                                         function = "ca_coex";
270                                 };
271                         };
272
273                         ca_curator_lpc_pmx: ca_curator_lpc@0 {
274                                 ca_curator_lpc {
275                                         groups = "ca_curator_lpc_grp";
276                                         function = "ca_curator_lpc";
277                                 };
278                         };
279
280                         ca_pcm_debug_pmx: ca_pcm_debug@0 {
281                                 ca_pcm_debug {
282                                         groups = "ca_pcm_debug_grp";
283                                         function = "ca_pcm_debug";
284                                 };
285                         };
286
287                         ca_pio_pmx: ca_pio@0 {
288                                 ca_pio {
289                                         groups = "ca_pio_grp";
290                                         function = "ca_pio";
291                                 };
292                         };
293
294                         ca_sdio_debug_pmx: ca_sdio_debug@0 {
295                                 ca_sdio_debug {
296                                         groups = "ca_sdio_debug_grp";
297                                         function = "ca_sdio_debug";
298                                 };
299                         };
300
301                         ca_spi_pmx: ca_spi@0 {
302                                 ca_spi {
303                                         groups = "ca_spi_grp";
304                                         function = "ca_spi";
305                                 };
306                         };
307
308                         ca_trb_pmx: ca_trb@0 {
309                                 ca_trb {
310                                         groups = "ca_trb_grp";
311                                         function = "ca_trb";
312                                 };
313                         };
314
315                         ca_uart_debug_pmx: ca_uart_debug@0 {
316                                 ca_uart_debug {
317                                         groups = "ca_uart_debug_grp";
318                                         function = "ca_uart_debug";
319                                 };
320                         };
321
322                         clkc_pmx0: clkc@0 {
323                                 clkc_0 {
324                                         groups = "clkc_grp0";
325                                         function = "clkc_m0";
326                                 };
327                         };
328
329                         clkc_pmx1: clkc@1 {
330                                 clkc_1 {
331                                         groups = "clkc_grp1";
332                                         function = "clkc_m1";
333                                 };
334                         };
335
336                         gn_gnss_i2c_pmx: gn_gnss_i2c@0 {
337                                 gn_gnss_i2c {
338                                         groups = "gn_gnss_i2c_grp";
339                                         function = "gn_gnss_i2c";
340                                 };
341                         };
342
343                         gn_gnss_uart_nopause_pmx: gn_gnss_uart_nopause@0 {
344                                 gn_gnss_uart_nopause {
345                                         groups = "gn_gnss_uart_nopause_grp";
346                                         function = "gn_gnss_uart_nopause";
347                                 };
348                         };
349
350                         gn_gnss_uart_pmx: gn_gnss_uart@0 {
351                                 gn_gnss_uart {
352                                         groups = "gn_gnss_uart_grp";
353                                         function = "gn_gnss_uart";
354                                 };
355                         };
356
357                         gn_trg_spi_pmx0: gn_trg_spi@0 {
358                                 gn_trg_spi_0 {
359                                         groups = "gn_trg_spi_grp0";
360                                         function = "gn_trg_spi_m0";
361                                 };
362                         };
363
364                         gn_trg_spi_pmx1: gn_trg_spi@1 {
365                                 gn_trg_spi_1 {
366                                         groups = "gn_trg_spi_grp1";
367                                         function = "gn_trg_spi_m1";
368                                 };
369                         };
370
371                         cvbs_dbg_pmx: cvbs_dbg@0 {
372                                 cvbs_dbg {
373                                         groups = "cvbs_dbg_grp";
374                                         function = "cvbs_dbg";
375                                 };
376                         };
377
378                         cvbs_dbg_test_pmx0: cvbs_dbg_test@0 {
379                                 cvbs_dbg_test_0 {
380                                         groups = "cvbs_dbg_test_grp0";
381                                         function = "cvbs_dbg_test_m0";
382                                 };
383                         };
384
385                         cvbs_dbg_test_pmx1: cvbs_dbg_test@1 {
386                                 cvbs_dbg_test_1 {
387                                         groups = "cvbs_dbg_test_grp1";
388                                         function = "cvbs_dbg_test_m1";
389                                 };
390                         };
391
392                         cvbs_dbg_test_pmx2: cvbs_dbg_test@2 {
393                                 cvbs_dbg_test_2 {
394                                         groups = "cvbs_dbg_test_grp2";
395                                         function = "cvbs_dbg_test_m2";
396                                 };
397                         };
398
399                         cvbs_dbg_test_pmx3: cvbs_dbg_test@3 {
400                                 cvbs_dbg_test_3 {
401                                         groups = "cvbs_dbg_test_grp3";
402                                         function = "cvbs_dbg_test_m3";
403                                 };
404                         };
405
406                         cvbs_dbg_test_pmx4: cvbs_dbg_test@4 {
407                                 cvbs_dbg_test_4 {
408                                         groups = "cvbs_dbg_test_grp4";
409                                         function = "cvbs_dbg_test_m4";
410                                 };
411                         };
412
413                         cvbs_dbg_test_pmx5: cvbs_dbg_test@5 {
414                                 cvbs_dbg_test_5 {
415                                         groups = "cvbs_dbg_test_grp5";
416                                         function = "cvbs_dbg_test_m5";
417                                 };
418                         };
419
420                         cvbs_dbg_test_pmx6: cvbs_dbg_test@6 {
421                                 cvbs_dbg_test_6 {
422                                         groups = "cvbs_dbg_test_grp6";
423                                         function = "cvbs_dbg_test_m6";
424                                 };
425                         };
426
427                         cvbs_dbg_test_pmx7: cvbs_dbg_test@7 {
428                                 cvbs_dbg_test_7 {
429                                         groups = "cvbs_dbg_test_grp7";
430                                         function = "cvbs_dbg_test_m7";
431                                 };
432                         };
433
434                         cvbs_dbg_test_pmx8: cvbs_dbg_test@8 {
435                                 cvbs_dbg_test_8 {
436                                         groups = "cvbs_dbg_test_grp8";
437                                         function = "cvbs_dbg_test_m8";
438                                 };
439                         };
440
441                         cvbs_dbg_test_pmx9: cvbs_dbg_test@9 {
442                                 cvbs_dbg_test_9 {
443                                         groups = "cvbs_dbg_test_grp9";
444                                         function = "cvbs_dbg_test_m9";
445                                 };
446                         };
447
448                         cvbs_dbg_test_pmx10: cvbs_dbg_test@10 {
449                                 cvbs_dbg_test_10 {
450                                         groups = "cvbs_dbg_test_grp10";
451                                         function = "cvbs_dbg_test_m10";
452                                 };
453                         };
454
455                         cvbs_dbg_test_pmx11: cvbs_dbg_test@11 {
456                                 cvbs_dbg_test_11 {
457                                         groups = "cvbs_dbg_test_grp11";
458                                         function = "cvbs_dbg_test_m11";
459                                 };
460                         };
461
462                         cvbs_dbg_test_pmx12: cvbs_dbg_test@12 {
463                                 cvbs_dbg_test_12 {
464                                         groups = "cvbs_dbg_test_grp12";
465                                         function = "cvbs_dbg_test_m12";
466                                 };
467                         };
468
469                         cvbs_dbg_test_pmx13: cvbs_dbg_test@13 {
470                                 cvbs_dbg_test_13 {
471                                         groups = "cvbs_dbg_test_grp13";
472                                         function = "cvbs_dbg_test_m13";
473                                 };
474                         };
475
476                         cvbs_dbg_test_pmx14: cvbs_dbg_test@14 {
477                                 cvbs_dbg_test_14 {
478                                         groups = "cvbs_dbg_test_grp14";
479                                         function = "cvbs_dbg_test_m14";
480                                 };
481                         };
482
483                         cvbs_dbg_test_pmx15: cvbs_dbg_test@15 {
484                                 cvbs_dbg_test_15 {
485                                         groups = "cvbs_dbg_test_grp15";
486                                         function = "cvbs_dbg_test_m15";
487                                 };
488                         };
489
490                         gn_gnss_power_pmx: gn_gnss_power@0 {
491                                 gn_gnss_power {
492                                         groups = "gn_gnss_power_grp";
493                                         function = "gn_gnss_power";
494                                 };
495                         };
496
497                         gn_gnss_sw_status_pmx: gn_gnss_sw_status@0 {
498                                 gn_gnss_sw_status {
499                                         groups = "gn_gnss_sw_status_grp";
500                                         function = "gn_gnss_sw_status";
501                                 };
502                         };
503
504                         gn_gnss_eclk_pmx: gn_gnss_eclk@0 {
505                                 gn_gnss_eclk {
506                                         groups = "gn_gnss_eclk_grp";
507                                         function = "gn_gnss_eclk";
508                                 };
509                         };
510
511                         gn_gnss_irq1_pmx0: gn_gnss_irq1@0 {
512                                 gn_gnss_irq1_0 {
513                                         groups = "gn_gnss_irq1_grp0";
514                                         function = "gn_gnss_irq1_m0";
515                                 };
516                         };
517
518                         gn_gnss_irq2_pmx0: gn_gnss_irq2@0 {
519                                 gn_gnss_irq2_0 {
520                                         groups = "gn_gnss_irq2_grp0";
521                                         function = "gn_gnss_irq2_m0";
522                                 };
523                         };
524
525                         gn_gnss_tm_pmx: gn_gnss_tm@0 {
526                                 gn_gnss_tm {
527                                         groups = "gn_gnss_tm_grp";
528                                         function = "gn_gnss_tm";
529                                 };
530                         };
531
532                         gn_gnss_tsync_pmx: gn_gnss_tsync@0 {
533                                 gn_gnss_tsync {
534                                         groups = "gn_gnss_tsync_grp";
535                                         function = "gn_gnss_tsync";
536                                 };
537                         };
538
539                         gn_io_gnsssys_sw_cfg_pmx: gn_io_gnsssys_sw_cfg@0 {
540                                 gn_io_gnsssys_sw_cfg {
541                                         groups = "gn_io_gnsssys_sw_cfg_grp";
542                                         function = "gn_io_gnsssys_sw_cfg";
543                                 };
544                         };
545
546                         gn_trg_pmx0: gn_trg@0 {
547                                 gn_trg_0 {
548                                         groups = "gn_trg_grp0";
549                                         function = "gn_trg_m0";
550                                 };
551                         };
552
553                         gn_trg_pmx1: gn_trg@1 {
554                                 gn_trg_1 {
555                                         groups = "gn_trg_grp1";
556                                         function = "gn_trg_m1";
557                                 };
558                         };
559
560                         gn_trg_shutdown_pmx0: gn_trg_shutdown@0 {
561                                 gn_trg_shutdown_0 {
562                                         groups = "gn_trg_shutdown_grp0";
563                                         function = "gn_trg_shutdown_m0";
564                                 };
565                         };
566
567                         gn_trg_shutdown_pmx1: gn_trg_shutdown@1 {
568                                 gn_trg_shutdown_1 {
569                                         groups = "gn_trg_shutdown_grp1";
570                                         function = "gn_trg_shutdown_m1";
571                                 };
572                         };
573
574                         gn_trg_shutdown_pmx2: gn_trg_shutdown@2 {
575                                 gn_trg_shutdown_2 {
576                                         groups = "gn_trg_shutdown_grp2";
577                                         function = "gn_trg_shutdown_m2";
578                                 };
579                         };
580
581                         gn_trg_shutdown_pmx3: gn_trg_shutdown@3 {
582                                 gn_trg_shutdown_3 {
583                                         groups = "gn_trg_shutdown_grp3";
584                                         function = "gn_trg_shutdown_m3";
585                                 };
586                         };
587
588                         i2c0_pmx: i2c0@0 {
589                                 i2c0 {
590                                         groups = "i2c0_grp";
591                                         function = "i2c0";
592                                 };
593                         };
594
595                         i2c1_pmx: i2c1@0 {
596                                 i2c1 {
597                                         groups = "i2c1_grp";
598                                         function = "i2c1";
599                                 };
600                         };
601
602                         jtag_pmx0: jtag@0 {
603                                 jtag_0 {
604                                         groups = "jtag_grp0";
605                                         function = "jtag_m0";
606                                 };
607                         };
608
609                         ks_kas_spi_pmx0: ks_kas_spi@0 {
610                                 ks_kas_spi_0 {
611                                         groups = "ks_kas_spi_grp0";
612                                         function = "ks_kas_spi_m0";
613                                 };
614                         };
615
616                         ld_ldd_pmx: ld_ldd@0 {
617                                 ld_ldd {
618                                         groups = "ld_ldd_grp";
619                                         function = "ld_ldd";
620                                 };
621                         };
622
623                         ld_ldd_16bit_pmx: ld_ldd_16bit@0 {
624                                 ld_ldd_16bit {
625                                         groups = "ld_ldd_16bit_grp";
626                                         function = "ld_ldd_16bit";
627                                 };
628                         };
629
630                         ld_ldd_fck_pmx: ld_ldd_fck@0 {
631                                 ld_ldd_fck {
632                                         groups = "ld_ldd_fck_grp";
633                                         function = "ld_ldd_fck";
634                                 };
635                         };
636
637                         ld_ldd_lck_pmx: ld_ldd_lck@0 {
638                                 ld_ldd_lck {
639                                         groups = "ld_ldd_lck_grp";
640                                         function = "ld_ldd_lck";
641                                 };
642                         };
643
644                         lr_lcdrom_pmx: lr_lcdrom@0 {
645                                 lr_lcdrom {
646                                         groups = "lr_lcdrom_grp";
647                                         function = "lr_lcdrom";
648                                 };
649                         };
650
651                         lvds_analog_pmx: lvds_analog@0 {
652                                 lvds_analog {
653                                         groups = "lvds_analog_grp";
654                                         function = "lvds_analog";
655                                 };
656                         };
657
658                         nd_df_pmx: nd_df@0 {
659                                 nd_df {
660                                         groups = "nd_df_grp";
661                                         function = "nd_df";
662                                 };
663                         };
664
665                         nd_df_nowp_pmx: nd_df_nowp@0 {
666                                 nd_df_nowp {
667                                         groups = "nd_df_nowp_grp";
668                                         function = "nd_df_nowp";
669                                 };
670                         };
671
672                         ps_pmx: ps@0 {
673                                 ps {
674                                         groups = "ps_grp";
675                                         function = "ps";
676                                 };
677                         };
678
679                         pwc_core_on_pmx: pwc_core_on@0 {
680                                 pwc_core_on {
681                                         groups = "pwc_core_on_grp";
682                                         function = "pwc_core_on";
683                                 };
684                         };
685
686                         pwc_ext_on_pmx: pwc_ext_on@0 {
687                                 pwc_ext_on {
688                                         groups = "pwc_ext_on_grp";
689                                         function = "pwc_ext_on";
690                                 };
691                         };
692
693                         pwc_gpio3_clk_pmx: pwc_gpio3_clk@0 {
694                                 pwc_gpio3_clk {
695                                         groups = "pwc_gpio3_clk_grp";
696                                         function = "pwc_gpio3_clk";
697                                 };
698                         };
699
700                         pwc_io_on_pmx: pwc_io_on@0 {
701                                 pwc_io_on {
702                                         groups = "pwc_io_on_grp";
703                                         function = "pwc_io_on";
704                                 };
705                         };
706
707                         pwc_lowbatt_b_pmx0: pwc_lowbatt_b@0 {
708                                 pwc_lowbatt_b_0 {
709                                         groups = "pwc_lowbatt_b_grp0";
710                                         function = "pwc_lowbatt_b_m0";
711                                 };
712                         };
713
714                         pwc_mem_on_pmx: pwc_mem_on@0 {
715                                 pwc_mem_on {
716                                         groups = "pwc_mem_on_grp";
717                                         function = "pwc_mem_on";
718                                 };
719                         };
720
721                         pwc_on_key_b_pmx0: pwc_on_key_b@0 {
722                                 pwc_on_key_b_0 {
723                                         groups = "pwc_on_key_b_grp0";
724                                         function = "pwc_on_key_b_m0";
725                                 };
726                         };
727
728                         pwc_wakeup_src0_pmx: pwc_wakeup_src0@0 {
729                                 pwc_wakeup_src0 {
730                                         groups = "pwc_wakeup_src0_grp";
731                                         function = "pwc_wakeup_src0";
732                                 };
733                         };
734
735                         pwc_wakeup_src1_pmx: pwc_wakeup_src1@0 {
736                                 pwc_wakeup_src1 {
737                                         groups = "pwc_wakeup_src1_grp";
738                                         function = "pwc_wakeup_src1";
739                                 };
740                         };
741
742                         pwc_wakeup_src2_pmx: pwc_wakeup_src2@0 {
743                                 pwc_wakeup_src2 {
744                                         groups = "pwc_wakeup_src2_grp";
745                                         function = "pwc_wakeup_src2";
746                                 };
747                         };
748
749                         pwc_wakeup_src3_pmx: pwc_wakeup_src3@0 {
750                                 pwc_wakeup_src3 {
751                                         groups = "pwc_wakeup_src3_grp";
752                                         function = "pwc_wakeup_src3";
753                                 };
754                         };
755
756                         pw_cko0_pmx0: pw_cko0@0 {
757                                 pw_cko0_0 {
758                                         groups = "pw_cko0_grp0";
759                                         function = "pw_cko0_m0";
760                                 };
761                         };
762
763                         pw_cko0_pmx1: pw_cko0@1 {
764                                 pw_cko0_1 {
765                                         groups = "pw_cko0_grp1";
766                                         function = "pw_cko0_m1";
767                                 };
768                         };
769
770                         pw_cko0_pmx2: pw_cko0@2 {
771                                 pw_cko0_2 {
772                                         groups = "pw_cko0_grp2";
773                                         function = "pw_cko0_m2";
774                                 };
775                         };
776
777                         pw_cko1_pmx0: pw_cko1@0 {
778                                 pw_cko1_0 {
779                                         groups = "pw_cko1_grp0";
780                                         function = "pw_cko1_m0";
781                                 };
782                         };
783
784                         pw_cko1_pmx1: pw_cko1@1 {
785                                 pw_cko1_1 {
786                                         groups = "pw_cko1_grp1";
787                                         function = "pw_cko1_m1";
788                                 };
789                         };
790
791                         pw_i2s01_clk_pmx0: pw_i2s01_clk@0 {
792                                 pw_i2s01_clk_0 {
793                                         groups = "pw_i2s01_clk_grp0";
794                                         function = "pw_i2s01_clk_m0";
795                                 };
796                         };
797
798                         pw_i2s01_clk_pmx1: pw_i2s01_clk@1 {
799                                 pw_i2s01_clk_1 {
800                                         groups = "pw_i2s01_clk_grp1";
801                                         function = "pw_i2s01_clk_m1";
802                                 };
803                         };
804
805                         pw_pwm0_pmx: pw_pwm0@0 {
806                                 pw_pwm0 {
807                                         groups = "pw_pwm0_grp";
808                                         function = "pw_pwm0";
809                                 };
810                         };
811
812                         pw_pwm1_pmx: pw_pwm1@0 {
813                                 pw_pwm1 {
814                                         groups = "pw_pwm1_grp";
815                                         function = "pw_pwm1";
816                                 };
817                         };
818
819                         pw_pwm2_pmx0: pw_pwm2@0 {
820                                 pw_pwm2_0 {
821                                         groups = "pw_pwm2_grp0";
822                                         function = "pw_pwm2_m0";
823                                 };
824                         };
825
826                         pw_pwm2_pmx1: pw_pwm2@1 {
827                                 pw_pwm2_1 {
828                                         groups = "pw_pwm2_grp1";
829                                         function = "pw_pwm2_m1";
830                                 };
831                         };
832
833                         pw_pwm3_pmx0: pw_pwm3@0 {
834                                 pw_pwm3_0 {
835                                         groups = "pw_pwm3_grp0";
836                                         function = "pw_pwm3_m0";
837                                 };
838                         };
839
840                         pw_pwm3_pmx1: pw_pwm3@1 {
841                                 pw_pwm3_1 {
842                                         groups = "pw_pwm3_grp1";
843                                         function = "pw_pwm3_m1";
844                                 };
845                         };
846
847                         pw_pwm_cpu_vol_pmx0: pw_pwm_cpu_vol@0 {
848                                 pw_pwm_cpu_vol_0 {
849                                         groups = "pw_pwm_cpu_vol_grp0";
850                                         function = "pw_pwm_cpu_vol_m0";
851                                 };
852                         };
853
854                         pw_pwm_cpu_vol_pmx1: pw_pwm_cpu_vol@1 {
855                                 pw_pwm_cpu_vol_1 {
856                                         groups = "pw_pwm_cpu_vol_grp1";
857                                         function = "pw_pwm_cpu_vol_m1";
858                                 };
859                         };
860
861                         pw_backlight_pmx0: pw_backlight@0 {
862                                 pw_backlight_0 {
863                                         groups = "pw_backlight_grp0";
864                                         function = "pw_backlight_m0";
865                                 };
866                         };
867
868                         pw_backlight_pmx1: pw_backlight@1 {
869                                 pw_backlight_1 {
870                                         groups = "pw_backlight_grp1";
871                                         function = "pw_backlight_m1";
872                                 };
873                         };
874
875                         rg_eth_mac_pmx: rg_eth_mac@0 {
876                                 rg_eth_mac {
877                                         groups = "rg_eth_mac_grp";
878                                         function = "rg_eth_mac";
879                                 };
880                         };
881
882                         rg_gmac_phy_intr_n_pmx: rg_gmac_phy_intr_n@0 {
883                                 rg_gmac_phy_intr_n {
884                                         groups = "rg_gmac_phy_intr_n_grp";
885                                         function = "rg_gmac_phy_intr_n";
886                                 };
887                         };
888
889                         rg_rgmii_mac_pmx: rg_rgmii_mac@0 {
890                                 rg_rgmii_mac {
891                                         groups = "rg_rgmii_mac_grp";
892                                         function = "rg_rgmii_mac";
893                                 };
894                         };
895
896                         rg_rgmii_phy_ref_clk_pmx0: rg_rgmii_phy_ref_clk@0 {
897                                 rg_rgmii_phy_ref_clk_0 {
898                                         groups =
899                                                 "rg_rgmii_phy_ref_clk_grp0";
900                                         function =
901                                                 "rg_rgmii_phy_ref_clk_m0";
902                                 };
903                         };
904
905                         rg_rgmii_phy_ref_clk_pmx1: rg_rgmii_phy_ref_clk@1 {
906                                 rg_rgmii_phy_ref_clk_1 {
907                                         groups =
908                                                 "rg_rgmii_phy_ref_clk_grp1";
909                                         function =
910                                                 "rg_rgmii_phy_ref_clk_m1";
911                                 };
912                         };
913
914                         sd0_pmx: sd0@0 {
915                                 sd0 {
916                                         groups = "sd0_grp";
917                                         function = "sd0";
918                                 };
919                         };
920
921                         sd0_4bit_pmx: sd0_4bit@0 {
922                                 sd0_4bit {
923                                         groups = "sd0_4bit_grp";
924                                         function = "sd0_4bit";
925                                 };
926                         };
927
928                         sd1_pmx: sd1@0 {
929                                 sd1 {
930                                         groups = "sd1_grp";
931                                         function = "sd1";
932                                 };
933                         };
934
935                         sd1_4bit_pmx0: sd1_4bit@0 {
936                                 sd1_4bit_0 {
937                                         groups = "sd1_4bit_grp0";
938                                         function = "sd1_4bit_m0";
939                                 };
940                         };
941
942                         sd1_4bit_pmx1: sd1_4bit@1 {
943                                 sd1_4bit_1 {
944                                         groups = "sd1_4bit_grp1";
945                                         function = "sd1_4bit_m1";
946                                 };
947                         };
948
949                         sd2_pmx0: sd2@0 {
950                                 sd2_0 {
951                                         groups = "sd2_grp0";
952                                         function = "sd2_m0";
953                                 };
954                         };
955
956                         sd2_no_cdb_pmx0: sd2_no_cdb@0 {
957                                 sd2_no_cdb_0 {
958                                         groups = "sd2_no_cdb_grp0";
959                                         function = "sd2_no_cdb_m0";
960                                 };
961                         };
962
963                         sd3_pmx: sd3@0 {
964                                 sd3 {
965                                         groups = "sd3_grp";
966                                         function = "sd3";
967                                 };
968                         };
969
970                         sd5_pmx: sd5@0 {
971                                 sd5 {
972                                         groups = "sd5_grp";
973                                         function = "sd5";
974                                 };
975                         };
976
977                         sd6_pmx0: sd6@0 {
978                                 sd6_0 {
979                                         groups = "sd6_grp0";
980                                         function = "sd6_m0";
981                                 };
982                         };
983
984                         sd6_pmx1: sd6@1 {
985                                 sd6_1 {
986                                         groups = "sd6_grp1";
987                                         function = "sd6_m1";
988                                 };
989                         };
990
991                         sp0_ext_ldo_on_pmx: sp0_ext_ldo_on@0 {
992                                 sp0_ext_ldo_on {
993                                         groups = "sp0_ext_ldo_on_grp";
994                                         function = "sp0_ext_ldo_on";
995                                 };
996                         };
997
998                         sp0_qspi_pmx: sp0_qspi@0 {
999                                 sp0_qspi {
1000                                         groups = "sp0_qspi_grp";
1001                                         function = "sp0_qspi";
1002                                 };
1003                         };
1004
1005                         sp1_spi_pmx: sp1_spi@0 {
1006                                 sp1_spi {
1007                                         groups = "sp1_spi_grp";
1008                                         function = "sp1_spi";
1009                                 };
1010                         };
1011
1012                         tpiu_trace_pmx: tpiu_trace@0 {
1013                                 tpiu_trace {
1014                                         groups = "tpiu_trace_grp";
1015                                         function = "tpiu_trace";
1016                                 };
1017                         };
1018
1019                         uart0_pmx: uart0@0 {
1020                                 uart0 {
1021                                         groups = "uart0_grp";
1022                                         function = "uart0";
1023                                 };
1024                         };
1025
1026                         uart0_nopause_pmx: uart0_nopause@0 {
1027                                 uart0_nopause {
1028                                         groups = "uart0_nopause_grp";
1029                                         function = "uart0_nopause";
1030                                 };
1031                         };
1032
1033                         uart1_pmx: uart1@0 {
1034                                 uart1 {
1035                                         groups = "uart1_grp";
1036                                         function = "uart1";
1037                                 };
1038                         };
1039
1040                         uart2_pmx: uart2@0 {
1041                                 uart2 {
1042                                         groups = "uart2_grp";
1043                                         function = "uart2";
1044                                 };
1045                         };
1046
1047                         uart3_pmx0: uart3@0 {
1048                                 uart3_0 {
1049                                         groups = "uart3_grp0";
1050                                         function = "uart3_m0";
1051                                 };
1052                         };
1053
1054                         uart3_pmx1: uart3@1 {
1055                                 uart3_1 {
1056                                         groups = "uart3_grp1";
1057                                         function = "uart3_m1";
1058                                 };
1059                         };
1060
1061                         uart3_pmx2: uart3@2 {
1062                                 uart3_2 {
1063                                         groups = "uart3_grp2";
1064                                         function = "uart3_m2";
1065                                 };
1066                         };
1067
1068                         uart3_pmx3: uart3@3 {
1069                                 uart3_3 {
1070                                         groups = "uart3_grp3";
1071                                         function = "uart3_m3";
1072                                 };
1073                         };
1074
1075                         uart3_nopause_pmx0: uart3_nopause@0 {
1076                                 uart3_nopause_0 {
1077                                         groups = "uart3_nopause_grp0";
1078                                         function = "uart3_nopause_m0";
1079                                 };
1080                         };
1081
1082                         uart3_nopause_pmx1: uart3_nopause@1 {
1083                                 uart3_nopause_1 {
1084                                         groups = "uart3_nopause_grp1";
1085                                         function = "uart3_nopause_m1";
1086                                 };
1087                         };
1088
1089                         uart4_pmx0: uart4@0 {
1090                                 uart4_0 {
1091                                         groups = "uart4_grp0";
1092                                         function = "uart4_m0";
1093                                 };
1094                         };
1095
1096                         uart4_pmx1: uart4@1 {
1097                                 uart4_1 {
1098                                         groups = "uart4_grp1";
1099                                         function = "uart4_m1";
1100                                 };
1101                         };
1102
1103                         uart4_pmx2: uart4@2 {
1104                                 uart4_2 {
1105                                         groups = "uart4_grp2";
1106                                         function = "uart4_m2";
1107                                 };
1108                         };
1109
1110                         uart4_nopause_pmx: uart4_nopause@0 {
1111                                 uart4_nopause {
1112                                         groups = "uart4_nopause_grp";
1113                                         function = "uart4_nopause";
1114                                 };
1115                         };
1116
1117                         usb0_drvvbus_pmx: usb0_drvvbus@0 {
1118                                 usb0_drvvbus {
1119                                         groups = "usb0_drvvbus_grp";
1120                                         function = "usb0_drvvbus";
1121                                 };
1122                         };
1123
1124                         usb1_drvvbus_pmx: usb1_drvvbus@0 {
1125                                 usb1_drvvbus {
1126                                         groups = "usb1_drvvbus_grp";
1127                                         function = "usb1_drvvbus";
1128                                 };
1129                         };
1130
1131                         visbus_dout_pmx: visbus_dout@0 {
1132                                 visbus_dout {
1133                                         groups = "visbus_dout_grp";
1134                                         function = "visbus_dout";
1135                                 };
1136                         };
1137
1138                         vi_vip1_pmx: vi_vip1@0 {
1139                                 vi_vip1 {
1140                                         groups = "vi_vip1_grp";
1141                                         function = "vi_vip1";
1142                                 };
1143                         };
1144
1145                         vi_vip1_ext_pmx: vi_vip1_ext@0 {
1146                                 vi_vip1_ext {
1147                                         groups = "vi_vip1_ext_grp";
1148                                         function = "vi_vip1_ext";
1149                                 };
1150                         };
1151
1152                         vi_vip1_low8bit_pmx: vi_vip1_low8bit@0 {
1153                                 vi_vip1_low8bit {
1154                                         groups = "vi_vip1_low8bit_grp";
1155                                         function = "vi_vip1_low8bit";
1156                                 };
1157                         };
1158
1159                         vi_vip1_high8bit_pmx: vi_vip1_high8bit@0 {
1160                                 vi_vip1_high8bit {
1161                                         groups = "vi_vip1_high8bit_grp";
1162                                         function = "vi_vip1_high8bit";
1163                                 };
1164                         };
1165                 };
1166
1167                 pmipc {
1168                         compatible = "arteris, flexnoc", "simple-bus";
1169                         #address-cells = <1>;
1170                         #size-cells = <1>;
1171                         ranges = <0x13240000 0x13240000 0x00010000>;
1172                         pmipc@0x13240000 {
1173                                 compatible = "sirf,atlas7-pmipc";
1174                                 reg = <0x13240000 0x00010000>;
1175                         };
1176                 };
1177
1178                 dramfw {
1179                         compatible = "arteris, flexnoc", "simple-bus";
1180                         #address-cells = <1>;
1181                         #size-cells = <1>;
1182                         ranges = <0x10830000 0x10830000 0x18000>;
1183                         dramfw@10820000 {
1184                                 compatible = "sirf,nocfw-dramfw";
1185                                 reg = <0x10830000 0x18000>;
1186                         };
1187                 };
1188
1189                 spramfw {
1190                         compatible = "arteris, flexnoc", "simple-bus";
1191                         #address-cells = <1>;
1192                         #size-cells = <1>;
1193                         ranges = <0x10250000 0x10250000 0x3000>;
1194                         spramfw@10820000 {
1195                                 compatible = "sirf,nocfw-spramfw";
1196                                 reg = <0x10250000 0x3000>;
1197                         };
1198                 };
1199
1200                 cpum {
1201                         compatible = "arteris, flexnoc", "simple-bus";
1202                         #address-cells = <1>;
1203                         #size-cells = <1>;
1204                         ranges = <0x10200000 0x10200000 0x3000>;
1205                         cpum@10200000 {
1206                                 compatible = "sirf,nocfw-cpum";
1207                                 reg = <0x10200000 0x3000>;
1208                         };
1209                 };
1210
1211                 cgum {
1212                         compatible = "arteris, flexnoc", "simple-bus";
1213                         #address-cells = <1>;
1214                         #size-cells = <1>;
1215                         ranges = <0x18641000 0x18641000 0x3000>,
1216                                          <0x18620000 0x18620000 0x1000>,
1217                                         <0x18630000 0x18630000 0x10000>;
1218
1219                         cgum@18641000 {
1220                                 compatible = "sirf,nocfw-cgum";
1221                                 reg = <0x18641000 0x3000>;
1222                         };
1223
1224                         car: clock-controller@18620000 {
1225                                 compatible = "sirf,atlas7-car";
1226                                 reg = <0x18620000 0x1000>;
1227                                 #clock-cells = <1>;
1228                                 #reset-cells = <1>;
1229                         };
1230                         pwm: pwm@18630000 {
1231                                 compatible = "sirf,prima2-pwm";
1232                                 #pwm-cells = <2>;
1233                                 reg = <0x18630000 0x10000>;
1234                                 clocks = <&car 138>, <&car 139>, <&car 237>,
1235                                         <&car 240>,  <&car 140>, <&car 246>;
1236                                 clock-names = "pwmc", "sigsrc0", "sigsrc1",
1237                                         "sigsrc2", "sigsrc3", "sigsrc4";
1238                         };
1239                 };
1240
1241                 gnssm {
1242                         compatible = "arteris, flexnoc", "simple-bus";
1243                         #address-cells = <1>;
1244                         #size-cells = <1>;
1245                         ranges = <0x18000000 0x18000000 0x0000ffff>,
1246                                 <0x18010000 0x18010000 0x1000>,
1247                                 <0x18020000 0x18020000 0x1000>,
1248                                 <0x18030000 0x18030000 0x1000>,
1249                                 <0x18040000 0x18040000 0x1000>,
1250                                 <0x18050000 0x18050000 0x1000>,
1251                                 <0x18060000 0x18060000 0x1000>,
1252                                 <0x180b0000 0x180b0000 0x4000>,
1253                                 <0x18100000 0x18100000 0x3000>,
1254                                 <0x18250000 0x18250000 0x10000>,
1255                                 <0x18200000 0x18200000 0x1000>;
1256
1257                         dmac0: dma-controller@18000000 {
1258                                 cell-index = <0>;
1259                                 compatible = "sirf,atlas7-dmac";
1260                                 reg = <0x18000000 0x1000>;
1261                                 interrupts = <0 12 0>;
1262                                 clocks = <&car 89>;
1263                                 dma-channels = <16>;
1264                                 #dma-cells = <1>;
1265                         };
1266
1267                         gnssmfw@0x18100000 {
1268                                 compatible = "sirf,nocfw-gnssm";
1269                                 reg = <0x18100000 0x3000>;
1270                         };
1271
1272                         uart0: uart@18010000 {
1273                                 cell-index = <0>;
1274                                 compatible = "sirf,atlas7-uart";
1275                                 reg = <0x18010000 0x1000>;
1276                                 interrupts = <0 17 0>;
1277                                 clocks = <&car 90>;
1278                                 fifosize = <128>;
1279                                 dmas = <&dmac0 3>, <&dmac0 2>;
1280                                 dma-names = "rx", "tx";
1281                         };
1282
1283                         uart1: uart@18020000 {
1284                                 cell-index = <1>;
1285                                 compatible = "sirf,atlas7-uart";
1286                                 reg = <0x18020000 0x1000>;
1287                                 interrupts = <0 18 0>;
1288                                 clocks = <&car 88>;
1289                                 fifosize = <32>;
1290                         };
1291
1292                         uart2: uart@18030000 {
1293                                 cell-index = <2>;
1294                                 compatible = "sirf,atlas7-uart";
1295                                 reg = <0x18030000 0x1000>;
1296                                 interrupts = <0 19 0>;
1297                                 clocks = <&car 91>;
1298                                 fifosize = <128>;
1299                                 dmas = <&dmac0 6>, <&dmac0 7>;
1300                                 dma-names = "rx", "tx";
1301                                 status = "disabled";
1302                         };
1303                         uart3: uart@18040000 {
1304                                 cell-index = <3>;
1305                                 compatible = "sirf,atlas7-uart";
1306                                 reg = <0x18040000 0x1000>;
1307                                 interrupts = <0 66 0>;
1308                                 clocks = <&car 92>;
1309                                 fifosize = <128>;
1310                                 dmas = <&dmac0 4>, <&dmac0 5>;
1311                                 dma-names = "rx", "tx";
1312                                 status = "disabled";
1313                         };
1314                         uart4: uart@18050000 {
1315                                 cell-index = <4>;
1316                                 compatible = "sirf,atlas7-uart";
1317                                 reg = <0x18050000 0x1000>;
1318                                 interrupts = <0 69 0>;
1319                                 clocks = <&car 93>;
1320                                 fifosize = <128>;
1321                                 dmas = <&dmac0 0>, <&dmac0 1>;
1322                                 dma-names = "rx", "tx";
1323                                 status = "disabled";
1324                         };
1325                         uart5: uart@18060000 {
1326                                 cell-index = <5>;
1327                                 compatible = "sirf,atlas7-uart";
1328                                 reg = <0x18060000 0x1000>;
1329                                 interrupts = <0 71 0>;
1330                                 clocks = <&car 94>;
1331                                 fifosize = <128>;
1332                                 dmas = <&dmac0 8>, <&dmac0 9>;
1333                                 dma-names = "rx", "tx";
1334                                 status = "disabled";
1335                         };
1336                         gmac: eth@180b0000 {
1337                                 compatible = "snps, dwc-eth-qos";
1338                                 reg = <0x180b0000 0x4000>;
1339                                 interrupts = <0 59 0>, <0 70 0>;
1340                                 interrupt-names = "macirq", "macpmt";
1341                                 clocks = <&car 39>, <&car 45>,
1342                                        <&car 86>, <&car 87>;
1343                                 clock-names = "gnssm_rgmii", "gnssm_gmac",
1344                                         "rgmii", "gmac";
1345                                 local-mac-address = [00 00 00 00 00 00];
1346                                 phy-mode = "rgmii";
1347                         };
1348                         dspub@18250000 {
1349                                 compatible = "dx,cc44p";
1350                                 reg = <0x18250000 0x10000>;
1351                                 interrupts = <0 27 0>;
1352                         };
1353
1354                         spi1: spi@18200000 {
1355                                 compatible = "sirf,prima2-spi";
1356                                 reg = <0x18200000 0x1000>;
1357                                 interrupts = <0 16 0>;
1358                                 clocks = <&car 95>;
1359                                 #address-cells = <1>;
1360                                 #size-cells = <0>;
1361                                 dmas = <&dmac0 12>, <&dmac0 13>;
1362                                 dma-names = "rx", "tx";
1363                                 status = "disabled";
1364                         };
1365                 };
1366
1367
1368                 gpum {
1369                         compatible = "arteris, flexnoc", "simple-bus";
1370                         #address-cells = <1>;
1371                         #size-cells = <1>;
1372                         ranges = <0x13000000 0x13000000 0x3000>,
1373                                 <0x13010000 0x13010000 0x1400>,
1374                                 <0x13010800 0x13010800 0x100>,
1375                                 <0x13011000 0x13011000 0x100>;
1376                         gpum@0x13000000 {
1377                                 compatible = "sirf,nocfw-gpum";
1378                                 reg = <0x13000000 0x3000>;
1379                         };
1380                         dmacsdrr: dma-controller@13010800 {
1381                                 cell-index = <5>;
1382                                 compatible = "sirf,atlas7-dmac-v2";
1383                                 reg = <0x13010800 0x100>;
1384                                 interrupts = <0 8 0>;
1385                                 clocks = <&car 127>;
1386                                 #dma-cells = <1>;
1387                                 #dma-channels = <1>;
1388                         };
1389                         dmacsdrw: dma-controller@13011000 {
1390                                 cell-index = <6>;
1391                                 compatible = "sirf,atlas7-dmac-v2";
1392                                 reg = <0x13011000 0x100>;
1393                                 interrupts = <0 9 0>;
1394                                 clocks = <&car 127>;
1395                                 #dma-cells = <1>;
1396                                 #dma-channels = <1>;
1397                         };
1398                         sdr@0x13010000 {
1399                                 compatible = "sirf,atlas7-sdr";
1400                                 reg = <0x13010000 0x1400>;
1401                                 interrupts = <0 7 0>,
1402                                            <0 8 0>,
1403                                            <0 9 0>;
1404                                 clocks = <&car 127>;
1405                                 dmas = <&dmacsdrr 0>, <&dmacsdrw 0>;
1406                                 dma-names = "tx", "rx";
1407                         };
1408                 };
1409
1410                 mediam {
1411                         compatible = "arteris, flexnoc", "simple-bus";
1412                         #address-cells = <1>;
1413                         #size-cells = <1>;
1414                         ranges = <0x15000000 0x15000000 0x00600000>,
1415                                 <0x16000000 0x16000000 0x00200000>,
1416                                 <0x17000000 0x17000000 0x10000>,
1417                                 <0x17020000 0x17020000 0x1000>,
1418                                 <0x17030000 0x17030000 0x1000>,
1419                                 <0x17040000 0x17040000 0x1000>,
1420                                 <0x17050000 0x17050000 0x10000>,
1421                                 <0x17060000 0x17060000 0x200>,
1422                                 <0x17060200 0x17060200 0x100>,
1423                                 <0x17070000 0x17070000 0x200>,
1424                                 <0x17070200 0x17070200 0x100>,
1425                                 <0x170A0000 0x170A0000 0x3000>;
1426
1427                         multimedia@15000000 {
1428                                 compatible = "sirf,atlas7-video-codec";
1429                                 reg = <0x15000000 0x10000>;
1430                                 interrupts = <0 5 0>;
1431                                 clocks = <&car 102>;
1432                         };
1433
1434                         mediam@170A0000 {
1435                                 compatible = "sirf,nocfw-mediam";
1436                                 reg = <0x170A0000 0x3000>;
1437                         };
1438
1439                         gpio_0: gpio_mediam@17040000 {
1440                                 #gpio-cells = <2>;
1441                                 #interrupt-cells = <2>;
1442                                 compatible = "sirf,atlas7-gpio";
1443                                 reg = <0x17040000 0x1000>;
1444                                 interrupts = <0 13 0>, <0 14 0>;
1445                                 clocks = <&car 107>;
1446                                 clock-names = "gpio0_io";
1447                                 gpio-controller;
1448                                 interrupt-controller;
1449
1450                                 gpio-banks = <2>;
1451                                 gpio-ranges = <&pinctrl 0 0 0>,
1452                                                 <&pinctrl 32 0 0>;
1453                                 gpio-ranges-group-names = "lvds_gpio_grp",
1454                                                         "uart_nand_gpio_grp";
1455                         };
1456
1457                         nand@17050000 {
1458                                 compatible = "sirf,atlas7-nand";
1459                                 reg = <0x17050000 0x10000>;
1460                                 pinctrl-names = "default";
1461                                 pinctrl-0 = <&nd_df_pmx>;
1462                                 interrupts = <0 41 0>;
1463                                 clocks = <&car 108>, <&car 112>;
1464                                 clock-names = "nand_io", "nand_nand";
1465                         };
1466
1467                         sd0: sdhci@16000000 {
1468                                 cell-index = <0>;
1469                                 compatible = "sirf,atlas7-sdhc";
1470                                 reg = <0x16000000 0x100000>;
1471                                 interrupts = <0 38 0>;
1472                                 clocks = <&car 109>, <&car 111>;
1473                                 clock-names = "core", "iface";
1474                                 wp-inverted;
1475                                 non-removable;
1476                                 status = "disabled";
1477                                 bus-width = <8>;
1478                         };
1479
1480                         sd1: sdhci@16100000 {
1481                                 cell-index = <1>;
1482                                 compatible = "sirf,atlas7-sdhc";
1483                                 reg = <0x16100000 0x100000>;
1484                                 interrupts = <0 38 0>;
1485                                 clocks = <&car 109>, <&car 111>;
1486                                 clock-names = "core", "iface";
1487                                 non-removable;
1488                                 status = "disabled";
1489                                 bus-width = <8>;
1490                         };
1491
1492                         jpeg@17000000 {
1493                                 compatible = "sirf,atlas7-jpeg";
1494                                 reg = <0x17000000 0x10000>;
1495                                 interrupts = <0 72 0>,
1496                                         <0 73 0>;
1497                                 clocks = <&car 103>;
1498                         };
1499
1500                         usb0: usb@17060000 {
1501                                 cell-index = <0>;
1502                                 compatible = "sirf,atlas7-usb";
1503                                 reg = <0x17060000 0x200>;
1504                                 interrupts = <0 10 0>;
1505                                 clocks = <&car 113>;
1506                                 sirf,usbphy = <&usbphy0>;
1507                                 phy_type = "utmi";
1508                                 dr_mode = "otg";
1509                                 maximum-speed = "high-speed";
1510                                 status = "okay";
1511                         };
1512
1513                         usb1: usb@17070000 {
1514                                 cell-index = <1>;
1515                                 compatible = "sirf,atlas7-usb";
1516                                 reg = <0x17070000 0x200>;
1517                                 interrupts = <0 11 0>;
1518                                 clocks = <&car 114>;
1519                                 sirf,usbphy = <&usbphy1>;
1520                                 phy_type = "utmi";
1521                                 dr_mode = "host";
1522                                 maximum-speed = "high-speed";
1523                                 status = "okay";
1524                         };
1525
1526                         usbphy0: usbphy@0 {
1527                                 compatible = "sirf,atlas7-usbphy";
1528                                 reg = <0x17060200 0x100>;
1529                                 clocks = <&car 115>;
1530                                 status = "okay";
1531                         };
1532
1533                         usbphy1: usbphy@1 {
1534                                 compatible = "sirf,atlas7-usbphy";
1535                                 reg = <0x17070200 0x100>;
1536                                 clocks = <&car 116>;
1537                                 status = "okay";
1538                         };
1539
1540                         i2c0: i2c@17020000 {
1541                                 cell-index = <0>;
1542                                 compatible = "sirf,prima2-i2c";
1543                                 reg = <0x17020000 0x1000>;
1544                                 interrupts = <0 24 0>;
1545                                 clocks = <&car 105>;
1546                                 #address-cells = <1>;
1547                                 #size-cells = <0>;
1548                         };
1549
1550                 };
1551
1552                 vdifm {
1553                         compatible = "arteris, flexnoc", "simple-bus";
1554                         #address-cells = <1>;
1555                         #size-cells = <1>;
1556                         ranges = <0x13290000 0x13290000 0x3000>,
1557                                 <0x13300000 0x13300000 0x1000>,
1558                                 <0x14200000 0x14200000 0x600000>;
1559
1560                         vdifm@13290000 {
1561                                 compatible = "sirf,nocfw-vdifm";
1562                                 reg = <0x13290000 0x3000>;
1563                         };
1564
1565                         gpio_1: gpio_vdifm@13300000 {
1566                                 #gpio-cells = <2>;
1567                                 #interrupt-cells = <2>;
1568                                 compatible = "sirf,atlas7-gpio";
1569                                 reg = <0x13300000 0x1000>;
1570                                 interrupts = <0 43 0>, <0 44 0>,
1571                                                 <0 45 0>, <0 46 0>;
1572                                 clocks = <&car 84>;
1573                                 clock-names = "gpio1_io";
1574                                 gpio-controller;
1575                                 interrupt-controller;
1576
1577                                 gpio-banks = <4>;
1578                                 gpio-ranges = <&pinctrl 0 0 0>,
1579                                                 <&pinctrl 32 0 0>,
1580                                                 <&pinctrl 64 0 0>,
1581                                                 <&pinctrl 96 0 0>;
1582                                 gpio-ranges-group-names = "gnss_gpio_grp",
1583                                                         "lcd_vip_gpio_grp",
1584                                                         "sdio_i2s_gpio_grp",
1585                                                         "sp_rgmii_gpio_grp";
1586                         };
1587
1588                         sd2: sdhci@14200000 {
1589                                 cell-index = <2>;
1590                                 compatible = "sirf,atlas7-sdhc";
1591                                 reg = <0x14200000 0x100000>;
1592                                 interrupts = <0 23 0>;
1593                                 clocks = <&car 70>, <&car 75>;
1594                                 clock-names = "core", "iface";
1595                                 status = "disabled";
1596                                 bus-width = <4>;
1597                                 sd-uhs-sdr50;
1598                                 vqmmc-supply = <&vqmmc>;
1599                                 vqmmc: vqmmc@2 {
1600                                         regulator-min-microvolt = <1650000>;
1601                                         regulator-max-microvolt = <1950000>;
1602                                         regulator-name = "vqmmc-ldo";
1603                                         regulator-type = "voltage";
1604                                         regulator-boot-on;
1605                                         regulator-allow-bypass;
1606                                 };
1607                         };
1608
1609                         sd3: sdhci@14300000 {
1610                                 cell-index = <3>;
1611                                 compatible = "sirf,atlas7-sdhc";
1612                                 reg = <0x14300000 0x100000>;
1613                                 interrupts = <0 23 0>;
1614                                 clocks = <&car 76>, <&car 81>;
1615                                 clock-names = "core", "iface";
1616                                 status = "disabled";
1617                                 bus-width = <4>;
1618                         };
1619
1620                         sd5: sdhci@14500000 {
1621                                 cell-index = <5>;
1622                                 compatible = "sirf,atlas7-sdhc";
1623                                 reg = <0x14500000 0x100000>;
1624                                 interrupts = <0 39 0>;
1625                                 clocks = <&car 71>, <&car 76>;
1626                                 clock-names = "core", "iface";
1627                                 status = "disabled";
1628                                 bus-width = <4>;
1629                                 loop-dma;
1630                         };
1631
1632                         sd6: sdhci@14600000 {
1633                                 cell-index = <6>;
1634                                 compatible = "sirf,atlas7-sdhc";
1635                                 reg = <0x14600000 0x100000>;
1636                                 interrupts = <0 98 0>;
1637                                 clocks = <&car 72>, <&car 77>;
1638                                 clock-names = "core", "iface";
1639                                 status = "disabled";
1640                                 bus-width = <4>;
1641                         };
1642
1643                         sd7: sdhci@14700000 {
1644                                 cell-index = <7>;
1645                                 compatible = "sirf,atlas7-sdhc";
1646                                 reg = <0x14700000 0x100000>;
1647                                 interrupts = <0 98 0>;
1648                                 clocks = <&car 72>, <&car 77>;
1649                                 clock-names = "core", "iface";
1650                                 status = "disabled";
1651                                 bus-width = <4>;
1652                         };
1653                 };
1654
1655                 audiom {
1656                         compatible = "arteris, flexnoc", "simple-bus";
1657                         #address-cells = <1>;
1658                         #size-cells = <1>;
1659                         ranges = <0x10d50000 0x10d50000 0x0000ffff>,
1660                                         <0x10d60000 0x10d60000 0x0000ffff>,
1661                                         <0x10d80000 0x10d80000 0x0000ffff>,
1662                                         <0x10d90000 0x10d90000 0x0000ffff>,
1663                                         <0x10ED0000 0x10ED0000 0x3000>,
1664                                         <0x10dc8000 0x10dc8000 0x1000>,
1665                                         <0x10dc0000 0x10dc0000 0x1000>,
1666                                         <0x10db0000 0x10db0000 0x4000>,
1667                                         <0x10d40000 0x10d40000 0x1000>,
1668                                         <0x10d30000 0x10d30000 0x1000>;
1669
1670                         timer@10dc0000 {
1671                                 compatible = "sirf,atlas7-tick";
1672                                 reg = <0x10dc0000 0x1000>;
1673                                 interrupts = <0 0 0>,
1674                                            <0 1 0>,
1675                                            <0 2 0>,
1676                                            <0 49 0>,
1677                                            <0 50 0>,
1678                                            <0 51 0>;
1679                                 clocks = <&car 47>;
1680                         };
1681
1682                         timerb@10dc8000 {
1683                                         compatible = "sirf,atlas7-tick";
1684                                         reg = <0x10dc8000 0x1000>;
1685                                         interrupts = <0 74 0>,
1686                                                            <0 75 0>,
1687                                                            <0 76 0>,
1688                                                            <0 77 0>,
1689                                                            <0 78 0>,
1690                                                            <0 79 0>;
1691                                         clocks = <&car 47>;
1692                         };
1693
1694                         vip0@10db0000 {
1695                                 compatible = "sirf,atlas7-vip0";
1696                                 reg = <0x10db0000 0x2000>;
1697                                 interrupts = <0 85 0>;
1698                                 sirf,vip_cma_size = <0xC00000>;
1699                         };
1700
1701                         cvd@10db2000 {
1702                                 compatible = "sirf,cvd";
1703                                 reg = <0x10db2000 0x2000>;
1704                                 clocks = <&car 46>;
1705                         };
1706
1707                         dmac2: dma-controller@10d50000 {
1708                                 cell-index = <2>;
1709                                 compatible = "sirf,atlas7-dmac";
1710                                 reg = <0x10d50000 0xffff>;
1711                                 interrupts = <0 55 0>;
1712                                 clocks = <&car 60>;
1713                                 dma-channels = <16>;
1714                                 #dma-cells = <1>;
1715                         };
1716
1717                         dmac3: dma-controller@10d60000 {
1718                                 cell-index = <3>;
1719                                 compatible = "sirf,atlas7-dmac";
1720                                 reg = <0x10d60000 0xffff>;
1721                                 interrupts = <0 56 0>;
1722                                 clocks = <&car 61>;
1723                                 dma-channels = <16>;
1724                                 #dma-cells = <1>;
1725                         };
1726
1727                         adc: adc@10d80000 {
1728                                 compatible = "sirf,atlas7-adc";
1729                                 reg = <0x10d80000 0xffff>;
1730                                 interrupts = <0 34 0>;
1731                                 clocks = <&car 49>;
1732                                 #io-channel-cells = <1>;
1733                         };
1734
1735                         pulsec@10d90000 {
1736                                 compatible = "sirf,prima2-pulsec";
1737                                 reg = <0x10d90000 0xffff>;
1738                                 interrupts = <0 42 0>;
1739                                 clocks = <&car 54>;
1740                         };
1741
1742                         audiom@10ED0000 {
1743                                 compatible = "sirf,nocfw-audiom";
1744                                 reg = <0x10ED0000 0x3000>;
1745                                 interrupts = <0 102 0>;
1746                         };
1747
1748                         usp1: usp@10d30000 {
1749                                 cell-index = <1>;
1750                                 reg = <0x10d30000 0x1000>;
1751                                 fifosize = <512>;
1752                                 clocks = <&car 58>;
1753                                 dmas = <&dmac2 6>, <&dmac2 7>;
1754                                 dma-names = "rx", "tx";
1755                         };
1756
1757                         usp2: usp@10d40000 {
1758                                 cell-index = <2>;
1759                                 reg = <0x10d40000 0x1000>;
1760                                 interrupts = <0 22 0>;
1761                                 clocks = <&car 59>;
1762                                 dmas = <&dmac2 12>, <&dmac2 13>;
1763                                 dma-names = "rx", "tx";
1764                                 #address-cells = <1>;
1765                                 #size-cells = <0>;
1766                                 status = "disabled";
1767                         };
1768                 };
1769
1770                 ddrm {
1771                         compatible = "arteris, flexnoc", "simple-bus";
1772                         #address-cells = <1>;
1773                         #size-cells = <1>;
1774                         ranges = <0x10820000 0x10820000 0x3000>,
1775                                         <0x10800000 0x10800000 0x2000>;
1776                         ddrm@10820000 {
1777                                 compatible = "sirf,nocfw-ddrm";
1778                                 reg = <0x10820000 0x3000>;
1779                                 interrupts = <0 105 0>;
1780                         };
1781
1782                         memory-controller@0x10800000 {
1783                                 compatible = "sirf,atlas7-memc";
1784                                 reg = <0x10800000 0x2000>;
1785                         };
1786
1787                 };
1788
1789                 btm {
1790                         compatible = "arteris, flexnoc", "simple-bus";
1791                         #address-cells = <1>;
1792                         #size-cells = <1>;
1793                         ranges = <0x11002000 0x11002000 0x0000ffff>,
1794                                <0x11010000 0x11010000 0x3000>,
1795                                <0x11000000 0x11000000 0x1000>,
1796                                <0x11001000 0x11001000 0x1000>;
1797
1798                         dmac4: dma-controller@11002000 {
1799                                 cell-index = <4>;
1800                                 compatible = "sirf,atlas7-dmac";
1801                                 reg = <0x11002000 0x1000>;
1802                                 interrupts = <0 99 0>;
1803                                 clocks = <&car 130>;
1804                                 dma-channels = <16>;
1805                                 #dma-cells = <1>;
1806                         };
1807                         uart6: uart@11000000 {
1808                                 cell-index = <6>;
1809                                 compatible = "sirf,atlas7-bt-uart",
1810                                                 "sirf,atlas7-uart";
1811                                 reg = <0x11000000 0x1000>;
1812                                 interrupts = <0 100 0>;
1813                                 clocks = <&car 131>, <&car 133>, <&car 134>;
1814                                 clock-names = "uart", "general", "noc";
1815                                 fifosize = <128>;
1816                                 dmas = <&dmac4 12>, <&dmac4 13>;
1817                                 dma-names = "rx", "tx";
1818                                 status = "disabled";
1819                         };
1820
1821                         usp3: usp@11001000 {
1822                                 compatible = "sirf,atlas7-bt-usp",
1823                                            "sirf,prima2-usp-pcm";
1824                                 cell-index = <3>;
1825                                 reg = <0x11001000 0x1000>;
1826                                 fifosize = <512>;
1827                                 clocks = <&car 132>, <&car 129>, <&car 133>,
1828                                         <&car 134>, <&car 135>;
1829                                 clock-names = "usp3_io", "a7ca_btss", "a7ca_io",
1830                                         "noc_btm_io", "thbtm_io";
1831                                 dmas = <&dmac4 0>, <&dmac4 1>;
1832                                 dma-names = "rx", "tx";
1833                         };
1834
1835                         btm@11010000 {
1836                                 compatible = "sirf,nocfw-btm";
1837                                 reg = <0x11010000 0x3000>;
1838                         };
1839                 };
1840
1841                 rtcm {
1842                         compatible = "arteris, flexnoc", "simple-bus";
1843                         #address-cells = <1>;
1844                         #size-cells = <1>;
1845                         ranges = <0x18810000 0x18810000 0x3000>,
1846                                 <0x18840000 0x18840000 0x1000>,
1847                                 <0x18890000 0x18890000 0x1000>,
1848                                 <0x188B0000 0x188B0000 0x10000>,
1849                                 <0x188D0000 0x188D0000 0x1000>;
1850                         rtcm@18810000 {
1851                                 compatible = "sirf,nocfw-rtcm";
1852                                 reg = <0x18810000 0x3000>;
1853                                 interrupts = <0 109 0>;
1854                         };
1855
1856                         gpio_2: gpio_rtcm@18890000 {
1857                                 #gpio-cells = <2>;
1858                                 #interrupt-cells = <2>;
1859                                 compatible = "sirf,atlas7-gpio";
1860                                 reg = <0x18890000 0x1000>;
1861                                 interrupts = <0 47 0>;
1862                                 gpio-controller;
1863                                 interrupt-controller;
1864
1865                                 gpio-banks = <1>;
1866                                 gpio-ranges = <&pinctrl 0 0 0>;
1867                                 gpio-ranges-group-names = "rtc_gpio_grp";
1868                         };
1869
1870                         rtc-iobg@18840000 {
1871                                 compatible = "sirf,prima2-rtciobg",
1872                                         "sirf-prima2-rtciobg-bus",
1873                                         "simple-bus";
1874                                 #address-cells = <1>;
1875                                 #size-cells = <1>;
1876                                 reg = <0x18840000 0x1000>;
1877
1878                                 sysrtc@2000 {
1879                                         compatible = "sirf,prima2-sysrtc";
1880                                         reg = <0x2000 0x100>;
1881                                         interrupts = <0 52 0>;
1882                                 };
1883                                 pwrc@3000 {
1884                                         compatible = "sirf,atlas7-pwrc";
1885                                         reg = <0x3000 0x100>;
1886                                 };
1887                         };
1888
1889                         qspi: flash@188B0000 {
1890                                 cell-index = <0>;
1891                                 compatible = "sirf,atlas7-qspi-nor";
1892                                 reg = <0x188B0000 0x10000>;
1893                                 interrupts = <0 15 0>;
1894                                 #address-cells = <1>;
1895                                 #size-cells = <0>;
1896                         };
1897
1898                         retain@0x188D0000 {
1899                                 compatible = "sirf,atlas7-retain";
1900                                 reg = <0x188D0000 0x1000>;
1901                         };
1902
1903                 };
1904                 disp-iobg {
1905                         /* lcdc0 */
1906                         compatible = "simple-bus";
1907                         #address-cells = <1>;
1908                         #size-cells = <1>;
1909                         ranges = <0x13100000 0x13100000 0x20000>,
1910                                 <0x10e10000 0x10e10000 0x10000>,
1911                                 <0x17010000 0x17010000 0x10000>;
1912
1913                         lcd@13100000 {
1914                                 compatible = "sirf,atlas7-lcdc";
1915                                 reg = <0x13100000 0x10000>;
1916                                 interrupts = <0 30 0>;
1917                                 clocks = <&car 79>;
1918                         };
1919                         vpp@13110000 {
1920                                 compatible = "sirf,atlas7-vpp";
1921                                 reg = <0x13110000 0x10000>;
1922                                 interrupts = <0 31 0>;
1923                                 clocks = <&car 78>;
1924                                 resets = <&car 29>;
1925                         };
1926                         lvds@10e10000 {
1927                                 compatible = "sirf,atlas7-lvdsc";
1928                                 reg = <0x10e10000 0x10000>;
1929                                 interrupts = <0 64 0>;
1930                                 clocks = <&car 54>;
1931                                 resets = <&car 29>;
1932                         };
1933                         g2d@17010000 {
1934                                 compatible = "sirf, atlas7-g2d";
1935                                 reg = <0x17010000 0x10000>;
1936                                 interrupts = <0 61 0>;
1937                                 clocks = <&car 104>;
1938                         };
1939
1940                 };
1941
1942                 graphics-iobg {
1943                         compatible = "simple-bus";
1944                         #address-cells = <1>;
1945                         #size-cells = <1>;
1946                         ranges = <0x12000000 0x12000000 0x1000000>;
1947
1948                         graphics@12000000 {
1949                                 compatible = "powervr,sgx531";
1950                                 reg = <0x12000000 0x1000000>;
1951                                 interrupts = <0 6 0>;
1952                                 clocks = <&car 126>;
1953                         };
1954                 };
1955         };
1956 };