arch/arm/boot/dts/at91sam9x5_can.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
   4  * Ethernet interface.
   5  *
   6  * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
   7  */
   8
   9 #include <dt-bindings/pinctrl/at91.h>
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11
  12 / {
  13         ahb {
  14                 apb {
  15                         can0: can@f8000000 {
  16                                 compatible = "atmel,at91sam9x5-can";
  17                                 reg = <0xf8000000 0x300>;
  18                                 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
  19                                 pinctrl-names = "default";
  20                                 pinctrl-0 = <&pinctrl_can0_rx_tx>;
  21                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
  22                                 clock-names = "can_clk";
  23                                 status = "disabled";
  24                         };
  25
  26                         can1: can@f8004000 {
  27                                 compatible = "atmel,at91sam9x5-can";
  28                                 reg = <0xf8004000 0x300>;
  29                                 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
  30                                 pinctrl-names = "default";
  31                                 pinctrl-0 = <&pinctrl_can1_rx_tx>;
  32                                 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
  33                                 clock-names = "can_clk";
  34                                 status = "disabled";
  35                         };
  36
  37                         pinctrl@fffff400 {
  38                                 can0 {
  39                                         pinctrl_can0_rx_tx: can0_rx_tx {
  40                                                 atmel,pins =
  41                                                         <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE    /* CANRX0, conflicts with DRXD */
  42                                                         AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* CANTX0, conflicts with DTXD */
  43                                         };
  44                                 };
  45
  46                                 can1 {
  47                                         pinctrl_can1_rx_tx: can1_rx_tx {
  48                                                 atmel,pins =
  49                                                         <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE    /* CANRX1, conflicts with RXD1 */
  50                                                         AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;   /* CANTX1, conflicts with TXD1 */
  51                                         };
  52                                 };
  53                         };
  54                 };
  55         };
  56 };