arch/arm/boot/dts/at91-sama5d27_som1.dtsi

   1 /*
   2  * at91-sama5d27_som1.dtsi - Device Tree file for SAMA5D27 SoM1 board
   3  *
   4  *  Copyright (c) 2017, Microchip Technology Inc.
   5  *                2017 Cristian Birsan <cristian.birsan@microchip.com>
   6  *                2017 Claudiu Beznea <claudiu.beznea@microchip.com>
   7  *
   8  * This file is dual-licensed: you can use it either under the terms
   9  * of the GPL or the X11 license, at your option. Note that this dual
  10  * licensing only applies to this file, and not this project as a
  11  * whole.
  12  *
  13  *  a) This file is free software; you can redistribute it and/or
  14  *     modify it under the terms of the GNU General Public License as
  15  *     published by the Free Software Foundation; either version 2 of the
  16  *     License, or (at your option) any later version.
  17  *
  18  *     This file is distributed in the hope that it will be useful,
  19  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *     GNU General Public License for more details.
  22  *
  23  * Or, alternatively,
  24  *
  25  *  b) Permission is hereby granted, free of charge, to any person
  26  *     obtaining a copy of this software and associated documentation
  27  *     files (the "Software"), to deal in the Software without
  28  *     restriction, including without limitation the rights to use,
  29  *     copy, modify, merge, publish, distribute, sublicense, and/or
  30  *     sell copies of the Software, and to permit persons to whom the
  31  *     Software is furnished to do so, subject to the following
  32  *     conditions:
  33  *
  34  *     The above copyright notice and this permission notice shall be
  35  *     included in all copies or substantial portions of the Software.
  36  *
  37  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  38  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  39  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  40  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  41  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  42  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  43  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  44  *     OTHER DEALINGS IN THE SOFTWARE.
  45  */
  46 #include "sama5d2.dtsi"
  47 #include "sama5d2-pinfunc.h"
  48
  49 / {
  50         model = "Atmel SAMA5D27 SoM1";
  51         compatible = "atmel,sama5d27-som1", "atmel,sama5d27", "atmel,sama5d2", "atmel,sama5";
  52
  53         clocks {
  54                 slow_xtal {
  55                         clock-frequency = <32768>;
  56                 };
  57
  58                 main_xtal {
  59                         clock-frequency = <24000000>;
  60                 };
  61         };
  62
  63         ahb {
  64                 apb {
  65                         qspi1: spi@f0024000 {
  66                                 pinctrl-names = "default";
  67                                 pinctrl-0 = <&pinctrl_qspi1_default>;
  68
  69                                 flash@0 {
  70                                         compatible = "jedec,spi-nor";
  71                                         reg = <0>;
  72                                         spi-max-frequency = <80000000>;
  73                                         spi-tx-bus-width = <4>;
  74                                         spi-rx-bus-width = <4>;
  75                                         m25p,fast-read;
  76                                 };
  77                         };
  78
  79                         macb0: ethernet@f8008000 {
  80                                 pinctrl-names = "default";
  81                                 pinctrl-0 = <&pinctrl_macb0_default>;
  82                                 phy-mode = "rmii";
  83
  84                                 ethernet-phy@0 {
  85                                         reg = <0x0>;
  86                                         interrupt-parent = <&pioA>;
  87                                         interrupts = <PIN_PD31 IRQ_TYPE_LEVEL_LOW>;
  88                                         pinctrl-names = "default";
  89                                         pinctrl-0 = <&pinctrl_macb0_phy_irq>;
  90                                 };
  91                         };
  92
  93                         pinctrl@fc038000 {
  94
  95                                 pinctrl_qspi1_default: qspi1_default {
  96                                         sck_cs {
  97                                                 pinmux = <PIN_PB5__QSPI1_SCK>,
  98                                                          <PIN_PB6__QSPI1_CS>;
  99                                                 bias-disable;
 100                                         };
 101
 102                                         data {
 103                                                 pinmux = <PIN_PB7__QSPI1_IO0>,
 104                                                          <PIN_PB8__QSPI1_IO1>,
 105                                                          <PIN_PB9__QSPI1_IO2>,
 106                                                          <PIN_PB10__QSPI1_IO3>;
 107                                                 bias-pull-up;
 108                                         };
 109                                 };
 110
 111                                 pinctrl_macb0_default: macb0_default {
 112                                         pinmux = <PIN_PD9__GTXCK>,
 113                                                  <PIN_PD10__GTXEN>,
 114                                                  <PIN_PD11__GRXDV>,
 115                                                  <PIN_PD12__GRXER>,
 116                                                  <PIN_PD13__GRX0>,
 117                                                  <PIN_PD14__GRX1>,
 118                                                  <PIN_PD15__GTX0>,
 119                                                  <PIN_PD16__GTX1>,
 120                                                  <PIN_PD17__GMDC>,
 121                                                  <PIN_PD18__GMDIO>;
 122                                         bias-disable;
 123                                 };
 124
 125                                 pinctrl_macb0_phy_irq: macb0_phy_irq {
 126                                         pinmux = <PIN_PD31__GPIO>;
 127                                         bias-disable;
 128                                 };
 129                         };
 130                 };
 131         };
 132 };