arch/arm/boot/dts/aspeed-g5.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 #include <dt-bindings/clock/aspeed-clock.h>
   3
   4 / {
   5         model = "Aspeed BMC";
   6         compatible = "aspeed,ast2500";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 i2c0 = &i2c0;
  13                 i2c1 = &i2c1;
  14                 i2c2 = &i2c2;
  15                 i2c3 = &i2c3;
  16                 i2c4 = &i2c4;
  17                 i2c5 = &i2c5;
  18                 i2c6 = &i2c6;
  19                 i2c7 = &i2c7;
  20                 i2c8 = &i2c8;
  21                 i2c9 = &i2c9;
  22                 i2c10 = &i2c10;
  23                 i2c11 = &i2c11;
  24                 i2c12 = &i2c12;
  25                 i2c13 = &i2c13;
  26                 serial0 = &uart1;
  27                 serial1 = &uart2;
  28                 serial2 = &uart3;
  29                 serial3 = &uart4;
  30                 serial4 = &uart5;
  31                 serial5 = &vuart;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu@0 {
  39                         compatible = "arm,arm1176jzf-s";
  40                         device_type = "cpu";
  41                         reg = <0>;
  42                 };
  43         };
  44
  45         memory@80000000 {
  46                 device_type = "memory";
  47                 reg = <0x80000000 0>;
  48         };
  49
  50         edac: sdram@1e6e0000 {
  51                 compatible = "aspeed,ast2500-sdram-edac";
  52                 reg = <0x1e6e0000 0x174>;
  53                 interrupts = <0>;
  54                 status = "disabled";
  55         };
  56
  57         ahb {
  58                 compatible = "simple-bus";
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61                 ranges;
  62
  63                 fmc: flash-controller@1e620000 {
  64                         reg = < 0x1e620000 0xc4
  65                                 0x20000000 0x10000000 >;
  66                         #address-cells = <1>;
  67                         #size-cells = <0>;
  68                         compatible = "aspeed,ast2500-fmc";
  69                         clocks = <&syscon ASPEED_CLK_AHB>;
  70                         status = "disabled";
  71                         interrupts = <19>;
  72                         flash@0 {
  73                                 reg = < 0 >;
  74                                 compatible = "jedec,spi-nor";
  75                                 status = "disabled";
  76                         };
  77                         flash@1 {
  78                                 reg = < 1 >;
  79                                 compatible = "jedec,spi-nor";
  80                                 status = "disabled";
  81                         };
  82                         flash@2 {
  83                                 reg = < 2 >;
  84                                 compatible = "jedec,spi-nor";
  85                                 status = "disabled";
  86                         };
  87                 };
  88
  89                 spi1: flash-controller@1e630000 {
  90                         reg = < 0x1e630000 0xc4
  91                                 0x30000000 0x08000000 >;
  92                         #address-cells = <1>;
  93                         #size-cells = <0>;
  94                         compatible = "aspeed,ast2500-spi";
  95                         clocks = <&syscon ASPEED_CLK_AHB>;
  96                         status = "disabled";
  97                         flash@0 {
  98                                 reg = < 0 >;
  99                                 compatible = "jedec,spi-nor";
 100                                 status = "disabled";
 101                         };
 102                         flash@1 {
 103                                 reg = < 1 >;
 104                                 compatible = "jedec,spi-nor";
 105                                 status = "disabled";
 106                         };
 107                 };
 108
 109                 spi2: flash-controller@1e631000 {
 110                         reg = < 0x1e631000 0xc4
 111                                 0x38000000 0x08000000 >;
 112                         #address-cells = <1>;
 113                         #size-cells = <0>;
 114                         compatible = "aspeed,ast2500-spi";
 115                         clocks = <&syscon ASPEED_CLK_AHB>;
 116                         status = "disabled";
 117                         flash@0 {
 118                                 reg = < 0 >;
 119                                 compatible = "jedec,spi-nor";
 120                                 status = "disabled";
 121                         };
 122                         flash@1 {
 123                                 reg = < 1 >;
 124                                 compatible = "jedec,spi-nor";
 125                                 status = "disabled";
 126                         };
 127                 };
 128
 129                 vic: interrupt-controller@1e6c0080 {
 130                         compatible = "aspeed,ast2400-vic";
 131                         interrupt-controller;
 132                         #interrupt-cells = <1>;
 133                         valid-sources = <0xfefff7ff 0x0807ffff>;
 134                         reg = <0x1e6c0080 0x80>;
 135                 };
 136
 137                 cvic: copro-interrupt-controller@1e6c2000 {
 138                         compatible = "aspeed,ast2500-cvic", "aspeed-cvic";
 139                         valid-sources = <0xffffffff>;
 140                         copro-sw-interrupts = <1>;
 141                         reg = <0x1e6c2000 0x80>;
 142                 };
 143
 144                 mac0: ethernet@1e660000 {
 145                         compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
 146                         reg = <0x1e660000 0x180>;
 147                         interrupts = <2>;
 148                         clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
 149                         status = "disabled";
 150                 };
 151
 152                 mac1: ethernet@1e680000 {
 153                         compatible = "aspeed,ast2500-mac", "faraday,ftgmac100";
 154                         reg = <0x1e680000 0x180>;
 155                         interrupts = <3>;
 156                         clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
 157                         status = "disabled";
 158                 };
 159
 160                 ehci0: usb@1e6a1000 {
 161                         compatible = "aspeed,ast2500-ehci", "generic-ehci";
 162                         reg = <0x1e6a1000 0x100>;
 163                         interrupts = <5>;
 164                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
 165                         pinctrl-names = "default";
 166                         pinctrl-0 = <&pinctrl_usb2ah_default>;
 167                         status = "disabled";
 168                 };
 169
 170                 ehci1: usb@1e6a3000 {
 171                         compatible = "aspeed,ast2500-ehci", "generic-ehci";
 172                         reg = <0x1e6a3000 0x100>;
 173                         interrupts = <13>;
 174                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
 175                         pinctrl-names = "default";
 176                         pinctrl-0 = <&pinctrl_usb2bh_default>;
 177                         status = "disabled";
 178                 };
 179
 180                 uhci: usb@1e6b0000 {
 181                         compatible = "aspeed,ast2500-uhci", "generic-uhci";
 182                         reg = <0x1e6b0000 0x100>;
 183                         interrupts = <14>;
 184                         #ports = <2>;
 185                         clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
 186                         status = "disabled";
 187                         /*
 188                          * No default pinmux, it will follow EHCI, use an explicit pinmux
 189                          * override if you don't enable EHCI
 190                          */
 191                 };
 192
 193                 vhub: usb-vhub@1e6a0000 {
 194                         compatible = "aspeed,ast2500-usb-vhub";
 195                         reg = <0x1e6a0000 0x300>;
 196                         interrupts = <5>;
 197                         clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
 198                         pinctrl-names = "default";
 199                         pinctrl-0 = <&pinctrl_usb2ad_default>;
 200                         status = "disabled";
 201                 };
 202
 203                 apb {
 204                         compatible = "simple-bus";
 205                         #address-cells = <1>;
 206                         #size-cells = <1>;
 207                         ranges;
 208
 209                         syscon: syscon@1e6e2000 {
 210                                 compatible = "aspeed,ast2500-scu", "syscon", "simple-mfd";
 211                                 reg = <0x1e6e2000 0x1a8>;
 212                                 #address-cells = <1>;
 213                                 #size-cells = <0>;
 214                                 #clock-cells = <1>;
 215                                 #reset-cells = <1>;
 216
 217                                 pinctrl: pinctrl {
 218                                         compatible = "aspeed,g5-pinctrl";
 219                                         aspeed,external-nodes = <&gfx &lhc>;
 220
 221                                 };
 222                         };
 223
 224                         rng: hwrng@1e6e2078 {
 225                                 compatible = "timeriomem_rng";
 226                                 reg = <0x1e6e2078 0x4>;
 227                                 period = <1>;
 228                                 quality = <100>;
 229                         };
 230
 231                         gfx: display@1e6e6000 {
 232                                 compatible = "aspeed,ast2500-gfx", "syscon";
 233                                 reg = <0x1e6e6000 0x1000>;
 234                                 reg-io-width = <4>;
 235                         };
 236
 237                         adc: adc@1e6e9000 {
 238                                 compatible = "aspeed,ast2500-adc";
 239                                 reg = <0x1e6e9000 0xb0>;
 240                                 clocks = <&syscon ASPEED_CLK_APB>;
 241                                 resets = <&syscon ASPEED_RESET_ADC>;
 242                                 #io-channel-cells = <1>;
 243                                 status = "disabled";
 244                         };
 245
 246                         sram: sram@1e720000 {
 247                                 compatible = "mmio-sram";
 248                                 reg = <0x1e720000 0x9000>;      // 36K
 249                         };
 250
 251                         gpio: gpio@1e780000 {
 252                                 #gpio-cells = <2>;
 253                                 gpio-controller;
 254                                 compatible = "aspeed,ast2500-gpio";
 255                                 reg = <0x1e780000 0x1000>;
 256                                 interrupts = <20>;
 257                                 gpio-ranges = <&pinctrl 0 0 220>;
 258                                 clocks = <&syscon ASPEED_CLK_APB>;
 259                                 interrupt-controller;
 260                         };
 261
 262                         timer: timer@1e782000 {
 263                                 /* This timer is a Faraday FTTMR010 derivative */
 264                                 compatible = "aspeed,ast2400-timer";
 265                                 reg = <0x1e782000 0x90>;
 266                                 interrupts = <16 17 18 35 36 37 38 39>;
 267                                 clocks = <&syscon ASPEED_CLK_APB>;
 268                                 clock-names = "PCLK";
 269                         };
 270
 271                         uart1: serial@1e783000 {
 272                                 compatible = "ns16550a";
 273                                 reg = <0x1e783000 0x20>;
 274                                 reg-shift = <2>;
 275                                 interrupts = <9>;
 276                                 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
 277                                 resets = <&lpc_reset 4>;
 278                                 no-loopback-test;
 279                                 status = "disabled";
 280                         };
 281
 282                         uart5: serial@1e784000 {
 283                                 compatible = "ns16550a";
 284                                 reg = <0x1e784000 0x20>;
 285                                 reg-shift = <2>;
 286                                 interrupts = <10>;
 287                                 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
 288                                 no-loopback-test;
 289                                 status = "disabled";
 290                         };
 291
 292                         wdt1: watchdog@1e785000 {
 293                                 compatible = "aspeed,ast2500-wdt";
 294                                 reg = <0x1e785000 0x20>;
 295                                 clocks = <&syscon ASPEED_CLK_APB>;
 296                         };
 297
 298                         wdt2: watchdog@1e785020 {
 299                                 compatible = "aspeed,ast2500-wdt";
 300                                 reg = <0x1e785020 0x20>;
 301                                 clocks = <&syscon ASPEED_CLK_APB>;
 302                         };
 303
 304                         wdt3: watchdog@1e785040 {
 305                                 compatible = "aspeed,ast2500-wdt";
 306                                 reg = <0x1e785040 0x20>;
 307                                 clocks = <&syscon ASPEED_CLK_APB>;
 308                                 status = "disabled";
 309                         };
 310
 311                         pwm_tacho: pwm-tacho-controller@1e786000 {
 312                                 compatible = "aspeed,ast2500-pwm-tacho";
 313                                 #address-cells = <1>;
 314                                 #size-cells = <0>;
 315                                 reg = <0x1e786000 0x1000>;
 316                                 clocks = <&syscon ASPEED_CLK_24M>;
 317                                 resets = <&syscon ASPEED_RESET_PWM>;
 318                                 status = "disabled";
 319                         };
 320
 321                         vuart: serial@1e787000 {
 322                                 compatible = "aspeed,ast2500-vuart";
 323                                 reg = <0x1e787000 0x40>;
 324                                 reg-shift = <2>;
 325                                 interrupts = <8>;
 326                                 clocks = <&syscon ASPEED_CLK_APB>;
 327                                 no-loopback-test;
 328                                 status = "disabled";
 329                         };
 330
 331                         lpc: lpc@1e789000 {
 332                                 compatible = "aspeed,ast2500-lpc", "simple-mfd";
 333                                 reg = <0x1e789000 0x1000>;
 334
 335                                 #address-cells = <1>;
 336                                 #size-cells = <1>;
 337                                 ranges = <0x0 0x1e789000 0x1000>;
 338
 339                                 lpc_bmc: lpc-bmc@0 {
 340                                         compatible = "aspeed,ast2500-lpc-bmc";
 341                                         reg = <0x0 0x80>;
 342                                 };
 343
 344                                 lpc_host: lpc-host@80 {
 345                                         compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
 346                                         reg = <0x80 0x1e0>;
 347                                         reg-io-width = <4>;
 348
 349                                         #address-cells = <1>;
 350                                         #size-cells = <1>;
 351                                         ranges = <0x0 0x80 0x1e0>;
 352
 353                                         lpc_ctrl: lpc-ctrl@0 {
 354                                                 compatible = "aspeed,ast2500-lpc-ctrl";
 355                                                 reg = <0x0 0x80>;
 356                                                 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
 357                                                 status = "disabled";
 358                                         };
 359
 360                                         lpc_snoop: lpc-snoop@0 {
 361                                                 compatible = "aspeed,ast2500-lpc-snoop";
 362                                                 reg = <0x0 0x80>;
 363                                                 interrupts = <8>;
 364                                                 status = "disabled";
 365                                         };
 366
 367                                         lhc: lhc@20 {
 368                                                 compatible = "aspeed,ast2500-lhc";
 369                                                 reg = <0x20 0x24 0x48 0x8>;
 370                                         };
 371
 372                                         lpc_reset: reset-controller@18 {
 373                                                 compatible = "aspeed,ast2500-lpc-reset";
 374                                                 reg = <0x18 0x4>;
 375                                                 #reset-cells = <1>;
 376                                         };
 377
 378                                         ibt: ibt@c0 {
 379                                                 compatible = "aspeed,ast2500-ibt-bmc";
 380                                                 reg = <0xc0 0x18>;
 381                                                 interrupts = <8>;
 382                                                 status = "disabled";
 383                                         };
 384                                 };
 385                         };
 386
 387                         uart2: serial@1e78d000 {
 388                                 compatible = "ns16550a";
 389                                 reg = <0x1e78d000 0x20>;
 390                                 reg-shift = <2>;
 391                                 interrupts = <32>;
 392                                 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
 393                                 resets = <&lpc_reset 5>;
 394                                 no-loopback-test;
 395                                 status = "disabled";
 396                         };
 397
 398                         uart3: serial@1e78e000 {
 399                                 compatible = "ns16550a";
 400                                 reg = <0x1e78e000 0x20>;
 401                                 reg-shift = <2>;
 402                                 interrupts = <33>;
 403                                 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
 404                                 resets = <&lpc_reset 6>;
 405                                 no-loopback-test;
 406                                 status = "disabled";
 407                         };
 408
 409                         uart4: serial@1e78f000 {
 410                                 compatible = "ns16550a";
 411                                 reg = <0x1e78f000 0x20>;
 412                                 reg-shift = <2>;
 413                                 interrupts = <34>;
 414                                 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
 415                                 resets = <&lpc_reset 7>;
 416                                 no-loopback-test;
 417                                 status = "disabled";
 418                         };
 419
 420                         i2c: bus@1e78a000 {
 421                                 compatible = "simple-bus";
 422                                 #address-cells = <1>;
 423                                 #size-cells = <1>;
 424                                 ranges = <0 0x1e78a000 0x1000>;
 425                         };
 426                 };
 427         };
 428 };
 429
 430 &i2c {
 431         i2c_ic: interrupt-controller@0 {
 432                 #interrupt-cells = <1>;
 433                 compatible = "aspeed,ast2500-i2c-ic";
 434                 reg = <0x0 0x40>;
 435                 interrupts = <12>;
 436                 interrupt-controller;
 437         };
 438
 439         i2c0: i2c-bus@40 {
 440                 #address-cells = <1>;
 441                 #size-cells = <0>;
 442                 #interrupt-cells = <1>;
 443
 444                 reg = <0x40 0x40>;
 445                 compatible = "aspeed,ast2500-i2c-bus";
 446                 clocks = <&syscon ASPEED_CLK_APB>;
 447                 resets = <&syscon ASPEED_RESET_I2C>;
 448                 bus-frequency = <100000>;
 449                 interrupts = <0>;
 450                 interrupt-parent = <&i2c_ic>;
 451                 status = "disabled";
 452                 /* Does not need pinctrl properties */
 453         };
 454
 455         i2c1: i2c-bus@80 {
 456                 #address-cells = <1>;
 457                 #size-cells = <0>;
 458                 #interrupt-cells = <1>;
 459
 460                 reg = <0x80 0x40>;
 461                 compatible = "aspeed,ast2500-i2c-bus";
 462                 clocks = <&syscon ASPEED_CLK_APB>;
 463                 resets = <&syscon ASPEED_RESET_I2C>;
 464                 bus-frequency = <100000>;
 465                 interrupts = <1>;
 466                 interrupt-parent = <&i2c_ic>;
 467                 status = "disabled";
 468                 /* Does not need pinctrl properties */
 469         };
 470
 471         i2c2: i2c-bus@c0 {
 472                 #address-cells = <1>;
 473                 #size-cells = <0>;
 474                 #interrupt-cells = <1>;
 475
 476                 reg = <0xc0 0x40>;
 477                 compatible = "aspeed,ast2500-i2c-bus";
 478                 clocks = <&syscon ASPEED_CLK_APB>;
 479                 resets = <&syscon ASPEED_RESET_I2C>;
 480                 bus-frequency = <100000>;
 481                 interrupts = <2>;
 482                 interrupt-parent = <&i2c_ic>;
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&pinctrl_i2c3_default>;
 485                 status = "disabled";
 486         };
 487
 488         i2c3: i2c-bus@100 {
 489                 #address-cells = <1>;
 490                 #size-cells = <0>;
 491                 #interrupt-cells = <1>;
 492
 493                 reg = <0x100 0x40>;
 494                 compatible = "aspeed,ast2500-i2c-bus";
 495                 clocks = <&syscon ASPEED_CLK_APB>;
 496                 resets = <&syscon ASPEED_RESET_I2C>;
 497                 bus-frequency = <100000>;
 498                 interrupts = <3>;
 499                 interrupt-parent = <&i2c_ic>;
 500                 pinctrl-names = "default";
 501                 pinctrl-0 = <&pinctrl_i2c4_default>;
 502                 status = "disabled";
 503         };
 504
 505         i2c4: i2c-bus@140 {
 506                 #address-cells = <1>;
 507                 #size-cells = <0>;
 508                 #interrupt-cells = <1>;
 509
 510                 reg = <0x140 0x40>;
 511                 compatible = "aspeed,ast2500-i2c-bus";
 512                 clocks = <&syscon ASPEED_CLK_APB>;
 513                 resets = <&syscon ASPEED_RESET_I2C>;
 514                 bus-frequency = <100000>;
 515                 interrupts = <4>;
 516                 interrupt-parent = <&i2c_ic>;
 517                 pinctrl-names = "default";
 518                 pinctrl-0 = <&pinctrl_i2c5_default>;
 519                 status = "disabled";
 520         };
 521
 522         i2c5: i2c-bus@180 {
 523                 #address-cells = <1>;
 524                 #size-cells = <0>;
 525                 #interrupt-cells = <1>;
 526
 527                 reg = <0x180 0x40>;
 528                 compatible = "aspeed,ast2500-i2c-bus";
 529                 clocks = <&syscon ASPEED_CLK_APB>;
 530                 resets = <&syscon ASPEED_RESET_I2C>;
 531                 bus-frequency = <100000>;
 532                 interrupts = <5>;
 533                 interrupt-parent = <&i2c_ic>;
 534                 pinctrl-names = "default";
 535                 pinctrl-0 = <&pinctrl_i2c6_default>;
 536                 status = "disabled";
 537         };
 538
 539         i2c6: i2c-bus@1c0 {
 540                 #address-cells = <1>;
 541                 #size-cells = <0>;
 542                 #interrupt-cells = <1>;
 543
 544                 reg = <0x1c0 0x40>;
 545                 compatible = "aspeed,ast2500-i2c-bus";
 546                 clocks = <&syscon ASPEED_CLK_APB>;
 547                 resets = <&syscon ASPEED_RESET_I2C>;
 548                 bus-frequency = <100000>;
 549                 interrupts = <6>;
 550                 interrupt-parent = <&i2c_ic>;
 551                 pinctrl-names = "default";
 552                 pinctrl-0 = <&pinctrl_i2c7_default>;
 553                 status = "disabled";
 554         };
 555
 556         i2c7: i2c-bus@300 {
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 #interrupt-cells = <1>;
 560
 561                 reg = <0x300 0x40>;
 562                 compatible = "aspeed,ast2500-i2c-bus";
 563                 clocks = <&syscon ASPEED_CLK_APB>;
 564                 resets = <&syscon ASPEED_RESET_I2C>;
 565                 bus-frequency = <100000>;
 566                 interrupts = <7>;
 567                 interrupt-parent = <&i2c_ic>;
 568                 pinctrl-names = "default";
 569                 pinctrl-0 = <&pinctrl_i2c8_default>;
 570                 status = "disabled";
 571         };
 572
 573         i2c8: i2c-bus@340 {
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 #interrupt-cells = <1>;
 577
 578                 reg = <0x340 0x40>;
 579                 compatible = "aspeed,ast2500-i2c-bus";
 580                 clocks = <&syscon ASPEED_CLK_APB>;
 581                 resets = <&syscon ASPEED_RESET_I2C>;
 582                 bus-frequency = <100000>;
 583                 interrupts = <8>;
 584                 interrupt-parent = <&i2c_ic>;
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&pinctrl_i2c9_default>;
 587                 status = "disabled";
 588         };
 589
 590         i2c9: i2c-bus@380 {
 591                 #address-cells = <1>;
 592                 #size-cells = <0>;
 593                 #interrupt-cells = <1>;
 594
 595                 reg = <0x380 0x40>;
 596                 compatible = "aspeed,ast2500-i2c-bus";
 597                 clocks = <&syscon ASPEED_CLK_APB>;
 598                 resets = <&syscon ASPEED_RESET_I2C>;
 599                 bus-frequency = <100000>;
 600                 interrupts = <9>;
 601                 interrupt-parent = <&i2c_ic>;
 602                 pinctrl-names = "default";
 603                 pinctrl-0 = <&pinctrl_i2c10_default>;
 604                 status = "disabled";
 605         };
 606
 607         i2c10: i2c-bus@3c0 {
 608                 #address-cells = <1>;
 609                 #size-cells = <0>;
 610                 #interrupt-cells = <1>;
 611
 612                 reg = <0x3c0 0x40>;
 613                 compatible = "aspeed,ast2500-i2c-bus";
 614                 clocks = <&syscon ASPEED_CLK_APB>;
 615                 resets = <&syscon ASPEED_RESET_I2C>;
 616                 bus-frequency = <100000>;
 617                 interrupts = <10>;
 618                 interrupt-parent = <&i2c_ic>;
 619                 pinctrl-names = "default";
 620                 pinctrl-0 = <&pinctrl_i2c11_default>;
 621                 status = "disabled";
 622         };
 623
 624         i2c11: i2c-bus@400 {
 625                 #address-cells = <1>;
 626                 #size-cells = <0>;
 627                 #interrupt-cells = <1>;
 628
 629                 reg = <0x400 0x40>;
 630                 compatible = "aspeed,ast2500-i2c-bus";
 631                 clocks = <&syscon ASPEED_CLK_APB>;
 632                 resets = <&syscon ASPEED_RESET_I2C>;
 633                 bus-frequency = <100000>;
 634                 interrupts = <11>;
 635                 interrupt-parent = <&i2c_ic>;
 636                 pinctrl-names = "default";
 637                 pinctrl-0 = <&pinctrl_i2c12_default>;
 638                 status = "disabled";
 639         };
 640
 641         i2c12: i2c-bus@440 {
 642                 #address-cells = <1>;
 643                 #size-cells = <0>;
 644                 #interrupt-cells = <1>;
 645
 646                 reg = <0x440 0x40>;
 647                 compatible = "aspeed,ast2500-i2c-bus";
 648                 clocks = <&syscon ASPEED_CLK_APB>;
 649                 resets = <&syscon ASPEED_RESET_I2C>;
 650                 bus-frequency = <100000>;
 651                 interrupts = <12>;
 652                 interrupt-parent = <&i2c_ic>;
 653                 pinctrl-names = "default";
 654                 pinctrl-0 = <&pinctrl_i2c13_default>;
 655                 status = "disabled";
 656         };
 657
 658         i2c13: i2c-bus@480 {
 659                 #address-cells = <1>;
 660                 #size-cells = <0>;
 661                 #interrupt-cells = <1>;
 662
 663                 reg = <0x480 0x40>;
 664                 compatible = "aspeed,ast2500-i2c-bus";
 665                 clocks = <&syscon ASPEED_CLK_APB>;
 666                 resets = <&syscon ASPEED_RESET_I2C>;
 667                 bus-frequency = <100000>;
 668                 interrupts = <13>;
 669                 interrupt-parent = <&i2c_ic>;
 670                 pinctrl-names = "default";
 671                 pinctrl-0 = <&pinctrl_i2c14_default>;
 672                 status = "disabled";
 673         };
 674 };
 675
 676 &pinctrl {
 677         pinctrl_acpi_default: acpi_default {
 678                 function = "ACPI";
 679                 groups = "ACPI";
 680         };
 681
 682         pinctrl_adc0_default: adc0_default {
 683                 function = "ADC0";
 684                 groups = "ADC0";
 685         };
 686
 687         pinctrl_adc1_default: adc1_default {
 688                 function = "ADC1";
 689                 groups = "ADC1";
 690         };
 691
 692         pinctrl_adc10_default: adc10_default {
 693                 function = "ADC10";
 694                 groups = "ADC10";
 695         };
 696
 697         pinctrl_adc11_default: adc11_default {
 698                 function = "ADC11";
 699                 groups = "ADC11";
 700         };
 701
 702         pinctrl_adc12_default: adc12_default {
 703                 function = "ADC12";
 704                 groups = "ADC12";
 705         };
 706
 707         pinctrl_adc13_default: adc13_default {
 708                 function = "ADC13";
 709                 groups = "ADC13";
 710         };
 711
 712         pinctrl_adc14_default: adc14_default {
 713                 function = "ADC14";
 714                 groups = "ADC14";
 715         };
 716
 717         pinctrl_adc15_default: adc15_default {
 718                 function = "ADC15";
 719                 groups = "ADC15";
 720         };
 721
 722         pinctrl_adc2_default: adc2_default {
 723                 function = "ADC2";
 724                 groups = "ADC2";
 725         };
 726
 727         pinctrl_adc3_default: adc3_default {
 728                 function = "ADC3";
 729                 groups = "ADC3";
 730         };
 731
 732         pinctrl_adc4_default: adc4_default {
 733                 function = "ADC4";
 734                 groups = "ADC4";
 735         };
 736
 737         pinctrl_adc5_default: adc5_default {
 738                 function = "ADC5";
 739                 groups = "ADC5";
 740         };
 741
 742         pinctrl_adc6_default: adc6_default {
 743                 function = "ADC6";
 744                 groups = "ADC6";
 745         };
 746
 747         pinctrl_adc7_default: adc7_default {
 748                 function = "ADC7";
 749                 groups = "ADC7";
 750         };
 751
 752         pinctrl_adc8_default: adc8_default {
 753                 function = "ADC8";
 754                 groups = "ADC8";
 755         };
 756
 757         pinctrl_adc9_default: adc9_default {
 758                 function = "ADC9";
 759                 groups = "ADC9";
 760         };
 761
 762         pinctrl_bmcint_default: bmcint_default {
 763                 function = "BMCINT";
 764                 groups = "BMCINT";
 765         };
 766
 767         pinctrl_ddcclk_default: ddcclk_default {
 768                 function = "DDCCLK";
 769                 groups = "DDCCLK";
 770         };
 771
 772         pinctrl_ddcdat_default: ddcdat_default {
 773                 function = "DDCDAT";
 774                 groups = "DDCDAT";
 775         };
 776
 777         pinctrl_espi_default: espi_default {
 778                 function = "ESPI";
 779                 groups = "ESPI";
 780         };
 781
 782         pinctrl_fwspics1_default: fwspics1_default {
 783                 function = "FWSPICS1";
 784                 groups = "FWSPICS1";
 785         };
 786
 787         pinctrl_fwspics2_default: fwspics2_default {
 788                 function = "FWSPICS2";
 789                 groups = "FWSPICS2";
 790         };
 791
 792         pinctrl_gpid0_default: gpid0_default {
 793                 function = "GPID0";
 794                 groups = "GPID0";
 795         };
 796
 797         pinctrl_gpid2_default: gpid2_default {
 798                 function = "GPID2";
 799                 groups = "GPID2";
 800         };
 801
 802         pinctrl_gpid4_default: gpid4_default {
 803                 function = "GPID4";
 804                 groups = "GPID4";
 805         };
 806
 807         pinctrl_gpid6_default: gpid6_default {
 808                 function = "GPID6";
 809                 groups = "GPID6";
 810         };
 811
 812         pinctrl_gpie0_default: gpie0_default {
 813                 function = "GPIE0";
 814                 groups = "GPIE0";
 815         };
 816
 817         pinctrl_gpie2_default: gpie2_default {
 818                 function = "GPIE2";
 819                 groups = "GPIE2";
 820         };
 821
 822         pinctrl_gpie4_default: gpie4_default {
 823                 function = "GPIE4";
 824                 groups = "GPIE4";
 825         };
 826
 827         pinctrl_gpie6_default: gpie6_default {
 828                 function = "GPIE6";
 829                 groups = "GPIE6";
 830         };
 831
 832         pinctrl_i2c10_default: i2c10_default {
 833                 function = "I2C10";
 834                 groups = "I2C10";
 835         };
 836
 837         pinctrl_i2c11_default: i2c11_default {
 838                 function = "I2C11";
 839                 groups = "I2C11";
 840         };
 841
 842         pinctrl_i2c12_default: i2c12_default {
 843                 function = "I2C12";
 844                 groups = "I2C12";
 845         };
 846
 847         pinctrl_i2c13_default: i2c13_default {
 848                 function = "I2C13";
 849                 groups = "I2C13";
 850         };
 851
 852         pinctrl_i2c14_default: i2c14_default {
 853                 function = "I2C14";
 854                 groups = "I2C14";
 855         };
 856
 857         pinctrl_i2c3_default: i2c3_default {
 858                 function = "I2C3";
 859                 groups = "I2C3";
 860         };
 861
 862         pinctrl_i2c4_default: i2c4_default {
 863                 function = "I2C4";
 864                 groups = "I2C4";
 865         };
 866
 867         pinctrl_i2c5_default: i2c5_default {
 868                 function = "I2C5";
 869                 groups = "I2C5";
 870         };
 871
 872         pinctrl_i2c6_default: i2c6_default {
 873                 function = "I2C6";
 874                 groups = "I2C6";
 875         };
 876
 877         pinctrl_i2c7_default: i2c7_default {
 878                 function = "I2C7";
 879                 groups = "I2C7";
 880         };
 881
 882         pinctrl_i2c8_default: i2c8_default {
 883                 function = "I2C8";
 884                 groups = "I2C8";
 885         };
 886
 887         pinctrl_i2c9_default: i2c9_default {
 888                 function = "I2C9";
 889                 groups = "I2C9";
 890         };
 891
 892         pinctrl_lad0_default: lad0_default {
 893                 function = "LAD0";
 894                 groups = "LAD0";
 895         };
 896
 897         pinctrl_lad1_default: lad1_default {
 898                 function = "LAD1";
 899                 groups = "LAD1";
 900         };
 901
 902         pinctrl_lad2_default: lad2_default {
 903                 function = "LAD2";
 904                 groups = "LAD2";
 905         };
 906
 907         pinctrl_lad3_default: lad3_default {
 908                 function = "LAD3";
 909                 groups = "LAD3";
 910         };
 911
 912         pinctrl_lclk_default: lclk_default {
 913                 function = "LCLK";
 914                 groups = "LCLK";
 915         };
 916
 917         pinctrl_lframe_default: lframe_default {
 918                 function = "LFRAME";
 919                 groups = "LFRAME";
 920         };
 921
 922         pinctrl_lpchc_default: lpchc_default {
 923                 function = "LPCHC";
 924                 groups = "LPCHC";
 925         };
 926
 927         pinctrl_lpcpd_default: lpcpd_default {
 928                 function = "LPCPD";
 929                 groups = "LPCPD";
 930         };
 931
 932         pinctrl_lpcplus_default: lpcplus_default {
 933                 function = "LPCPLUS";
 934                 groups = "LPCPLUS";
 935         };
 936
 937         pinctrl_lpcpme_default: lpcpme_default {
 938                 function = "LPCPME";
 939                 groups = "LPCPME";
 940         };
 941
 942         pinctrl_lpcrst_default: lpcrst_default {
 943                 function = "LPCRST";
 944                 groups = "LPCRST";
 945         };
 946
 947         pinctrl_lpcsmi_default: lpcsmi_default {
 948                 function = "LPCSMI";
 949                 groups = "LPCSMI";
 950         };
 951
 952         pinctrl_lsirq_default: lsirq_default {
 953                 function = "LSIRQ";
 954                 groups = "LSIRQ";
 955         };
 956
 957         pinctrl_mac1link_default: mac1link_default {
 958                 function = "MAC1LINK";
 959                 groups = "MAC1LINK";
 960         };
 961
 962         pinctrl_mac2link_default: mac2link_default {
 963                 function = "MAC2LINK";
 964                 groups = "MAC2LINK";
 965         };
 966
 967         pinctrl_mdio1_default: mdio1_default {
 968                 function = "MDIO1";
 969                 groups = "MDIO1";
 970         };
 971
 972         pinctrl_mdio2_default: mdio2_default {
 973                 function = "MDIO2";
 974                 groups = "MDIO2";
 975         };
 976
 977         pinctrl_ncts1_default: ncts1_default {
 978                 function = "NCTS1";
 979                 groups = "NCTS1";
 980         };
 981
 982         pinctrl_ncts2_default: ncts2_default {
 983                 function = "NCTS2";
 984                 groups = "NCTS2";
 985         };
 986
 987         pinctrl_ncts3_default: ncts3_default {
 988                 function = "NCTS3";
 989                 groups = "NCTS3";
 990         };
 991
 992         pinctrl_ncts4_default: ncts4_default {
 993                 function = "NCTS4";
 994                 groups = "NCTS4";
 995         };
 996
 997         pinctrl_ndcd1_default: ndcd1_default {
 998                 function = "NDCD1";
 999                 groups = "NDCD1";
1000         };
1001
1002         pinctrl_ndcd2_default: ndcd2_default {
1003                 function = "NDCD2";
1004                 groups = "NDCD2";
1005         };
1006
1007         pinctrl_ndcd3_default: ndcd3_default {
1008                 function = "NDCD3";
1009                 groups = "NDCD3";
1010         };
1011
1012         pinctrl_ndcd4_default: ndcd4_default {
1013                 function = "NDCD4";
1014                 groups = "NDCD4";
1015         };
1016
1017         pinctrl_ndsr1_default: ndsr1_default {
1018                 function = "NDSR1";
1019                 groups = "NDSR1";
1020         };
1021
1022         pinctrl_ndsr2_default: ndsr2_default {
1023                 function = "NDSR2";
1024                 groups = "NDSR2";
1025         };
1026
1027         pinctrl_ndsr3_default: ndsr3_default {
1028                 function = "NDSR3";
1029                 groups = "NDSR3";
1030         };
1031
1032         pinctrl_ndsr4_default: ndsr4_default {
1033                 function = "NDSR4";
1034                 groups = "NDSR4";
1035         };
1036
1037         pinctrl_ndtr1_default: ndtr1_default {
1038                 function = "NDTR1";
1039                 groups = "NDTR1";
1040         };
1041
1042         pinctrl_ndtr2_default: ndtr2_default {
1043                 function = "NDTR2";
1044                 groups = "NDTR2";
1045         };
1046
1047         pinctrl_ndtr3_default: ndtr3_default {
1048                 function = "NDTR3";
1049                 groups = "NDTR3";
1050         };
1051
1052         pinctrl_ndtr4_default: ndtr4_default {
1053                 function = "NDTR4";
1054                 groups = "NDTR4";
1055         };
1056
1057         pinctrl_nri1_default: nri1_default {
1058                 function = "NRI1";
1059                 groups = "NRI1";
1060         };
1061
1062         pinctrl_nri2_default: nri2_default {
1063                 function = "NRI2";
1064                 groups = "NRI2";
1065         };
1066
1067         pinctrl_nri3_default: nri3_default {
1068                 function = "NRI3";
1069                 groups = "NRI3";
1070         };
1071
1072         pinctrl_nri4_default: nri4_default {
1073                 function = "NRI4";
1074                 groups = "NRI4";
1075         };
1076
1077         pinctrl_nrts1_default: nrts1_default {
1078                 function = "NRTS1";
1079                 groups = "NRTS1";
1080         };
1081
1082         pinctrl_nrts2_default: nrts2_default {
1083                 function = "NRTS2";
1084                 groups = "NRTS2";
1085         };
1086
1087         pinctrl_nrts3_default: nrts3_default {
1088                 function = "NRTS3";
1089                 groups = "NRTS3";
1090         };
1091
1092         pinctrl_nrts4_default: nrts4_default {
1093                 function = "NRTS4";
1094                 groups = "NRTS4";
1095         };
1096
1097         pinctrl_oscclk_default: oscclk_default {
1098                 function = "OSCCLK";
1099                 groups = "OSCCLK";
1100         };
1101
1102         pinctrl_pewake_default: pewake_default {
1103                 function = "PEWAKE";
1104                 groups = "PEWAKE";
1105         };
1106
1107         pinctrl_pnor_default: pnor_default {
1108                 function = "PNOR";
1109                 groups = "PNOR";
1110         };
1111
1112         pinctrl_pwm0_default: pwm0_default {
1113                 function = "PWM0";
1114                 groups = "PWM0";
1115         };
1116
1117         pinctrl_pwm1_default: pwm1_default {
1118                 function = "PWM1";
1119                 groups = "PWM1";
1120         };
1121
1122         pinctrl_pwm2_default: pwm2_default {
1123                 function = "PWM2";
1124                 groups = "PWM2";
1125         };
1126
1127         pinctrl_pwm3_default: pwm3_default {
1128                 function = "PWM3";
1129                 groups = "PWM3";
1130         };
1131
1132         pinctrl_pwm4_default: pwm4_default {
1133                 function = "PWM4";
1134                 groups = "PWM4";
1135         };
1136
1137         pinctrl_pwm5_default: pwm5_default {
1138                 function = "PWM5";
1139                 groups = "PWM5";
1140         };
1141
1142         pinctrl_pwm6_default: pwm6_default {
1143                 function = "PWM6";
1144                 groups = "PWM6";
1145         };
1146
1147         pinctrl_pwm7_default: pwm7_default {
1148                 function = "PWM7";
1149                 groups = "PWM7";
1150         };
1151
1152         pinctrl_rgmii1_default: rgmii1_default {
1153                 function = "RGMII1";
1154                 groups = "RGMII1";
1155         };
1156
1157         pinctrl_rgmii2_default: rgmii2_default {
1158                 function = "RGMII2";
1159                 groups = "RGMII2";
1160         };
1161
1162         pinctrl_rmii1_default: rmii1_default {
1163                 function = "RMII1";
1164                 groups = "RMII1";
1165         };
1166
1167         pinctrl_rmii2_default: rmii2_default {
1168                 function = "RMII2";
1169                 groups = "RMII2";
1170         };
1171
1172         pinctrl_rxd1_default: rxd1_default {
1173                 function = "RXD1";
1174                 groups = "RXD1";
1175         };
1176
1177         pinctrl_rxd2_default: rxd2_default {
1178                 function = "RXD2";
1179                 groups = "RXD2";
1180         };
1181
1182         pinctrl_rxd3_default: rxd3_default {
1183                 function = "RXD3";
1184                 groups = "RXD3";
1185         };
1186
1187         pinctrl_rxd4_default: rxd4_default {
1188                 function = "RXD4";
1189                 groups = "RXD4";
1190         };
1191
1192         pinctrl_salt1_default: salt1_default {
1193                 function = "SALT1";
1194                 groups = "SALT1";
1195         };
1196
1197         pinctrl_salt10_default: salt10_default {
1198                 function = "SALT10";
1199                 groups = "SALT10";
1200         };
1201
1202         pinctrl_salt11_default: salt11_default {
1203                 function = "SALT11";
1204                 groups = "SALT11";
1205         };
1206
1207         pinctrl_salt12_default: salt12_default {
1208                 function = "SALT12";
1209                 groups = "SALT12";
1210         };
1211
1212         pinctrl_salt13_default: salt13_default {
1213                 function = "SALT13";
1214                 groups = "SALT13";
1215         };
1216
1217         pinctrl_salt14_default: salt14_default {
1218                 function = "SALT14";
1219                 groups = "SALT14";
1220         };
1221
1222         pinctrl_salt2_default: salt2_default {
1223                 function = "SALT2";
1224                 groups = "SALT2";
1225         };
1226
1227         pinctrl_salt3_default: salt3_default {
1228                 function = "SALT3";
1229                 groups = "SALT3";
1230         };
1231
1232         pinctrl_salt4_default: salt4_default {
1233                 function = "SALT4";
1234                 groups = "SALT4";
1235         };
1236
1237         pinctrl_salt5_default: salt5_default {
1238                 function = "SALT5";
1239                 groups = "SALT5";
1240         };
1241
1242         pinctrl_salt6_default: salt6_default {
1243                 function = "SALT6";
1244                 groups = "SALT6";
1245         };
1246
1247         pinctrl_salt7_default: salt7_default {
1248                 function = "SALT7";
1249                 groups = "SALT7";
1250         };
1251
1252         pinctrl_salt8_default: salt8_default {
1253                 function = "SALT8";
1254                 groups = "SALT8";
1255         };
1256
1257         pinctrl_salt9_default: salt9_default {
1258                 function = "SALT9";
1259                 groups = "SALT9";
1260         };
1261
1262         pinctrl_scl1_default: scl1_default {
1263                 function = "SCL1";
1264                 groups = "SCL1";
1265         };
1266
1267         pinctrl_scl2_default: scl2_default {
1268                 function = "SCL2";
1269                 groups = "SCL2";
1270         };
1271
1272         pinctrl_sd1_default: sd1_default {
1273                 function = "SD1";
1274                 groups = "SD1";
1275         };
1276
1277         pinctrl_sd2_default: sd2_default {
1278                 function = "SD2";
1279                 groups = "SD2";
1280         };
1281
1282         pinctrl_sda1_default: sda1_default {
1283                 function = "SDA1";
1284                 groups = "SDA1";
1285         };
1286
1287         pinctrl_sda2_default: sda2_default {
1288                 function = "SDA2";
1289                 groups = "SDA2";
1290         };
1291
1292         pinctrl_sgps1_default: sgps1_default {
1293                 function = "SGPS1";
1294                 groups = "SGPS1";
1295         };
1296
1297         pinctrl_sgps2_default: sgps2_default {
1298                 function = "SGPS2";
1299                 groups = "SGPS2";
1300         };
1301
1302         pinctrl_sioonctrl_default: sioonctrl_default {
1303                 function = "SIOONCTRL";
1304                 groups = "SIOONCTRL";
1305         };
1306
1307         pinctrl_siopbi_default: siopbi_default {
1308                 function = "SIOPBI";
1309                 groups = "SIOPBI";
1310         };
1311
1312         pinctrl_siopbo_default: siopbo_default {
1313                 function = "SIOPBO";
1314                 groups = "SIOPBO";
1315         };
1316
1317         pinctrl_siopwreq_default: siopwreq_default {
1318                 function = "SIOPWREQ";
1319                 groups = "SIOPWREQ";
1320         };
1321
1322         pinctrl_siopwrgd_default: siopwrgd_default {
1323                 function = "SIOPWRGD";
1324                 groups = "SIOPWRGD";
1325         };
1326
1327         pinctrl_sios3_default: sios3_default {
1328                 function = "SIOS3";
1329                 groups = "SIOS3";
1330         };
1331
1332         pinctrl_sios5_default: sios5_default {
1333                 function = "SIOS5";
1334                 groups = "SIOS5";
1335         };
1336
1337         pinctrl_siosci_default: siosci_default {
1338                 function = "SIOSCI";
1339                 groups = "SIOSCI";
1340         };
1341
1342         pinctrl_spi1_default: spi1_default {
1343                 function = "SPI1";
1344                 groups = "SPI1";
1345         };
1346
1347         pinctrl_spi1cs1_default: spi1cs1_default {
1348                 function = "SPI1CS1";
1349                 groups = "SPI1CS1";
1350         };
1351
1352         pinctrl_spi1debug_default: spi1debug_default {
1353                 function = "SPI1DEBUG";
1354                 groups = "SPI1DEBUG";
1355         };
1356
1357         pinctrl_spi1passthru_default: spi1passthru_default {
1358                 function = "SPI1PASSTHRU";
1359                 groups = "SPI1PASSTHRU";
1360         };
1361
1362         pinctrl_spi2ck_default: spi2ck_default {
1363                 function = "SPI2CK";
1364                 groups = "SPI2CK";
1365         };
1366
1367         pinctrl_spi2cs0_default: spi2cs0_default {
1368                 function = "SPI2CS0";
1369                 groups = "SPI2CS0";
1370         };
1371
1372         pinctrl_spi2cs1_default: spi2cs1_default {
1373                 function = "SPI2CS1";
1374                 groups = "SPI2CS1";
1375         };
1376
1377         pinctrl_spi2miso_default: spi2miso_default {
1378                 function = "SPI2MISO";
1379                 groups = "SPI2MISO";
1380         };
1381
1382         pinctrl_spi2mosi_default: spi2mosi_default {
1383                 function = "SPI2MOSI";
1384                 groups = "SPI2MOSI";
1385         };
1386
1387         pinctrl_timer3_default: timer3_default {
1388                 function = "TIMER3";
1389                 groups = "TIMER3";
1390         };
1391
1392         pinctrl_timer4_default: timer4_default {
1393                 function = "TIMER4";
1394                 groups = "TIMER4";
1395         };
1396
1397         pinctrl_timer5_default: timer5_default {
1398                 function = "TIMER5";
1399                 groups = "TIMER5";
1400         };
1401
1402         pinctrl_timer6_default: timer6_default {
1403                 function = "TIMER6";
1404                 groups = "TIMER6";
1405         };
1406
1407         pinctrl_timer7_default: timer7_default {
1408                 function = "TIMER7";
1409                 groups = "TIMER7";
1410         };
1411
1412         pinctrl_timer8_default: timer8_default {
1413                 function = "TIMER8";
1414                 groups = "TIMER8";
1415         };
1416
1417         pinctrl_txd1_default: txd1_default {
1418                 function = "TXD1";
1419                 groups = "TXD1";
1420         };
1421
1422         pinctrl_txd2_default: txd2_default {
1423                 function = "TXD2";
1424                 groups = "TXD2";
1425         };
1426
1427         pinctrl_txd3_default: txd3_default {
1428                 function = "TXD3";
1429                 groups = "TXD3";
1430         };
1431
1432         pinctrl_txd4_default: txd4_default {
1433                 function = "TXD4";
1434                 groups = "TXD4";
1435         };
1436
1437         pinctrl_uart6_default: uart6_default {
1438                 function = "UART6";
1439                 groups = "UART6";
1440         };
1441
1442         pinctrl_usbcki_default: usbcki_default {
1443                 function = "USBCKI";
1444                 groups = "USBCKI";
1445         };
1446
1447         pinctrl_usb2ah_default: usb2ah_default {
1448                 function = "USB2AH";
1449                 groups = "USB2AH";
1450         };
1451
1452         pinctrl_usb2ad_default: usb2ad_default {
1453                 function = "USB2AD";
1454                 groups = "USB2AD";
1455         };
1456
1457         pinctrl_usb11bhid_default: usb11bhid_default {
1458                 function = "USB11BHID";
1459                 groups = "USB11BHID";
1460         };
1461
1462         pinctrl_usb2bh_default: usb2bh_default {
1463                 function = "USB2BH";
1464                 groups = "USB2BH";
1465         };
1466
1467         pinctrl_vgabiosrom_default: vgabiosrom_default {
1468                 function = "VGABIOSROM";
1469                 groups = "VGABIOSROM";
1470         };
1471
1472         pinctrl_vgahs_default: vgahs_default {
1473                 function = "VGAHS";
1474                 groups = "VGAHS";
1475         };
1476
1477         pinctrl_vgavs_default: vgavs_default {
1478                 function = "VGAVS";
1479                 groups = "VGAVS";
1480         };
1481
1482         pinctrl_vpi24_default: vpi24_default {
1483                 function = "VPI24";
1484                 groups = "VPI24";
1485         };
1486
1487         pinctrl_vpo_default: vpo_default {
1488                 function = "VPO";
1489                 groups = "VPO";
1490         };
1491
1492         pinctrl_wdtrst1_default: wdtrst1_default {
1493                 function = "WDTRST1";
1494                 groups = "WDTRST1";
1495         };
1496
1497         pinctrl_wdtrst2_default: wdtrst2_default {
1498                 function = "WDTRST2";
1499                 groups = "WDTRST2";
1500         };
1501 };