arch/arm/boot/dts/aspeed-g4.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+
   2 #include <dt-bindings/clock/aspeed-clock.h>
   3
   4 / {
   5         model = "Aspeed BMC";
   6         compatible = "aspeed,ast2400";
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         interrupt-parent = <&vic>;
  10
  11         aliases {
  12                 i2c0 = &i2c0;
  13                 i2c1 = &i2c1;
  14                 i2c2 = &i2c2;
  15                 i2c3 = &i2c3;
  16                 i2c4 = &i2c4;
  17                 i2c5 = &i2c5;
  18                 i2c6 = &i2c6;
  19                 i2c7 = &i2c7;
  20                 i2c8 = &i2c8;
  21                 i2c9 = &i2c9;
  22                 i2c10 = &i2c10;
  23                 i2c11 = &i2c11;
  24                 i2c12 = &i2c12;
  25                 i2c13 = &i2c13;
  26                 serial0 = &uart1;
  27                 serial1 = &uart2;
  28                 serial2 = &uart3;
  29                 serial3 = &uart4;
  30                 serial4 = &uart5;
  31                 serial5 = &vuart;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 cpu@0 {
  39                         compatible = "arm,arm926ej-s";
  40                         device_type = "cpu";
  41                         reg = <0>;
  42                 };
  43         };
  44
  45         memory@40000000 {
  46                 device_type = "memory";
  47                 reg = <0x40000000 0>;
  48         };
  49
  50         ahb {
  51                 compatible = "simple-bus";
  52                 #address-cells = <1>;
  53                 #size-cells = <1>;
  54                 ranges;
  55
  56                 fmc: flash-controller@1e620000 {
  57                         reg = < 0x1e620000 0x94
  58                                 0x20000000 0x10000000 >;
  59                         #address-cells = <1>;
  60                         #size-cells = <0>;
  61                         compatible = "aspeed,ast2400-fmc";
  62                         clocks = <&syscon ASPEED_CLK_AHB>;
  63                         status = "disabled";
  64                         interrupts = <19>;
  65                         flash@0 {
  66                                 reg = < 0 >;
  67                                 compatible = "jedec,spi-nor";
  68                                 status = "disabled";
  69                         };
  70                 };
  71
  72                 spi: flash-controller@1e630000 {
  73                         reg = < 0x1e630000 0x18
  74                                 0x30000000 0x10000000 >;
  75                         #address-cells = <1>;
  76                         #size-cells = <0>;
  77                         compatible = "aspeed,ast2400-spi";
  78                         clocks = <&syscon ASPEED_CLK_AHB>;
  79                         status = "disabled";
  80                         flash@0 {
  81                                 reg = < 0 >;
  82                                 compatible = "jedec,spi-nor";
  83                                 status = "disabled";
  84                         };
  85                 };
  86
  87                 vic: interrupt-controller@1e6c0080 {
  88                         compatible = "aspeed,ast2400-vic";
  89                         interrupt-controller;
  90                         #interrupt-cells = <1>;
  91                         valid-sources = <0xffffffff 0x0007ffff>;
  92                         reg = <0x1e6c0080 0x80>;
  93                 };
  94
  95                 mac0: ethernet@1e660000 {
  96                         compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
  97                         reg = <0x1e660000 0x180>;
  98                         interrupts = <2>;
  99                         clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
 100                         status = "disabled";
 101                 };
 102
 103                 mac1: ethernet@1e680000 {
 104                         compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
 105                         reg = <0x1e680000 0x180>;
 106                         interrupts = <3>;
 107                         clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
 108                         status = "disabled";
 109                 };
 110
 111                 apb {
 112                         compatible = "simple-bus";
 113                         #address-cells = <1>;
 114                         #size-cells = <1>;
 115                         ranges;
 116
 117                         syscon: syscon@1e6e2000 {
 118                                 compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
 119                                 reg = <0x1e6e2000 0x1a8>;
 120                                 #address-cells = <1>;
 121                                 #size-cells = <0>;
 122                                 #clock-cells = <1>;
 123                                 #reset-cells = <1>;
 124
 125                                 pinctrl: pinctrl {
 126                                         compatible = "aspeed,g4-pinctrl";
 127                                 };
 128                         };
 129
 130                         adc: adc@1e6e9000 {
 131                                 compatible = "aspeed,ast2400-adc";
 132                                 reg = <0x1e6e9000 0xb0>;
 133                                 clocks = <&syscon ASPEED_CLK_APB>;
 134                                 resets = <&syscon ASPEED_RESET_ADC>;
 135                                 #io-channel-cells = <1>;
 136                                 status = "disabled";
 137                         };
 138
 139                         sram@1e720000 {
 140                                 compatible = "mmio-sram";
 141                                 reg = <0x1e720000 0x8000>;      // 32K
 142                         };
 143
 144                         gpio: gpio@1e780000 {
 145                                 #gpio-cells = <2>;
 146                                 gpio-controller;
 147                                 compatible = "aspeed,ast2400-gpio";
 148                                 reg = <0x1e780000 0x1000>;
 149                                 interrupts = <20>;
 150                                 gpio-ranges = <&pinctrl 0 0 220>;
 151                                 clocks = <&syscon ASPEED_CLK_APB>;
 152                                 interrupt-controller;
 153                         };
 154
 155                         timer: timer@1e782000 {
 156                                 /* This timer is a Faraday FTTMR010 derivative */
 157                                 compatible = "aspeed,ast2400-timer";
 158                                 reg = <0x1e782000 0x90>;
 159                                 interrupts = <16 17 18 35 36 37 38 39>;
 160                                 clocks = <&syscon ASPEED_CLK_APB>;
 161                                 clock-names = "PCLK";
 162                         };
 163
 164                         uart1: serial@1e783000 {
 165                                 compatible = "ns16550a";
 166                                 reg = <0x1e783000 0x20>;
 167                                 reg-shift = <2>;
 168                                 interrupts = <9>;
 169                                 clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
 170                                 resets = <&lpc_reset 4>;
 171                                 no-loopback-test;
 172                                 status = "disabled";
 173                         };
 174
 175                         uart5: serial@1e784000 {
 176                                 compatible = "ns16550a";
 177                                 reg = <0x1e784000 0x20>;
 178                                 reg-shift = <2>;
 179                                 interrupts = <10>;
 180                                 clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
 181                                 no-loopback-test;
 182                                 status = "disabled";
 183                         };
 184
 185                         wdt1: watchdog@1e785000 {
 186                                 compatible = "aspeed,ast2400-wdt";
 187                                 reg = <0x1e785000 0x1c>;
 188                                 clocks = <&syscon ASPEED_CLK_APB>;
 189                         };
 190
 191                         wdt2: watchdog@1e785020 {
 192                                 compatible = "aspeed,ast2400-wdt";
 193                                 reg = <0x1e785020 0x1c>;
 194                                 clocks = <&syscon ASPEED_CLK_APB>;
 195                         };
 196
 197                         pwm_tacho: pwm-tacho-controller@1e786000 {
 198                                 compatible = "aspeed,ast2400-pwm-tacho";
 199                                 #address-cells = <1>;
 200                                 #size-cells = <0>;
 201                                 reg = <0x1e786000 0x1000>;
 202                                 clocks = <&syscon ASPEED_CLK_APB>;
 203                                 resets = <&syscon ASPEED_RESET_PWM>;
 204                                 status = "disabled";
 205                         };
 206
 207                         vuart: serial@1e787000 {
 208                                 compatible = "aspeed,ast2400-vuart";
 209                                 reg = <0x1e787000 0x40>;
 210                                 reg-shift = <2>;
 211                                 interrupts = <8>;
 212                                 clocks = <&syscon ASPEED_CLK_APB>;
 213                                 no-loopback-test;
 214                                 status = "disabled";
 215                         };
 216
 217                         lpc: lpc@1e789000 {
 218                                 compatible = "aspeed,ast2400-lpc", "simple-mfd";
 219                                 reg = <0x1e789000 0x1000>;
 220
 221                                 #address-cells = <1>;
 222                                 #size-cells = <1>;
 223                                 ranges = <0x0 0x1e789000 0x1000>;
 224
 225                                 lpc_bmc: lpc-bmc@0 {
 226                                         compatible = "aspeed,ast2400-lpc-bmc";
 227                                         reg = <0x0 0x80>;
 228                                 };
 229
 230                                 lpc_host: lpc-host@80 {
 231                                         compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
 232                                         reg = <0x80 0x1e0>;
 233                                         reg-io-width = <4>;
 234
 235                                         #address-cells = <1>;
 236                                         #size-cells = <1>;
 237                                         ranges = <0x0 0x80 0x1e0>;
 238
 239                                         lpc_ctrl: lpc-ctrl@0 {
 240                                                 compatible = "aspeed,ast2400-lpc-ctrl";
 241                                                 reg = <0x0 0x80>;
 242                                                 clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
 243                                                 status = "disabled";
 244                                         };
 245
 246                                         lpc_snoop: lpc-snoop@0 {
 247                                                 compatible = "aspeed,ast2400-lpc-snoop";
 248                                                 reg = <0x0 0x80>;
 249                                                 interrupts = <8>;
 250                                                 status = "disabled";
 251                                         };
 252
 253                                         lhc: lhc@20 {
 254                                                 compatible = "aspeed,ast2400-lhc";
 255                                                 reg = <0x20 0x24 0x48 0x8>;
 256                                         };
 257
 258                                         lpc_reset: reset-controller@18 {
 259                                                 compatible = "aspeed,ast2400-lpc-reset";
 260                                                 reg = <0x18 0x4>;
 261                                                 #reset-cells = <1>;
 262                                         };
 263
 264                                         ibt: ibt@c0  {
 265                                                 compatible = "aspeed,ast2400-ibt-bmc";
 266                                                 reg = <0xc0 0x18>;
 267                                                 interrupts = <8>;
 268                                                 status = "disabled";
 269                                         };
 270                                 };
 271                         };
 272
 273                         uart2: serial@1e78d000 {
 274                                 compatible = "ns16550a";
 275                                 reg = <0x1e78d000 0x20>;
 276                                 reg-shift = <2>;
 277                                 interrupts = <32>;
 278                                 clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
 279                                 resets = <&lpc_reset 5>;
 280                                 no-loopback-test;
 281                                 status = "disabled";
 282                         };
 283
 284                         uart3: serial@1e78e000 {
 285                                 compatible = "ns16550a";
 286                                 reg = <0x1e78e000 0x20>;
 287                                 reg-shift = <2>;
 288                                 interrupts = <33>;
 289                                 clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
 290                                 resets = <&lpc_reset 6>;
 291                                 no-loopback-test;
 292                                 status = "disabled";
 293                         };
 294
 295                         uart4: serial@1e78f000 {
 296                                 compatible = "ns16550a";
 297                                 reg = <0x1e78f000 0x20>;
 298                                 reg-shift = <2>;
 299                                 interrupts = <34>;
 300                                 clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
 301                                 resets = <&lpc_reset 7>;
 302                                 no-loopback-test;
 303                                 status = "disabled";
 304                         };
 305
 306                         i2c: i2c@1e78a000 {
 307                                 compatible = "simple-bus";
 308                                 #address-cells = <1>;
 309                                 #size-cells = <1>;
 310                                 ranges = <0 0x1e78a000 0x1000>;
 311                         };
 312                 };
 313         };
 314 };
 315
 316 &i2c {
 317         i2c_ic: interrupt-controller@0 {
 318                 #interrupt-cells = <1>;
 319                 compatible = "aspeed,ast2400-i2c-ic";
 320                 reg = <0x0 0x40>;
 321                 interrupts = <12>;
 322                 interrupt-controller;
 323         };
 324
 325         i2c0: i2c-bus@40 {
 326                 #address-cells = <1>;
 327                 #size-cells = <0>;
 328                 #interrupt-cells = <1>;
 329
 330                 reg = <0x40 0x40>;
 331                 compatible = "aspeed,ast2400-i2c-bus";
 332                 clocks = <&syscon ASPEED_CLK_APB>;
 333                 resets = <&syscon ASPEED_RESET_I2C>;
 334                 bus-frequency = <100000>;
 335                 interrupts = <0>;
 336                 interrupt-parent = <&i2c_ic>;
 337                 status = "disabled";
 338                 /* Does not need pinctrl properties */
 339         };
 340
 341         i2c1: i2c-bus@80 {
 342                 #address-cells = <1>;
 343                 #size-cells = <0>;
 344                 #interrupt-cells = <1>;
 345
 346                 reg = <0x80 0x40>;
 347                 compatible = "aspeed,ast2400-i2c-bus";
 348                 clocks = <&syscon ASPEED_CLK_APB>;
 349                 resets = <&syscon ASPEED_RESET_I2C>;
 350                 bus-frequency = <100000>;
 351                 interrupts = <1>;
 352                 interrupt-parent = <&i2c_ic>;
 353                 status = "disabled";
 354                 /* Does not need pinctrl properties */
 355         };
 356
 357         i2c2: i2c-bus@c0 {
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 #interrupt-cells = <1>;
 361
 362                 reg = <0xc0 0x40>;
 363                 compatible = "aspeed,ast2400-i2c-bus";
 364                 clocks = <&syscon ASPEED_CLK_APB>;
 365                 resets = <&syscon ASPEED_RESET_I2C>;
 366                 bus-frequency = <100000>;
 367                 interrupts = <2>;
 368                 interrupt-parent = <&i2c_ic>;
 369                 pinctrl-names = "default";
 370                 pinctrl-0 = <&pinctrl_i2c3_default>;
 371                 status = "disabled";
 372         };
 373
 374         i2c3: i2c-bus@100 {
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377                 #interrupt-cells = <1>;
 378
 379                 reg = <0x100 0x40>;
 380                 compatible = "aspeed,ast2400-i2c-bus";
 381                 clocks = <&syscon ASPEED_CLK_APB>;
 382                 resets = <&syscon ASPEED_RESET_I2C>;
 383                 bus-frequency = <100000>;
 384                 interrupts = <3>;
 385                 interrupt-parent = <&i2c_ic>;
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&pinctrl_i2c4_default>;
 388                 status = "disabled";
 389         };
 390
 391         i2c4: i2c-bus@140 {
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 #interrupt-cells = <1>;
 395
 396                 reg = <0x140 0x40>;
 397                 compatible = "aspeed,ast2400-i2c-bus";
 398                 clocks = <&syscon ASPEED_CLK_APB>;
 399                 resets = <&syscon ASPEED_RESET_I2C>;
 400                 bus-frequency = <100000>;
 401                 interrupts = <4>;
 402                 interrupt-parent = <&i2c_ic>;
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&pinctrl_i2c5_default>;
 405                 status = "disabled";
 406         };
 407
 408         i2c5: i2c-bus@180 {
 409                 #address-cells = <1>;
 410                 #size-cells = <0>;
 411                 #interrupt-cells = <1>;
 412
 413                 reg = <0x180 0x40>;
 414                 compatible = "aspeed,ast2400-i2c-bus";
 415                 clocks = <&syscon ASPEED_CLK_APB>;
 416                 resets = <&syscon ASPEED_RESET_I2C>;
 417                 bus-frequency = <100000>;
 418                 interrupts = <5>;
 419                 interrupt-parent = <&i2c_ic>;
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&pinctrl_i2c6_default>;
 422                 status = "disabled";
 423         };
 424
 425         i2c6: i2c-bus@1c0 {
 426                 #address-cells = <1>;
 427                 #size-cells = <0>;
 428                 #interrupt-cells = <1>;
 429
 430                 reg = <0x1c0 0x40>;
 431                 compatible = "aspeed,ast2400-i2c-bus";
 432                 clocks = <&syscon ASPEED_CLK_APB>;
 433                 resets = <&syscon ASPEED_RESET_I2C>;
 434                 bus-frequency = <100000>;
 435                 interrupts = <6>;
 436                 interrupt-parent = <&i2c_ic>;
 437                 pinctrl-names = "default";
 438                 pinctrl-0 = <&pinctrl_i2c7_default>;
 439                 status = "disabled";
 440         };
 441
 442         i2c7: i2c-bus@300 {
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 #interrupt-cells = <1>;
 446
 447                 reg = <0x300 0x40>;
 448                 compatible = "aspeed,ast2400-i2c-bus";
 449                 clocks = <&syscon ASPEED_CLK_APB>;
 450                 resets = <&syscon ASPEED_RESET_I2C>;
 451                 bus-frequency = <100000>;
 452                 interrupts = <7>;
 453                 interrupt-parent = <&i2c_ic>;
 454                 pinctrl-names = "default";
 455                 pinctrl-0 = <&pinctrl_i2c8_default>;
 456                 status = "disabled";
 457         };
 458
 459         i2c8: i2c-bus@340 {
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 #interrupt-cells = <1>;
 463
 464                 reg = <0x340 0x40>;
 465                 compatible = "aspeed,ast2400-i2c-bus";
 466                 clocks = <&syscon ASPEED_CLK_APB>;
 467                 resets = <&syscon ASPEED_RESET_I2C>;
 468                 bus-frequency = <100000>;
 469                 interrupts = <8>;
 470                 interrupt-parent = <&i2c_ic>;
 471                 pinctrl-names = "default";
 472                 pinctrl-0 = <&pinctrl_i2c9_default>;
 473                 status = "disabled";
 474         };
 475
 476         i2c9: i2c-bus@380 {
 477                 #address-cells = <1>;
 478                 #size-cells = <0>;
 479                 #interrupt-cells = <1>;
 480
 481                 reg = <0x380 0x40>;
 482                 compatible = "aspeed,ast2400-i2c-bus";
 483                 clocks = <&syscon ASPEED_CLK_APB>;
 484                 resets = <&syscon ASPEED_RESET_I2C>;
 485                 bus-frequency = <100000>;
 486                 interrupts = <9>;
 487                 interrupt-parent = <&i2c_ic>;
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&pinctrl_i2c10_default>;
 490                 status = "disabled";
 491         };
 492
 493         i2c10: i2c-bus@3c0 {
 494                 #address-cells = <1>;
 495                 #size-cells = <0>;
 496                 #interrupt-cells = <1>;
 497
 498                 reg = <0x3c0 0x40>;
 499                 compatible = "aspeed,ast2400-i2c-bus";
 500                 clocks = <&syscon ASPEED_CLK_APB>;
 501                 resets = <&syscon ASPEED_RESET_I2C>;
 502                 bus-frequency = <100000>;
 503                 interrupts = <10>;
 504                 interrupt-parent = <&i2c_ic>;
 505                 pinctrl-names = "default";
 506                 pinctrl-0 = <&pinctrl_i2c11_default>;
 507                 status = "disabled";
 508         };
 509
 510         i2c11: i2c-bus@400 {
 511                 #address-cells = <1>;
 512                 #size-cells = <0>;
 513                 #interrupt-cells = <1>;
 514
 515                 reg = <0x400 0x40>;
 516                 compatible = "aspeed,ast2400-i2c-bus";
 517                 clocks = <&syscon ASPEED_CLK_APB>;
 518                 resets = <&syscon ASPEED_RESET_I2C>;
 519                 bus-frequency = <100000>;
 520                 interrupts = <11>;
 521                 interrupt-parent = <&i2c_ic>;
 522                 pinctrl-names = "default";
 523                 pinctrl-0 = <&pinctrl_i2c12_default>;
 524                 status = "disabled";
 525         };
 526
 527         i2c12: i2c-bus@440 {
 528                 #address-cells = <1>;
 529                 #size-cells = <0>;
 530                 #interrupt-cells = <1>;
 531
 532                 reg = <0x440 0x40>;
 533                 compatible = "aspeed,ast2400-i2c-bus";
 534                 clocks = <&syscon ASPEED_CLK_APB>;
 535                 resets = <&syscon ASPEED_RESET_I2C>;
 536                 bus-frequency = <100000>;
 537                 interrupts = <12>;
 538                 interrupt-parent = <&i2c_ic>;
 539                 pinctrl-names = "default";
 540                 pinctrl-0 = <&pinctrl_i2c13_default>;
 541                 status = "disabled";
 542         };
 543
 544         i2c13: i2c-bus@480 {
 545                 #address-cells = <1>;
 546                 #size-cells = <0>;
 547                 #interrupt-cells = <1>;
 548
 549                 reg = <0x480 0x40>;
 550                 compatible = "aspeed,ast2400-i2c-bus";
 551                 clocks = <&syscon ASPEED_CLK_APB>;
 552                 resets = <&syscon ASPEED_RESET_I2C>;
 553                 bus-frequency = <100000>;
 554                 interrupts = <13>;
 555                 interrupt-parent = <&i2c_ic>;
 556                 pinctrl-names = "default";
 557                 pinctrl-0 = <&pinctrl_i2c14_default>;
 558                 status = "disabled";
 559         };
 560 };
 561
 562 &pinctrl {
 563         pinctrl_acpi_default: acpi_default {
 564                 function = "ACPI";
 565                 groups = "ACPI";
 566         };
 567
 568         pinctrl_adc0_default: adc0_default {
 569                 function = "ADC0";
 570                 groups = "ADC0";
 571         };
 572
 573         pinctrl_adc1_default: adc1_default {
 574                 function = "ADC1";
 575                 groups = "ADC1";
 576         };
 577
 578         pinctrl_adc10_default: adc10_default {
 579                 function = "ADC10";
 580                 groups = "ADC10";
 581         };
 582
 583         pinctrl_adc11_default: adc11_default {
 584                 function = "ADC11";
 585                 groups = "ADC11";
 586         };
 587
 588         pinctrl_adc12_default: adc12_default {
 589                 function = "ADC12";
 590                 groups = "ADC12";
 591         };
 592
 593         pinctrl_adc13_default: adc13_default {
 594                 function = "ADC13";
 595                 groups = "ADC13";
 596         };
 597
 598         pinctrl_adc14_default: adc14_default {
 599                 function = "ADC14";
 600                 groups = "ADC14";
 601         };
 602
 603         pinctrl_adc15_default: adc15_default {
 604                 function = "ADC15";
 605                 groups = "ADC15";
 606         };
 607
 608         pinctrl_adc2_default: adc2_default {
 609                 function = "ADC2";
 610                 groups = "ADC2";
 611         };
 612
 613         pinctrl_adc3_default: adc3_default {
 614                 function = "ADC3";
 615                 groups = "ADC3";
 616         };
 617
 618         pinctrl_adc4_default: adc4_default {
 619                 function = "ADC4";
 620                 groups = "ADC4";
 621         };
 622
 623         pinctrl_adc5_default: adc5_default {
 624                 function = "ADC5";
 625                 groups = "ADC5";
 626         };
 627
 628         pinctrl_adc6_default: adc6_default {
 629                 function = "ADC6";
 630                 groups = "ADC6";
 631         };
 632
 633         pinctrl_adc7_default: adc7_default {
 634                 function = "ADC7";
 635                 groups = "ADC7";
 636         };
 637
 638         pinctrl_adc8_default: adc8_default {
 639                 function = "ADC8";
 640                 groups = "ADC8";
 641         };
 642
 643         pinctrl_adc9_default: adc9_default {
 644                 function = "ADC9";
 645                 groups = "ADC9";
 646         };
 647
 648         pinctrl_bmcint_default: bmcint_default {
 649                 function = "BMCINT";
 650                 groups = "BMCINT";
 651         };
 652
 653         pinctrl_ddcclk_default: ddcclk_default {
 654                 function = "DDCCLK";
 655                 groups = "DDCCLK";
 656         };
 657
 658         pinctrl_ddcdat_default: ddcdat_default {
 659                 function = "DDCDAT";
 660                 groups = "DDCDAT";
 661         };
 662
 663         pinctrl_extrst_default: extrst_default {
 664                 function = "EXTRST";
 665                 groups = "EXTRST";
 666         };
 667
 668         pinctrl_flack_default: flack_default {
 669                 function = "FLACK";
 670                 groups = "FLACK";
 671         };
 672
 673         pinctrl_flbusy_default: flbusy_default {
 674                 function = "FLBUSY";
 675                 groups = "FLBUSY";
 676         };
 677
 678         pinctrl_flwp_default: flwp_default {
 679                 function = "FLWP";
 680                 groups = "FLWP";
 681         };
 682
 683         pinctrl_gpid_default: gpid_default {
 684                 function = "GPID";
 685                 groups = "GPID";
 686         };
 687
 688         pinctrl_gpid0_default: gpid0_default {
 689                 function = "GPID0";
 690                 groups = "GPID0";
 691         };
 692
 693         pinctrl_gpid2_default: gpid2_default {
 694                 function = "GPID2";
 695                 groups = "GPID2";
 696         };
 697
 698         pinctrl_gpid4_default: gpid4_default {
 699                 function = "GPID4";
 700                 groups = "GPID4";
 701         };
 702
 703         pinctrl_gpid6_default: gpid6_default {
 704                 function = "GPID6";
 705                 groups = "GPID6";
 706         };
 707
 708         pinctrl_gpie0_default: gpie0_default {
 709                 function = "GPIE0";
 710                 groups = "GPIE0";
 711         };
 712
 713         pinctrl_gpie2_default: gpie2_default {
 714                 function = "GPIE2";
 715                 groups = "GPIE2";
 716         };
 717
 718         pinctrl_gpie4_default: gpie4_default {
 719                 function = "GPIE4";
 720                 groups = "GPIE4";
 721         };
 722
 723         pinctrl_gpie6_default: gpie6_default {
 724                 function = "GPIE6";
 725                 groups = "GPIE6";
 726         };
 727
 728         pinctrl_i2c10_default: i2c10_default {
 729                 function = "I2C10";
 730                 groups = "I2C10";
 731         };
 732
 733         pinctrl_i2c11_default: i2c11_default {
 734                 function = "I2C11";
 735                 groups = "I2C11";
 736         };
 737
 738         pinctrl_i2c12_default: i2c12_default {
 739                 function = "I2C12";
 740                 groups = "I2C12";
 741         };
 742
 743         pinctrl_i2c13_default: i2c13_default {
 744                 function = "I2C13";
 745                 groups = "I2C13";
 746         };
 747
 748         pinctrl_i2c14_default: i2c14_default {
 749                 function = "I2C14";
 750                 groups = "I2C14";
 751         };
 752
 753         pinctrl_i2c3_default: i2c3_default {
 754                 function = "I2C3";
 755                 groups = "I2C3";
 756         };
 757
 758         pinctrl_i2c4_default: i2c4_default {
 759                 function = "I2C4";
 760                 groups = "I2C4";
 761         };
 762
 763         pinctrl_i2c5_default: i2c5_default {
 764                 function = "I2C5";
 765                 groups = "I2C5";
 766         };
 767
 768         pinctrl_i2c6_default: i2c6_default {
 769                 function = "I2C6";
 770                 groups = "I2C6";
 771         };
 772
 773         pinctrl_i2c7_default: i2c7_default {
 774                 function = "I2C7";
 775                 groups = "I2C7";
 776         };
 777
 778         pinctrl_i2c8_default: i2c8_default {
 779                 function = "I2C8";
 780                 groups = "I2C8";
 781         };
 782
 783         pinctrl_i2c9_default: i2c9_default {
 784                 function = "I2C9";
 785                 groups = "I2C9";
 786         };
 787
 788         pinctrl_lpcpd_default: lpcpd_default {
 789                 function = "LPCPD";
 790                 groups = "LPCPD";
 791         };
 792
 793         pinctrl_lpcpme_default: lpcpme_default {
 794                 function = "LPCPME";
 795                 groups = "LPCPME";
 796         };
 797
 798         pinctrl_lpcrst_default: lpcrst_default {
 799                 function = "LPCRST";
 800                 groups = "LPCRST";
 801         };
 802
 803         pinctrl_lpcsmi_default: lpcsmi_default {
 804                 function = "LPCSMI";
 805                 groups = "LPCSMI";
 806         };
 807
 808         pinctrl_mac1link_default: mac1link_default {
 809                 function = "MAC1LINK";
 810                 groups = "MAC1LINK";
 811         };
 812
 813         pinctrl_mac2link_default: mac2link_default {
 814                 function = "MAC2LINK";
 815                 groups = "MAC2LINK";
 816         };
 817
 818         pinctrl_mdio1_default: mdio1_default {
 819                 function = "MDIO1";
 820                 groups = "MDIO1";
 821         };
 822
 823         pinctrl_mdio2_default: mdio2_default {
 824                 function = "MDIO2";
 825                 groups = "MDIO2";
 826         };
 827
 828         pinctrl_ncts1_default: ncts1_default {
 829                 function = "NCTS1";
 830                 groups = "NCTS1";
 831         };
 832
 833         pinctrl_ncts2_default: ncts2_default {
 834                 function = "NCTS2";
 835                 groups = "NCTS2";
 836         };
 837
 838         pinctrl_ncts3_default: ncts3_default {
 839                 function = "NCTS3";
 840                 groups = "NCTS3";
 841         };
 842
 843         pinctrl_ncts4_default: ncts4_default {
 844                 function = "NCTS4";
 845                 groups = "NCTS4";
 846         };
 847
 848         pinctrl_ndcd1_default: ndcd1_default {
 849                 function = "NDCD1";
 850                 groups = "NDCD1";
 851         };
 852
 853         pinctrl_ndcd2_default: ndcd2_default {
 854                 function = "NDCD2";
 855                 groups = "NDCD2";
 856         };
 857
 858         pinctrl_ndcd3_default: ndcd3_default {
 859                 function = "NDCD3";
 860                 groups = "NDCD3";
 861         };
 862
 863         pinctrl_ndcd4_default: ndcd4_default {
 864                 function = "NDCD4";
 865                 groups = "NDCD4";
 866         };
 867
 868         pinctrl_ndsr1_default: ndsr1_default {
 869                 function = "NDSR1";
 870                 groups = "NDSR1";
 871         };
 872
 873         pinctrl_ndsr2_default: ndsr2_default {
 874                 function = "NDSR2";
 875                 groups = "NDSR2";
 876         };
 877
 878         pinctrl_ndsr3_default: ndsr3_default {
 879                 function = "NDSR3";
 880                 groups = "NDSR3";
 881         };
 882
 883         pinctrl_ndsr4_default: ndsr4_default {
 884                 function = "NDSR4";
 885                 groups = "NDSR4";
 886         };
 887
 888         pinctrl_ndtr1_default: ndtr1_default {
 889                 function = "NDTR1";
 890                 groups = "NDTR1";
 891         };
 892
 893         pinctrl_ndtr2_default: ndtr2_default {
 894                 function = "NDTR2";
 895                 groups = "NDTR2";
 896         };
 897
 898         pinctrl_ndtr3_default: ndtr3_default {
 899                 function = "NDTR3";
 900                 groups = "NDTR3";
 901         };
 902
 903         pinctrl_ndtr4_default: ndtr4_default {
 904                 function = "NDTR4";
 905                 groups = "NDTR4";
 906         };
 907
 908         pinctrl_ndts4_default: ndts4_default {
 909                 function = "NDTS4";
 910                 groups = "NDTS4";
 911         };
 912
 913         pinctrl_nri1_default: nri1_default {
 914                 function = "NRI1";
 915                 groups = "NRI1";
 916         };
 917
 918         pinctrl_nri2_default: nri2_default {
 919                 function = "NRI2";
 920                 groups = "NRI2";
 921         };
 922
 923         pinctrl_nri3_default: nri3_default {
 924                 function = "NRI3";
 925                 groups = "NRI3";
 926         };
 927
 928         pinctrl_nri4_default: nri4_default {
 929                 function = "NRI4";
 930                 groups = "NRI4";
 931         };
 932
 933         pinctrl_nrts1_default: nrts1_default {
 934                 function = "NRTS1";
 935                 groups = "NRTS1";
 936         };
 937
 938         pinctrl_nrts2_default: nrts2_default {
 939                 function = "NRTS2";
 940                 groups = "NRTS2";
 941         };
 942
 943         pinctrl_nrts3_default: nrts3_default {
 944                 function = "NRTS3";
 945                 groups = "NRTS3";
 946         };
 947
 948         pinctrl_oscclk_default: oscclk_default {
 949                 function = "OSCCLK";
 950                 groups = "OSCCLK";
 951         };
 952
 953         pinctrl_pwm0_default: pwm0_default {
 954                 function = "PWM0";
 955                 groups = "PWM0";
 956         };
 957
 958         pinctrl_pwm1_default: pwm1_default {
 959                 function = "PWM1";
 960                 groups = "PWM1";
 961         };
 962
 963         pinctrl_pwm2_default: pwm2_default {
 964                 function = "PWM2";
 965                 groups = "PWM2";
 966         };
 967
 968         pinctrl_pwm3_default: pwm3_default {
 969                 function = "PWM3";
 970                 groups = "PWM3";
 971         };
 972
 973         pinctrl_pwm4_default: pwm4_default {
 974                 function = "PWM4";
 975                 groups = "PWM4";
 976         };
 977
 978         pinctrl_pwm5_default: pwm5_default {
 979                 function = "PWM5";
 980                 groups = "PWM5";
 981         };
 982
 983         pinctrl_pwm6_default: pwm6_default {
 984                 function = "PWM6";
 985                 groups = "PWM6";
 986         };
 987
 988         pinctrl_pwm7_default: pwm7_default {
 989                 function = "PWM7";
 990                 groups = "PWM7";
 991         };
 992
 993         pinctrl_rgmii1_default: rgmii1_default {
 994                 function = "RGMII1";
 995                 groups = "RGMII1";
 996         };
 997
 998         pinctrl_rgmii2_default: rgmii2_default {
 999                 function = "RGMII2";
1000                 groups = "RGMII2";
1001         };
1002
1003         pinctrl_rmii1_default: rmii1_default {
1004                 function = "RMII1";
1005                 groups = "RMII1";
1006         };
1007
1008         pinctrl_rmii2_default: rmii2_default {
1009                 function = "RMII2";
1010                 groups = "RMII2";
1011         };
1012
1013         pinctrl_rom16_default: rom16_default {
1014                 function = "ROM16";
1015                 groups = "ROM16";
1016         };
1017
1018         pinctrl_rom8_default: rom8_default {
1019                 function = "ROM8";
1020                 groups = "ROM8";
1021         };
1022
1023         pinctrl_romcs1_default: romcs1_default {
1024                 function = "ROMCS1";
1025                 groups = "ROMCS1";
1026         };
1027
1028         pinctrl_romcs2_default: romcs2_default {
1029                 function = "ROMCS2";
1030                 groups = "ROMCS2";
1031         };
1032
1033         pinctrl_romcs3_default: romcs3_default {
1034                 function = "ROMCS3";
1035                 groups = "ROMCS3";
1036         };
1037
1038         pinctrl_romcs4_default: romcs4_default {
1039                 function = "ROMCS4";
1040                 groups = "ROMCS4";
1041         };
1042
1043         pinctrl_rxd1_default: rxd1_default {
1044                 function = "RXD1";
1045                 groups = "RXD1";
1046         };
1047
1048         pinctrl_rxd2_default: rxd2_default {
1049                 function = "RXD2";
1050                 groups = "RXD2";
1051         };
1052
1053         pinctrl_rxd3_default: rxd3_default {
1054                 function = "RXD3";
1055                 groups = "RXD3";
1056         };
1057
1058         pinctrl_rxd4_default: rxd4_default {
1059                 function = "RXD4";
1060                 groups = "RXD4";
1061         };
1062
1063         pinctrl_salt1_default: salt1_default {
1064                 function = "SALT1";
1065                 groups = "SALT1";
1066         };
1067
1068         pinctrl_salt2_default: salt2_default {
1069                 function = "SALT2";
1070                 groups = "SALT2";
1071         };
1072
1073         pinctrl_salt3_default: salt3_default {
1074                 function = "SALT3";
1075                 groups = "SALT3";
1076         };
1077
1078         pinctrl_salt4_default: salt4_default {
1079                 function = "SALT4";
1080                 groups = "SALT4";
1081         };
1082
1083         pinctrl_sd1_default: sd1_default {
1084                 function = "SD1";
1085                 groups = "SD1";
1086         };
1087
1088         pinctrl_sd2_default: sd2_default {
1089                 function = "SD2";
1090                 groups = "SD2";
1091         };
1092
1093         pinctrl_sgpmck_default: sgpmck_default {
1094                 function = "SGPMCK";
1095                 groups = "SGPMCK";
1096         };
1097
1098         pinctrl_sgpmi_default: sgpmi_default {
1099                 function = "SGPMI";
1100                 groups = "SGPMI";
1101         };
1102
1103         pinctrl_sgpmld_default: sgpmld_default {
1104                 function = "SGPMLD";
1105                 groups = "SGPMLD";
1106         };
1107
1108         pinctrl_sgpmo_default: sgpmo_default {
1109                 function = "SGPMO";
1110                 groups = "SGPMO";
1111         };
1112
1113         pinctrl_sgpsck_default: sgpsck_default {
1114                 function = "SGPSCK";
1115                 groups = "SGPSCK";
1116         };
1117
1118         pinctrl_sgpsi0_default: sgpsi0_default {
1119                 function = "SGPSI0";
1120                 groups = "SGPSI0";
1121         };
1122
1123         pinctrl_sgpsi1_default: sgpsi1_default {
1124                 function = "SGPSI1";
1125                 groups = "SGPSI1";
1126         };
1127
1128         pinctrl_sgpsld_default: sgpsld_default {
1129                 function = "SGPSLD";
1130                 groups = "SGPSLD";
1131         };
1132
1133         pinctrl_sioonctrl_default: sioonctrl_default {
1134                 function = "SIOONCTRL";
1135                 groups = "SIOONCTRL";
1136         };
1137
1138         pinctrl_siopbi_default: siopbi_default {
1139                 function = "SIOPBI";
1140                 groups = "SIOPBI";
1141         };
1142
1143         pinctrl_siopbo_default: siopbo_default {
1144                 function = "SIOPBO";
1145                 groups = "SIOPBO";
1146         };
1147
1148         pinctrl_siopwreq_default: siopwreq_default {
1149                 function = "SIOPWREQ";
1150                 groups = "SIOPWREQ";
1151         };
1152
1153         pinctrl_siopwrgd_default: siopwrgd_default {
1154                 function = "SIOPWRGD";
1155                 groups = "SIOPWRGD";
1156         };
1157
1158         pinctrl_sios3_default: sios3_default {
1159                 function = "SIOS3";
1160                 groups = "SIOS3";
1161         };
1162
1163         pinctrl_sios5_default: sios5_default {
1164                 function = "SIOS5";
1165                 groups = "SIOS5";
1166         };
1167
1168         pinctrl_siosci_default: siosci_default {
1169                 function = "SIOSCI";
1170                 groups = "SIOSCI";
1171         };
1172
1173         pinctrl_spi1_default: spi1_default {
1174                 function = "SPI1";
1175                 groups = "SPI1";
1176         };
1177
1178         pinctrl_spi1debug_default: spi1debug_default {
1179                 function = "SPI1DEBUG";
1180                 groups = "SPI1DEBUG";
1181         };
1182
1183         pinctrl_spi1passthru_default: spi1passthru_default {
1184                 function = "SPI1PASSTHRU";
1185                 groups = "SPI1PASSTHRU";
1186         };
1187
1188         pinctrl_spics1_default: spics1_default {
1189                 function = "SPICS1";
1190                 groups = "SPICS1";
1191         };
1192
1193         pinctrl_timer3_default: timer3_default {
1194                 function = "TIMER3";
1195                 groups = "TIMER3";
1196         };
1197
1198         pinctrl_timer4_default: timer4_default {
1199                 function = "TIMER4";
1200                 groups = "TIMER4";
1201         };
1202
1203         pinctrl_timer5_default: timer5_default {
1204                 function = "TIMER5";
1205                 groups = "TIMER5";
1206         };
1207
1208         pinctrl_timer6_default: timer6_default {
1209                 function = "TIMER6";
1210                 groups = "TIMER6";
1211         };
1212
1213         pinctrl_timer7_default: timer7_default {
1214                 function = "TIMER7";
1215                 groups = "TIMER7";
1216         };
1217
1218         pinctrl_timer8_default: timer8_default {
1219                 function = "TIMER8";
1220                 groups = "TIMER8";
1221         };
1222
1223         pinctrl_txd1_default: txd1_default {
1224                 function = "TXD1";
1225                 groups = "TXD1";
1226         };
1227
1228         pinctrl_txd2_default: txd2_default {
1229                 function = "TXD2";
1230                 groups = "TXD2";
1231         };
1232
1233         pinctrl_txd3_default: txd3_default {
1234                 function = "TXD3";
1235                 groups = "TXD3";
1236         };
1237
1238         pinctrl_txd4_default: txd4_default {
1239                 function = "TXD4";
1240                 groups = "TXD4";
1241         };
1242
1243         pinctrl_uart6_default: uart6_default {
1244                 function = "UART6";
1245                 groups = "UART6";
1246         };
1247
1248         pinctrl_usbcki_default: usbcki_default {
1249                 function = "USBCKI";
1250                 groups = "USBCKI";
1251         };
1252
1253         pinctrl_vgabios_rom_default: vgabios_rom_default {
1254                 function = "VGABIOS_ROM";
1255                 groups = "VGABIOS_ROM";
1256         };
1257
1258         pinctrl_vgahs_default: vgahs_default {
1259                 function = "VGAHS";
1260                 groups = "VGAHS";
1261         };
1262
1263         pinctrl_vgavs_default: vgavs_default {
1264                 function = "VGAVS";
1265                 groups = "VGAVS";
1266         };
1267
1268         pinctrl_vpi18_default: vpi18_default {
1269                 function = "VPI18";
1270                 groups = "VPI18";
1271         };
1272
1273         pinctrl_vpi24_default: vpi24_default {
1274                 function = "VPI24";
1275                 groups = "VPI24";
1276         };
1277
1278         pinctrl_vpi30_default: vpi30_default {
1279                 function = "VPI30";
1280                 groups = "VPI30";
1281         };
1282
1283         pinctrl_vpo12_default: vpo12_default {
1284                 function = "VPO12";
1285                 groups = "VPO12";
1286         };
1287
1288         pinctrl_vpo24_default: vpo24_default {
1289                 function = "VPO24";
1290                 groups = "VPO24";
1291         };
1292
1293         pinctrl_wdtrst1_default: wdtrst1_default {
1294                 function = "WDTRST1";
1295                 groups = "WDTRST1";
1296         };
1297
1298         pinctrl_wdtrst2_default: wdtrst2_default {
1299                 function = "WDTRST2";
1300                 groups = "WDTRST2";
1301         };
1302 };