arch/arm/boot/dts/aspeed-bmc-quanta-q71l.dts

   1 // SPDX-License-Identifier: GPL-2.0
   2 /dts-v1/;
   3 #include "aspeed-g4.dtsi"
   4 #include <dt-bindings/gpio/aspeed-gpio.h>
   5
   6 / {
   7         model = "Quanta Q71L BMC";
   8         compatible = "quanta,q71l-bmc", "aspeed,ast2400";
   9
  10         aliases {
  11                 i2c14 = &i2c_pcie2;
  12                 i2c15 = &i2c_pcie3;
  13                 i2c16 = &i2c_pcie6;
  14                 i2c17 = &i2c_pcie7;
  15                 i2c18 = &i2c_pcie1;
  16                 i2c19 = &i2c_pcie4;
  17                 i2c20 = &i2c_pcie5;
  18                 i2c21 = &i2c_pcie8;
  19                 i2c22 = &i2c_pcie9;
  20                 i2c23 = &i2c_pcie10;
  21                 i2c24 = &i2c_ssd1;
  22                 i2c25 = &i2c_ssd2;
  23                 i2c26 = &i2c_psu4;
  24                 i2c27 = &i2c_psu1;
  25                 i2c28 = &i2c_psu3;
  26                 i2c29 = &i2c_psu2;
  27         };
  28
  29         chosen {
  30                 stdout-path = &uart5;
  31                 bootargs = "console=ttyS4,115200 earlyprintk";
  32         };
  33
  34         memory@40000000 {
  35                 reg = <0x40000000 0x8000000>;
  36         };
  37
  38         reserved-memory {
  39                 #address-cells = <1>;
  40                 #size-cells = <1>;
  41                 ranges;
  42
  43                 vga_memory: framebuffer@47800000 {
  44                         no-map;
  45                         reg = <0x47800000 0x00800000>; /* 8MB */
  46                 };
  47         };
  48
  49         leds {
  50                 compatible = "gpio-leds";
  51
  52                 heartbeat {
  53                         gpios = <&gpio ASPEED_GPIO(B, 0) GPIO_ACTIVE_LOW>;
  54                 };
  55
  56                 power {
  57                         gpios = <&gpio ASPEED_GPIO(B, 2) GPIO_ACTIVE_LOW>;
  58                 };
  59
  60                 identify {
  61                         gpios = <&gpio ASPEED_GPIO(B, 3) GPIO_ACTIVE_LOW>;
  62                 };
  63         };
  64
  65         iio-hwmon {
  66                 compatible = "iio-hwmon";
  67                 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>,
  68                         <&adc 4>, <&adc 5>, <&adc 6>, <&adc 7>,
  69                         <&adc 8>, <&adc 9>, <&adc 10>;
  70         };
  71
  72         iio-hwmon-battery {
  73                 compatible = "iio-hwmon";
  74                 io-channels = <&adc 11>;
  75         };
  76
  77         i2c1mux: i2cmux {
  78                 compatible = "i2c-mux-gpio";
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 /* mux-gpios = <&sgpio 10 GPIO_ACTIVE_HIGH> */
  83                 i2c-parent = <&i2c1>;
  84         };
  85 };
  86
  87 &fmc {
  88         status = "okay";
  89         flash@0 {
  90                 status = "okay";
  91                 label = "bmc";
  92                 m25p,fast-read;
  93 #include "openbmc-flash-layout.dtsi"
  94         };
  95 };
  96
  97 &spi {
  98         status = "okay";
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&pinctrl_spi1_default>;
 101
 102         flash@0 {
 103                 status = "okay";
 104                 m25p,fast-read;
 105                 label = "pnor";
 106         };
 107 };
 108
 109 &pinctrl {
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&pinctrl_vgahs_default &pinctrl_vgavs_default
 112                         &pinctrl_ddcclk_default &pinctrl_ddcdat_default>;
 113 };
 114
 115 &ibt {
 116         status = "okay";
 117 };
 118
 119 &lpc_ctrl {
 120         status = "okay";
 121 };
 122
 123 &lpc_snoop {
 124         status = "okay";
 125         snoop-ports = <0x80>;
 126 };
 127
 128 &mac0 {
 129         status = "okay";
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&pinctrl_rmii1_default>;
 132         use-ncsi;
 133 };
 134
 135 &mac1 {
 136         status = "okay";
 137         pinctrl-names = "default";
 138         pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;
 139 };
 140
 141 &uart1 {
 142         status = "okay";
 143 };
 144
 145 &uart5 {
 146         status = "okay";
 147 };
 148
 149 &i2c0 {
 150         status = "okay";
 151 };
 152
 153 &i2c1 {
 154         status = "okay";
 155
 156         /* temp2 inlet */
 157         tmp75@4c {
 158                 compatible = "ti,tmp75";
 159                 reg = <0x4c>;
 160         };
 161
 162         /* temp3 */
 163         tmp75@4e {
 164                 compatible = "ti,tmp75";
 165                 reg = <0x4e>;
 166         };
 167
 168         /* temp1 */
 169         tmp75@4f {
 170                 compatible = "ti,tmp75";
 171                 reg = <0x4f>;
 172         };
 173
 174         /* Baseboard FRU */
 175         eeprom@54 {
 176                 compatible = "atmel,24c64";
 177                 reg = <0x54>;
 178         };
 179
 180         /* FP FRU */
 181         eeprom@57 {
 182                 compatible = "atmel,24c64";
 183                 reg = <0x57>;
 184         };
 185 };
 186
 187 &i2c2 {
 188         status = "okay";
 189
 190         /* 0: PCIe Slot 2,
 191          *    Slot 3,
 192          *    Slot 6,
 193          *    Slot 7
 194          */
 195         i2c-switch@74 {
 196                 compatible = "nxp,pca9546";
 197                 reg = <0x74>;
 198                 #address-cells = <1>;
 199                 #size-cells = <0>;
 200                 i2c-mux-idle-disconnect;  /* may use mux@77 next. */
 201
 202                 i2c_pcie2: i2c@0 {
 203                         #address-cells = <1>;
 204                         #size-cells = <0>;
 205                         reg = <0>;
 206                 };
 207
 208                 i2c_pcie3: i2c@1 {
 209                         #address-cells = <1>;
 210                         #size-cells = <0>;
 211                         reg = <1>;
 212                 };
 213
 214                 i2c_pcie6: i2c@2 {
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217                         reg = <2>;
 218                 };
 219
 220                 i2c_pcie7: i2c@3 {
 221                         #address-cells = <1>;
 222                         #size-cells = <0>;
 223                         reg = <3>;
 224                 };
 225         };
 226
 227         /* 0: PCIe Slot 1,
 228          *    Slot 4,
 229          *    Slot 5,
 230          *    Slot 8,
 231          *    Slot 9,
 232          *    Slot 10,
 233          *    SSD 1,
 234          *    SSD 2
 235          */
 236         i2c-switch@77 {
 237                 compatible = "nxp,pca9548";
 238                 #address-cells = <1>;
 239                 #size-cells = <0>;
 240                 reg = <0x77>;
 241                 i2c-mux-idle-disconnect;  /* may use mux@74 next. */
 242
 243                 i2c_pcie1: i2c@0 {
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246                         reg = <0>;
 247                 };
 248
 249                 i2c_pcie4: i2c@1 {
 250                         #address-cells = <1>;
 251                         #size-cells = <0>;
 252                         reg = <1>;
 253                 };
 254
 255                 i2c_pcie5: i2c@2 {
 256                         #address-cells = <1>;
 257                         #size-cells = <0>;
 258                         reg = <2>;
 259                 };
 260
 261                 i2c_pcie8: i2c@3 {
 262                         #address-cells = <1>;
 263                         #size-cells = <0>;
 264                         reg = <3>;
 265                 };
 266
 267                 i2c_pcie9: i2c@4 {
 268                         #address-cells = <1>;
 269                         #size-cells = <0>;
 270                         reg = <4>;
 271                 };
 272
 273                 i2c_pcie10: i2c@5 {
 274                         #address-cells = <1>;
 275                         #size-cells = <0>;
 276                         reg = <5>;
 277                 };
 278
 279                 i2c_ssd1: i2c@6 {
 280                         #address-cells = <1>;
 281                         #size-cells = <0>;
 282                         reg = <6>;
 283                 };
 284
 285                 i2c_ssd2: i2c@7 {
 286                         #address-cells = <1>;
 287                         #size-cells = <0>;
 288                         reg = <7>;
 289                 };
 290         };
 291 };
 292
 293 &i2c3 {
 294         status = "okay";
 295
 296         /* BIOS FRU */
 297         eeprom@56 {
 298                 compatible = "atmel,24c64";
 299                 reg = <0x56>;
 300         };
 301 };
 302
 303 &i2c4 {
 304         status = "okay";
 305 };
 306
 307 &i2c5 {
 308         status = "okay";
 309 };
 310
 311 &i2c6 {
 312         status = "okay";
 313 };
 314
 315 &i2c7 {
 316         status = "okay";
 317
 318         /* 0: PSU4
 319          *    PSU1
 320          *    PSU3
 321          *    PSU2
 322          */
 323         i2c-switch@70 {
 324                 compatible = "nxp,pca9546";
 325                 reg = <0x70>;
 326                 #address-cells = <1>;
 327                 #size-cells = <0>;
 328
 329                 i2c_psu4: i2c@0 {
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         reg = <0>;
 333
 334                         psu@59 {
 335                                 compatible = "pmbus";
 336                                 reg = <0x59>;
 337                         };
 338                 };
 339
 340                 i2c_psu1: i2c@1 {
 341                         #address-cells = <1>;
 342                         #size-cells = <0>;
 343                         reg = <1>;
 344
 345                         psu@58 {
 346                                 compatible = "pmbus";
 347                                 reg = <0x58>;
 348                         };
 349                 };
 350
 351                 i2c_psu3: i2c@2 {
 352                         #address-cells = <1>;
 353                         #size-cells = <0>;
 354                         reg = <2>;
 355
 356                         psu@58 {
 357                                 compatible = "pmbus";
 358                                 reg = <0x58>;
 359                         };
 360                 };
 361
 362                 i2c_psu2: i2c@3 {
 363                         #address-cells = <1>;
 364                         #size-cells = <0>;
 365                         reg = <3>;
 366
 367                         psu@59 {
 368                                 compatible = "pmbus";
 369                                 reg = <0x59>;
 370                         };
 371                 };
 372         };
 373
 374         /* PDB FRU */
 375         eeprom@52 {
 376                 compatible = "atmel,24c64";
 377                 reg = <0x52>;
 378         };
 379 };
 380
 381 &i2c8 {
 382         status = "okay";
 383
 384         /* BMC FRU */
 385         eeprom@50 {
 386                 compatible = "atmel,24c64";
 387                 reg = <0x50>;
 388         };
 389 };
 390
 391 &vuart {
 392         status = "okay";
 393 };
 394
 395 &wdt2 {
 396         status = "okay";
 397 };
 398
 399 &adc {
 400         status = "okay";
 401 };
 402
 403 &pwm_tacho {
 404         status = "okay";
 405
 406         pinctrl-names = "default";
 407         pinctrl-0 = <&pinctrl_pwm0_default
 408                 &pinctrl_pwm1_default
 409                 &pinctrl_pwm2_default
 410                 &pinctrl_pwm3_default>;
 411
 412         fan@0 {
 413                 reg = <0x00>;
 414                 aspeed,fan-tach-ch = /bits/ 8 <0x00>;
 415         };
 416
 417         fan@1 {
 418                 reg = <0x01>;
 419                 aspeed,fan-tach-ch = /bits/ 8 <0x01>;
 420         };
 421
 422         fan@2 {
 423                 reg = <0x02>;
 424                 aspeed,fan-tach-ch = /bits/ 8 <0x02>;
 425         };
 426
 427         fan@3 {
 428                 reg = <0x03>;
 429                 aspeed,fan-tach-ch = /bits/ 8 <0x03>;
 430         };
 431
 432         fan@4 {
 433                 reg = <0x00>;
 434                 aspeed,fan-tach-ch = /bits/ 8 <0x04>;
 435         };
 436
 437         fan@5 {
 438                 reg = <0x01>;
 439                 aspeed,fan-tach-ch = /bits/ 8 <0x05>;
 440         };
 441
 442         fan@6 {
 443                 reg = <0x02>;
 444                 aspeed,fan-tach-ch = /bits/ 8 <0x06>;
 445         };
 446
 447         fan@7 {
 448                 reg = <0x03>;
 449                 aspeed,fan-tach-ch = /bits/ 8 <0x07>;
 450         };
 451 };
 452
 453 &i2c1mux {
 454         i2c@0 {
 455                 reg = <0>;
 456                 #address-cells = <1>;
 457                 #size-cells = <0>;
 458
 459                 /* Memory Riser 1 FRU */
 460                 eeprom@50 {
 461                         compatible = "atmel,24c02";
 462                         reg = <0x50>;
 463                 };
 464
 465                 /* Memory Riser 2 FRU */
 466                 eeprom@51 {
 467                         compatible = "atmel,24c02";
 468                         reg = <0x51>;
 469                 };
 470
 471                 /* Memory Riser 3 FRU */
 472                 eeprom@52 {
 473                         compatible = "atmel,24c02";
 474                         reg = <0x52>;
 475                 };
 476
 477                 /* Memory Riser 4 FRU */
 478                 eeprom@53 {
 479                         compatible = "atmel,24c02";
 480                         reg = <0x53>;
 481                 };
 482         };
 483
 484         i2c@1 {
 485                 reg = <1>;
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488
 489                 /* Memory Riser 5 FRU */
 490                 eeprom@50 {
 491                         compatible = "atmel,24c02";
 492                         reg = <0x50>;
 493                 };
 494
 495                 /* Memory Riser 6 FRU */
 496                 eeprom@51 {
 497                         compatible = "atmel,24c02";
 498                         reg = <0x51>;
 499                 };
 500
 501                 /* Memory Riser 7 FRU */
 502                 eeprom@52 {
 503                         compatible = "atmel,24c02";
 504                         reg = <0x52>;
 505                 };
 506
 507                 /* Memory Riser 8 FRU */
 508                 eeprom@53 {
 509                         compatible = "atmel,24c02";
 510                         reg = <0x53>;
 511                 };
 512         };
 513 };