arch/arm/boot/dts/armada-xp.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada XP family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  * Ben Dooks <ben.dooks@codethink.co.uk>
  10  *
  11  * This file is dual-licensed: you can use it either under the terms
  12  * of the GPL or the X11 license, at your option. Note that this dual
  13  * licensing only applies to this file, and not this project as a
  14  * whole.
  15  *
  16  *  a) This file is free software; you can redistribute it and/or
  17  *     modify it under the terms of the GNU General Public License as
  18  *     published by the Free Software Foundation; either version 2 of the
  19  *     License, or (at your option) any later version.
  20  *
  21  *     This file is distributed in the hope that it will be useful
  22  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  *     GNU General Public License for more details.
  25  *
  26  * Or, alternatively
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  *
  49  * Contains definitions specific to the Armada XP SoC that are not
  50  * common to all Armada SoCs.
  51  */
  52
  53 #include "armada-370-xp.dtsi"
  54
  55 / {
  56         model = "Marvell Armada XP family SoC";
  57         compatible = "marvell,armadaxp", "marvell,armada-370-xp";
  58
  59         aliases {
  60                 serial2 = &uart2;
  61                 serial3 = &uart3;
  62         };
  63
  64         soc {
  65                 compatible = "marvell,armadaxp-mbus", "simple-bus";
  66
  67                 bootrom {
  68                         compatible = "marvell,bootrom";
  69                         reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
  70                 };
  71
  72                 internal-regs {
  73                         sdramc@1400 {
  74                                 compatible = "marvell,armada-xp-sdram-controller";
  75                                 reg = <0x1400 0x500>;
  76                         };
  77
  78                         L2: l2-cache {
  79                                 compatible = "marvell,aurora-system-cache";
  80                                 reg = <0x08000 0x1000>;
  81                                 cache-id-part = <0x100>;
  82                                 cache-level = <2>;
  83                                 cache-unified;
  84                                 wt-override;
  85                         };
  86
  87                         i2c0: i2c@11000 {
  88                                 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
  89                                 reg = <0x11000 0x100>;
  90                         };
  91
  92                         i2c1: i2c@11100 {
  93                                 compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
  94                                 reg = <0x11100 0x100>;
  95                         };
  96
  97                         uart2: serial@12200 {
  98                                 compatible = "snps,dw-apb-uart";
  99                                 pinctrl-0 = <&uart2_pins>;
 100                                 pinctrl-names = "default";
 101                                 reg = <0x12200 0x100>;
 102                                 reg-shift = <2>;
 103                                 interrupts = <43>;
 104                                 reg-io-width = <1>;
 105                                 clocks = <&coreclk 0>;
 106                                 status = "disabled";
 107                         };
 108
 109                         uart3: serial@12300 {
 110                                 compatible = "snps,dw-apb-uart";
 111                                 pinctrl-0 = <&uart3_pins>;
 112                                 pinctrl-names = "default";
 113                                 reg = <0x12300 0x100>;
 114                                 reg-shift = <2>;
 115                                 interrupts = <44>;
 116                                 reg-io-width = <1>;
 117                                 clocks = <&coreclk 0>;
 118                                 status = "disabled";
 119                         };
 120
 121                         system-controller@18200 {
 122                                 compatible = "marvell,armada-370-xp-system-controller";
 123                                 reg = <0x18200 0x500>;
 124                         };
 125
 126                         gateclk: clock-gating-control@18220 {
 127                                 compatible = "marvell,armada-xp-gating-clock";
 128                                 reg = <0x18220 0x4>;
 129                                 clocks = <&coreclk 0>;
 130                                 #clock-cells = <1>;
 131                         };
 132
 133                         coreclk: mvebu-sar@18230 {
 134                                 compatible = "marvell,armada-xp-core-clock";
 135                                 reg = <0x18230 0x08>;
 136                                 #clock-cells = <1>;
 137                         };
 138
 139                         thermal@182b0 {
 140                                 compatible = "marvell,armadaxp-thermal";
 141                                 reg = <0x182b0 0x4
 142                                         0x184d0 0x4>;
 143                                 status = "okay";
 144                         };
 145
 146                         cpuclk: clock-complex@18700 {
 147                                 #clock-cells = <1>;
 148                                 compatible = "marvell,armada-xp-cpu-clock";
 149                                 reg = <0x18700 0x24>, <0x1c054 0x10>;
 150                                 clocks = <&coreclk 1>;
 151                         };
 152
 153                         interrupt-controller@20a00 {
 154                               reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 155                         };
 156
 157                         timer@20300 {
 158                                 compatible = "marvell,armada-xp-timer";
 159                                 clocks = <&coreclk 2>, <&refclk>;
 160                                 clock-names = "nbclk", "fixed";
 161                         };
 162
 163                         watchdog@20300 {
 164                                 compatible = "marvell,armada-xp-wdt";
 165                                 clocks = <&coreclk 2>, <&refclk>;
 166                                 clock-names = "nbclk", "fixed";
 167                         };
 168
 169                         cpurst@20800 {
 170                                 compatible = "marvell,armada-370-cpu-reset";
 171                                 reg = <0x20800 0x20>;
 172                         };
 173
 174                         cpu-config@21000 {
 175                                 compatible = "marvell,armada-xp-cpu-config";
 176                                 reg = <0x21000 0x8>;
 177                         };
 178
 179                         eth2: ethernet@30000 {
 180                                 compatible = "marvell,armada-xp-neta";
 181                                 reg = <0x30000 0x4000>;
 182                                 interrupts = <12>;
 183                                 clocks = <&gateclk 2>;
 184                                 status = "disabled";
 185                         };
 186
 187                         usb@50000 {
 188                                 clocks = <&gateclk 18>;
 189                         };
 190
 191                         usb@51000 {
 192                                 clocks = <&gateclk 19>;
 193                         };
 194
 195                         usb@52000 {
 196                                 compatible = "marvell,orion-ehci";
 197                                 reg = <0x52000 0x500>;
 198                                 interrupts = <47>;
 199                                 clocks = <&gateclk 20>;
 200                                 status = "disabled";
 201                         };
 202
 203                         xor@60900 {
 204                                 compatible = "marvell,orion-xor";
 205                                 reg = <0x60900 0x100
 206                                        0x60b00 0x100>;
 207                                 clocks = <&gateclk 22>;
 208                                 status = "okay";
 209
 210                                 xor10 {
 211                                         interrupts = <51>;
 212                                         dmacap,memcpy;
 213                                         dmacap,xor;
 214                                 };
 215                                 xor11 {
 216                                         interrupts = <52>;
 217                                         dmacap,memcpy;
 218                                         dmacap,xor;
 219                                         dmacap,memset;
 220                                 };
 221                         };
 222
 223                         ethernet@70000 {
 224                                 compatible = "marvell,armada-xp-neta";
 225                         };
 226
 227                         ethernet@74000 {
 228                                 compatible = "marvell,armada-xp-neta";
 229                         };
 230
 231                         crypto@90000 {
 232                                 compatible = "marvell,armada-xp-crypto";
 233                                 reg = <0x90000 0x10000>;
 234                                 reg-names = "regs";
 235                                 interrupts = <48>, <49>;
 236                                 clocks = <&gateclk 23>, <&gateclk 23>;
 237                                 clock-names = "cesa0", "cesa1";
 238                                 marvell,crypto-srams = <&crypto_sram0>,
 239                                                        <&crypto_sram1>;
 240                                 marvell,crypto-sram-size = <0x800>;
 241                         };
 242
 243                         bm: bm@c0000 {
 244                                 compatible = "marvell,armada-380-neta-bm";
 245                                 reg = <0xc0000 0xac>;
 246                                 clocks = <&gateclk 13>;
 247                                 internal-mem = <&bm_bppi>;
 248                                 status = "disabled";
 249                         };
 250
 251                         xor@f0900 {
 252                                 compatible = "marvell,orion-xor";
 253                                 reg = <0xF0900 0x100
 254                                        0xF0B00 0x100>;
 255                                 clocks = <&gateclk 28>;
 256                                 status = "okay";
 257
 258                                 xor00 {
 259                                         interrupts = <94>;
 260                                         dmacap,memcpy;
 261                                         dmacap,xor;
 262                                 };
 263                                 xor01 {
 264                                         interrupts = <95>;
 265                                         dmacap,memcpy;
 266                                         dmacap,xor;
 267                                         dmacap,memset;
 268                                 };
 269                         };
 270                 };
 271
 272                 crypto_sram0: sa-sram0 {
 273                         compatible = "mmio-sram";
 274                         reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
 275                         clocks = <&gateclk 23>;
 276                         #address-cells = <1>;
 277                         #size-cells = <1>;
 278                         ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
 279                 };
 280
 281                 crypto_sram1: sa-sram1 {
 282                         compatible = "mmio-sram";
 283                         reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
 284                         clocks = <&gateclk 23>;
 285                         #address-cells = <1>;
 286                         #size-cells = <1>;
 287                         ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
 288                 };
 289
 290                 bm_bppi: bm-bppi {
 291                         compatible = "mmio-sram";
 292                         reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
 293                         ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
 294                         #address-cells = <1>;
 295                         #size-cells = <1>;
 296                         clocks = <&gateclk 13>;
 297                         no-memory-wc;
 298                         status = "disabled";
 299                 };
 300         };
 301
 302         clocks {
 303                 /* 25 MHz reference crystal */
 304                 refclk: oscillator {
 305                         compatible = "fixed-clock";
 306                         #clock-cells = <0>;
 307                         clock-frequency = <25000000>;
 308                 };
 309         };
 310 };
 311
 312 &pinctrl {
 313         ge0_gmii_pins: ge0-gmii-pins {
 314                 marvell,pins =
 315                      "mpp0",  "mpp1",  "mpp2",  "mpp3",
 316                      "mpp4",  "mpp5",  "mpp6",  "mpp7",
 317                      "mpp8",  "mpp9",  "mpp10", "mpp11",
 318                      "mpp12", "mpp13", "mpp14", "mpp15",
 319                      "mpp16", "mpp17", "mpp18", "mpp19",
 320                      "mpp20", "mpp21", "mpp22", "mpp23";
 321                 marvell,function = "ge0";
 322         };
 323
 324         ge0_rgmii_pins: ge0-rgmii-pins {
 325                 marvell,pins =
 326                      "mpp0", "mpp1", "mpp2", "mpp3",
 327                      "mpp4", "mpp5", "mpp6", "mpp7",
 328                      "mpp8", "mpp9", "mpp10", "mpp11";
 329                 marvell,function = "ge0";
 330         };
 331
 332         ge1_rgmii_pins: ge1-rgmii-pins {
 333                 marvell,pins =
 334                      "mpp12", "mpp13", "mpp14", "mpp15",
 335                      "mpp16", "mpp17", "mpp18", "mpp19",
 336                      "mpp20", "mpp21", "mpp22", "mpp23";
 337                 marvell,function = "ge1";
 338         };
 339
 340         sdio_pins: sdio-pins {
 341                 marvell,pins = "mpp30", "mpp31", "mpp32",
 342                                "mpp33", "mpp34", "mpp35";
 343                 marvell,function = "sd0";
 344         };
 345
 346         spi0_pins: spi0-pins {
 347                 marvell,pins = "mpp36", "mpp37",
 348                                "mpp38", "mpp39";
 349                 marvell,function = "spi0";
 350         };
 351
 352         spi1_pins: spi1-pins {
 353                 marvell,pins = "mpp13", "mpp14",
 354                                "mpp16", "mpp17";
 355                 marvell,function = "spi1";
 356         };
 357
 358         uart2_pins: uart2-pins {
 359                 marvell,pins = "mpp42", "mpp43";
 360                 marvell,function = "uart2";
 361         };
 362
 363         uart3_pins: uart3-pins {
 364                 marvell,pins = "mpp44", "mpp45";
 365                 marvell,function = "uart3";
 366         };
 367 };
 368
 369 &spi0 {
 370         compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
 371         pinctrl-0 = <&spi0_pins>;
 372         pinctrl-names = "default";
 373 };
 374
 375 &spi1 {
 376         compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
 377         pinctrl-0 = <&spi1_pins>;
 378         pinctrl-names = "default";
 379 };