arch/arm/boot/dts/armada-xp-98dx3236.dtsi

   1 /*
   2  * Device Tree Include file for Marvell 98dx3236 family SoC
   3  *
   4  * Copyright (C) 2016 Allied Telesis Labs
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  *
  44  * Contains definitions specific to the 98dx3236 SoC that are not
  45  * common to all Armada XP SoCs.
  46  */
  47
  48 #include "armada-370-xp.dtsi"
  49
  50 / {
  51         #address-cells = <2>;
  52         #size-cells = <2>;
  53
  54         model = "Marvell 98DX3236 SoC";
  55         compatible = "marvell,armadaxp-98dx3236", "marvell,armada-370-xp";
  56
  57         aliases {
  58                 gpio0 = &gpio0;
  59                 gpio1 = &gpio1;
  60                 gpio2 = &gpio2;
  61         };
  62
  63         cpus {
  64                 #address-cells = <1>;
  65                 #size-cells = <0>;
  66                 enable-method = "marvell,98dx3236-smp";
  67
  68                 cpu@0 {
  69                         device_type = "cpu";
  70                         compatible = "marvell,sheeva-v7";
  71                         reg = <0>;
  72                         clocks = <&cpuclk 0>;
  73                         clock-latency = <1000000>;
  74                 };
  75         };
  76
  77         soc {
  78                 compatible = "marvell,armadaxp-mbus", "simple-bus";
  79
  80                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
  81                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
  82                           MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
  83                           MBUS_ID(0x03, 0x00) 0 0 0xa8000000 0x4000000
  84                           MBUS_ID(0x08, 0x00) 0 0 0xac000000 0x100000>;
  85
  86                 bootrom {
  87                         compatible = "marvell,bootrom";
  88                         reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
  89                 };
  90
  91                 /*
  92                  * 98DX3236 has 1 x1 PCIe unit Gen2.0
  93                  */
  94                 pciec: pcie-controller@82000000 {
  95                         compatible = "marvell,armada-xp-pcie";
  96                         status = "disabled";
  97                         device_type = "pci";
  98
  99                         #address-cells = <3>;
 100                         #size-cells = <2>;
 101
 102                         msi-parent = <&mpic>;
 103                         bus-range = <0x00 0xff>;
 104
 105                         ranges =
 106                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
 107                                 0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
 108                                 0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */>;
 109
 110                         pcie1: pcie@1,0 {
 111                                 device_type = "pci";
 112                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 113                                 reg = <0x0800 0 0 0 0>;
 114                                 #address-cells = <3>;
 115                                 #size-cells = <2>;
 116                                 #interrupt-cells = <1>;
 117                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 118                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 119                                 interrupt-map-mask = <0 0 0 0>;
 120                                 interrupt-map = <0 0 0 0 &mpic 58>;
 121                                 marvell,pcie-port = <0>;
 122                                 marvell,pcie-lane = <0>;
 123                                 clocks = <&gateclk 5>;
 124                                 status = "disabled";
 125                         };
 126                 };
 127
 128                 internal-regs {
 129                         sdramc@1400 {
 130                                 compatible = "marvell,armada-xp-sdram-controller";
 131                                 reg = <0x1400 0x500>;
 132                         };
 133
 134                         L2: l2-cache@8000 {
 135                                 compatible = "marvell,aurora-system-cache";
 136                                 reg = <0x08000 0x1000>;
 137                                 cache-id-part = <0x100>;
 138                                 cache-level = <2>;
 139                                 cache-unified;
 140                                 wt-override;
 141                         };
 142
 143                         gpio0: gpio@18100 {
 144                                 compatible = "marvell,orion-gpio";
 145                                 reg = <0x18100 0x40>;
 146                                 ngpios = <32>;
 147                                 gpio-controller;
 148                                 #gpio-cells = <2>;
 149                                 interrupt-controller;
 150                                 #interrupt-cells = <2>;
 151                                 interrupts = <82>, <83>, <84>, <85>;
 152                         };
 153
 154                         /* does not exist */
 155                         gpio1: gpio@18140 {
 156                                 compatible = "marvell,orion-gpio";
 157                                 reg = <0x18140 0x40>;
 158                                 status = "disabled";
 159                         };
 160
 161                         gpio2: gpio@18180 { /* rework some properties */
 162                                 compatible = "marvell,orion-gpio";
 163                                 reg = <0x18180 0x40>;
 164                                 ngpios = <1>; /* only gpio #32 */
 165                                 gpio-controller;
 166                                 #gpio-cells = <2>;
 167                                 interrupt-controller;
 168                                 #interrupt-cells = <2>;
 169                                 interrupts = <87>;
 170                         };
 171
 172                         systemc: system-controller@18200 {
 173                                 compatible = "marvell,armada-370-xp-system-controller";
 174                                 reg = <0x18200 0x500>;
 175                         };
 176
 177                         gateclk: clock-gating-control@18220 {
 178                                 compatible = "marvell,mv98dx3236-gating-clock";
 179                                 reg = <0x18220 0x4>;
 180                                 clocks = <&coreclk 0>;
 181                                 #clock-cells = <1>;
 182                         };
 183
 184                         cpuclk: clock-complex@18700 {
 185                                 #clock-cells = <1>;
 186                                 compatible = "marvell,mv98dx3236-cpu-clock";
 187                                 reg = <0x18700 0x24>, <0x1c054 0x10>;
 188                                 clocks = <&coreclk 1>;
 189                         };
 190
 191                         corediv-clock@18740 {
 192                                 status = "disabled";
 193                         };
 194
 195                         cpu-config@21000 {
 196                                 compatible = "marvell,armada-xp-cpu-config";
 197                                 reg = <0x21000 0x8>;
 198                         };
 199
 200                         ethernet@70000 {
 201                                 compatible = "marvell,armada-xp-neta";
 202                         };
 203
 204                         ethernet@74000 {
 205                                 compatible = "marvell,armada-xp-neta";
 206                         };
 207
 208                         xor1: xor@f0800 {
 209                                 compatible = "marvell,orion-xor";
 210                                 reg = <0xf0800 0x100
 211                                        0xf0a00 0x100>;
 212                                 clocks = <&gateclk 22>;
 213                                 status = "okay";
 214
 215                                 xor10 {
 216                                         interrupts = <51>;
 217                                         dmacap,memcpy;
 218                                         dmacap,xor;
 219                                 };
 220                                 xor11 {
 221                                         interrupts = <52>;
 222                                         dmacap,memcpy;
 223                                         dmacap,xor;
 224                                         dmacap,memset;
 225                                 };
 226                         };
 227
 228                         nand: nand@d0000 {
 229                                 clocks = <&dfx_coredivclk 0>;
 230                         };
 231
 232                         xor0: xor@f0900 {
 233                                 compatible = "marvell,orion-xor";
 234                                 reg = <0xF0900 0x100
 235                                        0xF0B00 0x100>;
 236                                 clocks = <&gateclk 28>;
 237                                 status = "okay";
 238
 239                                 xor00 {
 240                                         interrupts = <94>;
 241                                         dmacap,memcpy;
 242                                         dmacap,xor;
 243                                 };
 244                                 xor01 {
 245                                         interrupts = <95>;
 246                                         dmacap,memcpy;
 247                                         dmacap,xor;
 248                                         dmacap,memset;
 249                                 };
 250                         };
 251                 };
 252
 253                 dfx: dfx-server@ac000000 {
 254                         compatible = "marvell,dfx-server", "simple-bus";
 255                         #address-cells = <1>;
 256                         #size-cells = <1>;
 257                         ranges = <0 MBUS_ID(0x08, 0x00) 0 0x100000>;
 258                         reg = <MBUS_ID(0x08, 0x00) 0 0x100000>;
 259
 260                         coreclk: mvebu-sar@f8204 {
 261                                 compatible = "marvell,mv98dx3236-core-clock";
 262                                 reg = <0xf8204 0x4>;
 263                                 #clock-cells = <1>;
 264                         };
 265
 266                         dfx_coredivclk: corediv-clock@f8268 {
 267                                 compatible = "marvell,mv98dx3236-corediv-clock";
 268                                 reg = <0xf8268 0xc>;
 269                                 #clock-cells = <1>;
 270                                 clocks = <&mainpll>;
 271                                 clock-output-names = "nand";
 272                         };
 273                 };
 274
 275                 switch: switch@a8000000 {
 276                         compatible = "simple-bus";
 277                         #address-cells = <1>;
 278                         #size-cells = <1>;
 279                         ranges = <0 MBUS_ID(0x03, 0x00) 0 0x100000>;
 280
 281                         pp0: packet-processor@0 {
 282                                 compatible = "marvell,prestera-98dx3236";
 283                                 reg = <0 0x4000000>;
 284                                 interrupts = <33>, <34>, <35>;
 285                                 dfx = <&dfx>;
 286                         };
 287                 };
 288         };
 289
 290         clocks {
 291                 /* 25 MHz reference crystal */
 292                 refclk: oscillator {
 293                         compatible = "fixed-clock";
 294                         #clock-cells = <0>;
 295                         clock-frequency = <25000000>;
 296                 };
 297         };
 298 };
 299
 300 &i2c0 {
 301         compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
 302         reg = <0x11000 0x100>;
 303 };
 304
 305 &i2c1 {
 306         compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
 307         reg = <0x11100 0x100>;
 308 };
 309
 310 &mpic {
 311         reg = <0x20a00 0x2d0>, <0x21070 0x58>;
 312 };
 313
 314 &rtc {
 315         status = "disabled";
 316 };
 317
 318 &timer {
 319         compatible = "marvell,armada-xp-timer";
 320         clocks = <&coreclk 2>, <&refclk>;
 321         clock-names = "nbclk", "fixed";
 322 };
 323
 324 &watchdog {
 325         compatible = "marvell,armada-xp-wdt";
 326         clocks = <&coreclk 2>, <&refclk>;
 327         clock-names = "nbclk", "fixed";
 328 };
 329
 330 &cpurst {
 331         reg = <0x20800 0x20>;
 332 };
 333
 334 &usb0 {
 335         clocks = <&gateclk 18>;
 336 };
 337
 338 &usb1 {
 339         clocks = <&gateclk 19>;
 340 };
 341
 342 &pinctrl {
 343         compatible = "marvell,98dx3236-pinctrl";
 344
 345         spi0_pins: spi0-pins {
 346                 marvell,pins = "mpp0", "mpp1",
 347                                "mpp2", "mpp3";
 348                 marvell,function = "spi0";
 349         };
 350 };
 351
 352 &spi0 {
 353         compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
 354         pinctrl-0 = <&spi0_pins>;
 355         pinctrl-names = "default";
 356 };
 357
 358 &sdio {
 359         status = "disabled";
 360 };
 361