arch/arm/boot/dts/armada-388-clearfog.dts

   1 /*
   2  * Device Tree file for SolidRun Clearfog Pro revision A1 rev 2.0 (88F6828)
   3  *
   4  *  Copyright (C) 2015 Russell King
   5  *
   6  * This board is in development; the contents of this file work with
   7  * the A1 rev 2.0 of the board, which does not represent final
   8  * production board.  Things will change, don't expect this file to
   9  * remain compatible info the future.
  10  *
  11  * This file is dual-licensed: you can use it either under the terms
  12  * of the GPL or the X11 license, at your option. Note that this dual
  13  * licensing only applies to this file, and not this project as a
  14  * whole.
  15  *
  16  *  a) This file is free software; you can redistribute it and/or
  17  *     modify it under the terms of the GNU General Public License
  18  *     version 2 as published by the Free Software Foundation.
  19  *
  20  *     This file is distributed in the hope that it will be useful,
  21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *     GNU General Public License for more details.
  24  *
  25  * Or, alternatively,
  26  *
  27  *  b) Permission is hereby granted, free of charge, to any person
  28  *     obtaining a copy of this software and associated documentation
  29  *     files (the "Software"), to deal in the Software without
  30  *     restriction, including without limitation the rights to use,
  31  *     copy, modify, merge, publish, distribute, sublicense, and/or
  32  *     sell copies of the Software, and to permit persons to whom the
  33  *     Software is furnished to do so, subject to the following
  34  *     conditions:
  35  *
  36  *     The above copyright notice and this permission notice shall be
  37  *     included in all copies or substantial portions of the Software.
  38  *
  39  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46  *     OTHER DEALINGS IN THE SOFTWARE.
  47  */
  48
  49 /dts-v1/;
  50 #include "armada-388-clearfog.dtsi"
  51
  52 / {
  53         model = "SolidRun Clearfog A1";
  54         compatible = "solidrun,clearfog-a1", "marvell,armada388",
  55                 "marvell,armada385", "marvell,armada380";
  56
  57         soc {
  58                 internal-regs {
  59                         usb3@f0000 {
  60                                 /* CON2, nearest CPU, USB2 only. */
  61                                 status = "okay";
  62                         };
  63                 };
  64
  65                 pcie-controller {
  66                         pcie@3,0 {
  67                                 /* Port 2, Lane 0. CON2, nearest CPU. */
  68                                 reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
  69                                 status = "okay";
  70                         };
  71                 };
  72         };
  73
  74         dsa@0 {
  75                 status = "disabled";
  76
  77                 compatible = "marvell,dsa";
  78                 dsa,ethernet = <&eth1>;
  79                 dsa,mii-bus = <&mdio>;
  80                 pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
  81                 pinctrl-names = "default";
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 switch@0 {
  86                         #address-cells = <1>;
  87                         #size-cells = <0>;
  88                         reg = <4 0>;
  89
  90                         port@0 {
  91                                 reg = <0>;
  92                                 label = "lan5";
  93                         };
  94
  95                         port@1 {
  96                                 reg = <1>;
  97                                 label = "lan4";
  98                         };
  99
 100                         port@2 {
 101                                 reg = <2>;
 102                                 label = "lan3";
 103                         };
 104
 105                         port@3 {
 106                                 reg = <3>;
 107                                 label = "lan2";
 108                         };
 109
 110                         port@4 {
 111                                 reg = <4>;
 112                                 label = "lan1";
 113                         };
 114
 115                         port@5 {
 116                                 reg = <5>;
 117                                 label = "cpu";
 118                         };
 119
 120                         port@6 {
 121                                 /* 88E1512 external phy */
 122                                 reg = <6>;
 123                                 label = "lan6";
 124                                 fixed-link {
 125                                         speed = <1000>;
 126                                         full-duplex;
 127                                 };
 128                         };
 129                 };
 130         };
 131
 132         gpio-keys {
 133                 compatible = "gpio-keys";
 134                 pinctrl-0 = <&rear_button_pins>;
 135                 pinctrl-names = "default";
 136
 137                 button_0 {
 138                         /* The rear SW3 button */
 139                         label = "Rear Button";
 140                         gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 141                         linux,can-disable;
 142                         linux,code = <BTN_0>;
 143                 };
 144         };
 145 };
 146
 147 &eth1 {
 148         /* ethernet@30000 */
 149         fixed-link {
 150                 speed = <1000>;
 151                 full-duplex;
 152         };
 153 };
 154
 155 &expander0 {
 156         /*
 157          * PCA9655 GPIO expander:
 158          *  0-CON3 CLKREQ#
 159          *  1-CON3 PERST#
 160          *  2-CON2 PERST#
 161          *  3-CON3 W_DISABLE
 162          *  4-CON2 CLKREQ#
 163          *  5-USB3 overcurrent
 164          *  6-USB3 power
 165          *  7-CON2 W_DISABLE
 166          *  8-JP4 P1
 167          *  9-JP4 P4
 168          * 10-JP4 P5
 169          * 11-m.2 DEVSLP
 170          * 12-SFP_LOS
 171          * 13-SFP_TX_FAULT
 172          * 14-SFP_TX_DISABLE
 173          * 15-SFP_MOD_DEF0
 174          */
 175         pcie2_0_clkreq {
 176                 gpio-hog;
 177                 gpios = <4 GPIO_ACTIVE_LOW>;
 178                 input;
 179                 line-name = "pcie2.0-clkreq";
 180         };
 181         pcie2_0_w_disable {
 182                 gpio-hog;
 183                 gpios = <7 GPIO_ACTIVE_LOW>;
 184                 output-low;
 185                 line-name = "pcie2.0-w-disable";
 186         };
 187 };
 188
 189 &mdio {
 190         status = "okay";
 191
 192         switch@4 {
 193                 compatible = "marvell,mv88e6085";
 194                 #address-cells = <1>;
 195                 #size-cells = <0>;
 196                 reg = <4>;
 197                 pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
 198                 pinctrl-names = "default";
 199
 200                 ports {
 201                         #address-cells = <1>;
 202                         #size-cells = <0>;
 203
 204                         port@0 {
 205                                 reg = <0>;
 206                                 label = "lan5";
 207                         };
 208
 209                         port@1 {
 210                                 reg = <1>;
 211                                 label = "lan4";
 212                         };
 213
 214                         port@2 {
 215                                 reg = <2>;
 216                                 label = "lan3";
 217                         };
 218
 219                         port@3 {
 220                                 reg = <3>;
 221                                 label = "lan2";
 222                         };
 223
 224                         port@4 {
 225                                 reg = <4>;
 226                                 label = "lan1";
 227                         };
 228
 229                         port@5 {
 230                                 reg = <5>;
 231                                 label = "cpu";
 232                                 ethernet = <&eth1>;
 233                                 fixed-link {
 234                                         speed = <1000>;
 235                                         full-duplex;
 236                                 };
 237                         };
 238
 239                         port@6 {
 240                                 /* 88E1512 external phy */
 241                                 reg = <6>;
 242                                 label = "lan6";
 243                                 fixed-link {
 244                                         speed = <1000>;
 245                                         full-duplex;
 246                                 };
 247                         };
 248                 };
 249         };
 250 };
 251
 252 &pinctrl {
 253         clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
 254                 marvell,pins = "mpp46";
 255                 marvell,function = "ref";
 256         };
 257         clearfog_dsa0_pins: clearfog-dsa0-pins {
 258                 marvell,pins = "mpp23", "mpp41";
 259                 marvell,function = "gpio";
 260         };
 261         clearfog_spi1_cs_pins: spi1-cs-pins {
 262                 marvell,pins = "mpp55";
 263                 marvell,function = "spi1";
 264         };
 265         rear_button_pins: rear-button-pins {
 266                 marvell,pins = "mpp34";
 267                 marvell,function = "gpio";
 268         };
 269 };
 270
 271 &spi1 {
 272         /*
 273          * Add SPI CS pins for clearfog:
 274          * CS0: W25Q32 (not populated on uSOM)
 275          * CS1:
 276          * CS2: mikrobus
 277          */
 278         pinctrl-0 = <&spi1_pins &clearfog_spi1_cs_pins &mikro_spi_pins>;
 279 };