arch/arm/boot/dts/armada-385-db.dts

   1 /*
   2  * Device Tree file for Marvell Armada 385 evaluation board
   3  * (DB-88F6820)
   4  *
   5  *  Copyright (C) 2014 Marvell
   6  *
   7  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2.  This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 /dts-v1/;
  15 #include "armada-385.dtsi"
  16
  17 / {
  18         model = "Marvell Armada 385 Development Board";
  19         compatible = "marvell,a385-db", "marvell,armada385", "marvell,armada38x";
  20
  21         chosen {
  22                 bootargs = "console=ttyS0,115200 earlyprintk";
  23         };
  24
  25         memory {
  26                 device_type = "memory";
  27                 reg = <0x00000000 0x10000000>; /* 256 MB */
  28         };
  29
  30         soc {
  31                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
  32                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
  33
  34                 internal-regs {
  35                         spi@10600 {
  36                                 status = "okay";
  37
  38                                 spi-flash@0 {
  39                                         #address-cells = <1>;
  40                                         #size-cells = <1>;
  41                                         compatible = "w25q32";
  42                                         reg = <0>; /* Chip select 0 */
  43                                         spi-max-frequency = <108000000>;
  44                                 };
  45                         };
  46
  47                         i2c@11000 {
  48                                 status = "okay";
  49                                 clock-frequency = <100000>;
  50                         };
  51
  52                         i2c@11100 {
  53                                 status = "okay";
  54                                 clock-frequency = <100000>;
  55                         };
  56
  57                         serial@12000 {
  58                                 clock-frequency = <200000000>;
  59                                 status = "okay";
  60                         };
  61
  62                         ethernet@30000 {
  63                                 status = "okay";
  64                                 phy = <&phy1>;
  65                                 phy-mode = "rgmii-id";
  66                         };
  67
  68                         ethernet@70000 {
  69                                 status = "okay";
  70                                 phy = <&phy0>;
  71                                 phy-mode = "rgmii-id";
  72                         };
  73
  74                         mdio {
  75                                 phy0: ethernet-phy@0 {
  76                                         reg = <0>;
  77                                 };
  78
  79                                 phy1: ethernet-phy@1 {
  80                                         reg = <1>;
  81                                 };
  82                         };
  83
  84                         flash@d0000 {
  85                                 status = "okay";
  86                                 num-cs = <1>;
  87                                 marvell,nand-keep-config;
  88                                 marvell,nand-enable-arbiter;
  89                                 nand-on-flash-bbt;
  90
  91                                 partition@0 {
  92                                         label = "U-Boot";
  93                                         reg = <0 0x800000>;
  94                                 };
  95                                 partition@800000 {
  96                                         label = "Linux";
  97                                         reg = <0x800000 0x800000>;
  98                                 };
  99                                 partition@1000000 {
 100                                         label = "Filesystem";
 101                                         reg = <0x1000000 0x3f000000>;
 102                                 };
 103                         };
 104                 };
 105
 106                 pcie-controller {
 107                         status = "okay";
 108                         /*
 109                          * The two PCIe units are accessible through
 110                          * standard PCIe slots on the board.
 111                          */
 112                         pcie@1,0 {
 113                                 /* Port 0, Lane 0 */
 114                                 status = "okay";
 115                         };
 116                         pcie@2,0 {
 117                                 /* Port 1, Lane 0 */
 118                                 status = "okay";
 119                         };
 120                 };
 121         };
 122 };