Merge branches 'arm/rockchip', 'arm/exynos', 'arm/smmu', 'x86/vt-d', 'x86/amd', ...
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / armada-375.dtsi
1 /*
2  * Device Tree Include file for Marvell Armada 375 family SoC
3  *
4  * Copyright (C) 2014 Marvell
5  *
6  * Gregory CLEMENT <gregory.clement@free-electrons.com>
7  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8  *
9  * This file is dual-licensed: you can use it either under the terms
10  * of the GPL or the X11 license, at your option. Note that this dual
11  * licensing only applies to this file, and not this project as a
12  * whole.
13  *
14  *  a) This file is free software; you can redistribute it and/or
15  *     modify it under the terms of the GNU General Public License as
16  *     published by the Free Software Foundation; either version 2 of the
17  *     License, or (at your option) any later version.
18  *
19  *     This file is distributed in the hope that it will be useful
20  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
21  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22  *     GNU General Public License for more details.
23  *
24  * Or, alternatively
25  *
26  *  b) Permission is hereby granted, free of charge, to any person
27  *     obtaining a copy of this software and associated documentation
28  *     files (the "Software"), to deal in the Software without
29  *     restriction, including without limitation the rights to use
30  *     copy, modify, merge, publish, distribute, sublicense, and/or
31  *     sell copies of the Software, and to permit persons to whom the
32  *     Software is furnished to do so, subject to the following
33  *     conditions:
34  *
35  *     The above copyright notice and this permission notice shall be
36  *     included in all copies or substantial portions of the Software.
37  *
38  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45  *     OTHER DEALINGS IN THE SOFTWARE.
46  */
47
48 #include "skeleton.dtsi"
49 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 #include <dt-bindings/interrupt-controller/irq.h>
51 #include <dt-bindings/phy/phy.h>
52
53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
54
55 / {
56         model = "Marvell Armada 375 family SoC";
57         compatible = "marvell,armada375";
58
59         aliases {
60                 gpio0 = &gpio0;
61                 gpio1 = &gpio1;
62                 gpio2 = &gpio2;
63                 serial0 = &uart0;
64                 serial1 = &uart1;
65         };
66
67         clocks {
68                 /* 2 GHz fixed main PLL */
69                 mainpll: mainpll {
70                         compatible = "fixed-clock";
71                         #clock-cells = <0>;
72                         clock-frequency = <1000000000>;
73                 };
74                 /* 25 MHz reference crystal */
75                 refclk: oscillator {
76                         compatible = "fixed-clock";
77                         #clock-cells = <0>;
78                         clock-frequency = <25000000>;
79                 };
80         };
81
82         cpus {
83                 #address-cells = <1>;
84                 #size-cells = <0>;
85                 enable-method = "marvell,armada-375-smp";
86
87                 cpu@0 {
88                         device_type = "cpu";
89                         compatible = "arm,cortex-a9";
90                         reg = <0>;
91                 };
92                 cpu@1 {
93                         device_type = "cpu";
94                         compatible = "arm,cortex-a9";
95                         reg = <1>;
96                 };
97         };
98
99         pmu {
100                 compatible = "arm,cortex-a9-pmu";
101                 interrupts-extended = <&mpic 3>;
102         };
103
104         soc {
105                 compatible = "marvell,armada375-mbus", "simple-bus";
106                 #address-cells = <2>;
107                 #size-cells = <1>;
108                 controller = <&mbusc>;
109                 interrupt-parent = <&gic>;
110                 pcie-mem-aperture = <0xe0000000 0x8000000>;
111                 pcie-io-aperture  = <0xe8000000 0x100000>;
112
113                 bootrom {
114                         compatible = "marvell,bootrom";
115                         reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
116                 };
117
118                 devbus-bootcs {
119                         compatible = "marvell,mvebu-devbus";
120                         reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
121                         ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
122                         #address-cells = <1>;
123                         #size-cells = <1>;
124                         clocks = <&coreclk 0>;
125                         status = "disabled";
126                 };
127
128                 devbus-cs0 {
129                         compatible = "marvell,mvebu-devbus";
130                         reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
131                         ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
132                         #address-cells = <1>;
133                         #size-cells = <1>;
134                         clocks = <&coreclk 0>;
135                         status = "disabled";
136                 };
137
138                 devbus-cs1 {
139                         compatible = "marvell,mvebu-devbus";
140                         reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
141                         ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
142                         #address-cells = <1>;
143                         #size-cells = <1>;
144                         clocks = <&coreclk 0>;
145                         status = "disabled";
146                 };
147
148                 devbus-cs2 {
149                         compatible = "marvell,mvebu-devbus";
150                         reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
151                         ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
152                         #address-cells = <1>;
153                         #size-cells = <1>;
154                         clocks = <&coreclk 0>;
155                         status = "disabled";
156                 };
157
158                 devbus-cs3 {
159                         compatible = "marvell,mvebu-devbus";
160                         reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
161                         ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
162                         #address-cells = <1>;
163                         #size-cells = <1>;
164                         clocks = <&coreclk 0>;
165                         status = "disabled";
166                 };
167
168                 internal-regs {
169                         compatible = "simple-bus";
170                         #address-cells = <1>;
171                         #size-cells = <1>;
172                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
173
174                         L2: cache-controller@8000 {
175                                 compatible = "arm,pl310-cache";
176                                 reg = <0x8000 0x1000>;
177                                 cache-unified;
178                                 cache-level = <2>;
179                         };
180
181                         scu@c000 {
182                                 compatible = "arm,cortex-a9-scu";
183                                 reg = <0xc000 0x58>;
184                         };
185
186                         timer@c600 {
187                                 compatible = "arm,cortex-a9-twd-timer";
188                                 reg = <0xc600 0x20>;
189                                 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
190                                 clocks = <&coreclk 2>;
191                         };
192
193                         gic: interrupt-controller@d000 {
194                                 compatible = "arm,cortex-a9-gic";
195                                 #interrupt-cells = <3>;
196                                 #size-cells = <0>;
197                                 interrupt-controller;
198                                 reg = <0xd000 0x1000>,
199                                       <0xc100 0x100>;
200                         };
201
202                         mdio {
203                                 #address-cells = <1>;
204                                 #size-cells = <0>;
205                                 compatible = "marvell,orion-mdio";
206                                 reg = <0xc0054 0x4>;
207                                 clocks = <&gateclk 19>;
208                         };
209
210                         /* Network controller */
211                         ethernet@f0000 {
212                                 compatible = "marvell,armada-375-pp2";
213                                 reg = <0xf0000 0xa000>, /* Packet Processor regs */
214                                       <0xc0000 0x3060>, /* LMS regs */
215                                       <0xc4000 0x100>,  /* eth0 regs */
216                                       <0xc5000 0x100>;  /* eth1 regs */
217                                 clocks = <&gateclk 3>, <&gateclk 19>;
218                                 clock-names = "pp_clk", "gop_clk";
219                                 status = "disabled";
220
221                                 eth0: eth0@c4000 {
222                                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
223                                         port-id = <0>;
224                                         status = "disabled";
225                                 };
226
227                                 eth1: eth1@c5000 {
228                                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
229                                         port-id = <1>;
230                                         status = "disabled";
231                                 };
232                         };
233
234                         rtc@10300 {
235                                 compatible = "marvell,orion-rtc";
236                                 reg = <0x10300 0x20>;
237                                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
238                         };
239
240                         spi0: spi@10600 {
241                                 compatible = "marvell,orion-spi";
242                                 reg = <0x10600 0x50>;
243                                 #address-cells = <1>;
244                                 #size-cells = <0>;
245                                 cell-index = <0>;
246                                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
247                                 clocks = <&coreclk 0>;
248                                 status = "disabled";
249                         };
250
251                         spi1: spi@10680 {
252                                 compatible = "marvell,orion-spi";
253                                 reg = <0x10680 0x50>;
254                                 #address-cells = <1>;
255                                 #size-cells = <0>;
256                                 cell-index = <1>;
257                                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
258                                 clocks = <&coreclk 0>;
259                                 status = "disabled";
260                         };
261
262                         i2c0: i2c@11000 {
263                                 compatible = "marvell,mv64xxx-i2c";
264                                 reg = <0x11000 0x20>;
265                                 #address-cells = <1>;
266                                 #size-cells = <0>;
267                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
268                                 timeout-ms = <1000>;
269                                 clocks = <&coreclk 0>;
270                                 status = "disabled";
271                         };
272
273                         i2c1: i2c@11100 {
274                                 compatible = "marvell,mv64xxx-i2c";
275                                 reg = <0x11100 0x20>;
276                                 #address-cells = <1>;
277                                 #size-cells = <0>;
278                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
279                                 timeout-ms = <1000>;
280                                 clocks = <&coreclk 0>;
281                                 status = "disabled";
282                         };
283
284                         uart0: serial@12000 {
285                                 compatible = "snps,dw-apb-uart";
286                                 reg = <0x12000 0x100>;
287                                 reg-shift = <2>;
288                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
289                                 reg-io-width = <1>;
290                                 clocks = <&coreclk 0>;
291                                 status = "disabled";
292                         };
293
294                         uart1: serial@12100 {
295                                 compatible = "snps,dw-apb-uart";
296                                 reg = <0x12100 0x100>;
297                                 reg-shift = <2>;
298                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
299                                 reg-io-width = <1>;
300                                 clocks = <&coreclk 0>;
301                                 status = "disabled";
302                         };
303
304                         pinctrl {
305                                 compatible = "marvell,mv88f6720-pinctrl";
306                                 reg = <0x18000 0x24>;
307
308                                 i2c0_pins: i2c0-pins {
309                                         marvell,pins = "mpp14",  "mpp15";
310                                         marvell,function = "i2c0";
311                                 };
312
313                                 i2c1_pins: i2c1-pins {
314                                         marvell,pins = "mpp61",  "mpp62";
315                                         marvell,function = "i2c1";
316                                 };
317
318                                 nand_pins: nand-pins {
319                                         marvell,pins = "mpp0", "mpp1", "mpp2",
320                                                 "mpp3", "mpp4", "mpp5",
321                                                 "mpp6", "mpp7", "mpp8",
322                                                 "mpp9", "mpp10", "mpp11",
323                                                 "mpp12", "mpp13";
324                                         marvell,function = "nand";
325                                 };
326
327                                 sdio_pins: sdio-pins {
328                                         marvell,pins = "mpp24",  "mpp25", "mpp26",
329                                                      "mpp27", "mpp28", "mpp29";
330                                         marvell,function = "sd";
331                                 };
332
333                                 spi0_pins: spi0-pins {
334                                         marvell,pins = "mpp0",  "mpp1", "mpp4",
335                                                      "mpp5", "mpp8", "mpp9";
336                                         marvell,function = "spi0";
337                                 };
338                         };
339
340                         gpio0: gpio@18100 {
341                                 compatible = "marvell,orion-gpio";
342                                 reg = <0x18100 0x40>;
343                                 ngpios = <32>;
344                                 gpio-controller;
345                                 #gpio-cells = <2>;
346                                 interrupt-controller;
347                                 #interrupt-cells = <2>;
348                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
349                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
350                                              <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
351                                              <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
352                         };
353
354                         gpio1: gpio@18140 {
355                                 compatible = "marvell,orion-gpio";
356                                 reg = <0x18140 0x40>;
357                                 ngpios = <32>;
358                                 gpio-controller;
359                                 #gpio-cells = <2>;
360                                 interrupt-controller;
361                                 #interrupt-cells = <2>;
362                                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
363                                              <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
364                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
365                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
366                         };
367
368                         gpio2: gpio@18180 {
369                                 compatible = "marvell,orion-gpio";
370                                 reg = <0x18180 0x40>;
371                                 ngpios = <3>;
372                                 gpio-controller;
373                                 #gpio-cells = <2>;
374                                 interrupt-controller;
375                                 #interrupt-cells = <2>;
376                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
377                         };
378
379                         system-controller@18200 {
380                                 compatible = "marvell,armada-375-system-controller";
381                                 reg = <0x18200 0x100>;
382                         };
383
384                         gateclk: clock-gating-control@18220 {
385                                 compatible = "marvell,armada-375-gating-clock";
386                                 reg = <0x18220 0x4>;
387                                 clocks = <&coreclk 0>;
388                                 #clock-cells = <1>;
389                         };
390
391                         usbcluster: usb-cluster@18400 {
392                                 compatible = "marvell,armada-375-usb-cluster";
393                                 reg = <0x18400 0x4>;
394                                 #phy-cells = <1>;
395                         };
396
397                         mbusc: mbus-controller@20000 {
398                                 compatible = "marvell,mbus-controller";
399                                 reg = <0x20000 0x100>, <0x20180 0x20>;
400                         };
401
402                         mpic: interrupt-controller@20a00 {
403                                 compatible = "marvell,mpic";
404                                 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
405                                 #interrupt-cells = <1>;
406                                 #size-cells = <1>;
407                                 interrupt-controller;
408                                 msi-controller;
409                                 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
410                         };
411
412                         timer@20300 {
413                                 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
414                                 reg = <0x20300 0x30>, <0x21040 0x30>;
415                                 interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
416                                                       <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
417                                                       <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
418                                                       <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
419                                                       <&mpic 5>,
420                                                       <&mpic 6>;
421                                 clocks = <&coreclk 0>, <&refclk>;
422                                 clock-names = "nbclk", "fixed";
423                         };
424
425                         watchdog@20300 {
426                                 compatible = "marvell,armada-375-wdt";
427                                 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
428                                 clocks = <&coreclk 0>, <&refclk>;
429                                 clock-names = "nbclk", "fixed";
430                         };
431
432                         cpurst@20800 {
433                                 compatible = "marvell,armada-370-cpu-reset";
434                                 reg = <0x20800 0x10>;
435                         };
436
437                         coherency-fabric@21010 {
438                                 compatible = "marvell,armada-375-coherency-fabric";
439                                 reg = <0x21010 0x1c>;
440                         };
441
442                         usb@50000 {
443                                 compatible = "marvell,orion-ehci";
444                                 reg = <0x50000 0x500>;
445                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
446                                 clocks = <&gateclk 18>;
447                                 phys = <&usbcluster PHY_TYPE_USB2>;
448                                 phy-names = "usb";
449                                 status = "disabled";
450                         };
451
452                         usb@54000 {
453                                 compatible = "marvell,orion-ehci";
454                                 reg = <0x54000 0x500>;
455                                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
456                                 clocks = <&gateclk 26>;
457                                 status = "disabled";
458                         };
459
460                         usb3@58000 {
461                                 compatible = "marvell,armada-375-xhci";
462                                 reg = <0x58000 0x20000>,<0x5b880 0x80>;
463                                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
464                                 clocks = <&gateclk 16>;
465                                 phys = <&usbcluster PHY_TYPE_USB3>;
466                                 phy-names = "usb";
467                                 status = "disabled";
468                         };
469
470                         xor@60800 {
471                                 compatible = "marvell,orion-xor";
472                                 reg = <0x60800 0x100
473                                        0x60A00 0x100>;
474                                 clocks = <&gateclk 22>;
475                                 status = "okay";
476
477                                 xor00 {
478                                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
479                                         dmacap,memcpy;
480                                         dmacap,xor;
481                                 };
482                                 xor01 {
483                                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
484                                         dmacap,memcpy;
485                                         dmacap,xor;
486                                         dmacap,memset;
487                                 };
488                         };
489
490                         xor@60900 {
491                                 compatible = "marvell,orion-xor";
492                                 reg = <0x60900 0x100
493                                        0x60b00 0x100>;
494                                 clocks = <&gateclk 23>;
495                                 status = "okay";
496
497                                 xor10 {
498                                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
499                                         dmacap,memcpy;
500                                         dmacap,xor;
501                                 };
502                                 xor11 {
503                                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
504                                         dmacap,memcpy;
505                                         dmacap,xor;
506                                         dmacap,memset;
507                                 };
508                         };
509
510                         sata@a0000 {
511                                 compatible = "marvell,orion-sata";
512                                 reg = <0xa0000 0x5000>;
513                                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
514                                 clocks = <&gateclk 14>, <&gateclk 20>;
515                                 clock-names = "0", "1";
516                                 status = "disabled";
517                         };
518
519                         nand@d0000 {
520                                 compatible = "marvell,armada370-nand";
521                                 reg = <0xd0000 0x54>;
522                                 #address-cells = <1>;
523                                 #size-cells = <1>;
524                                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
525                                 clocks = <&gateclk 11>;
526                                 status = "disabled";
527                         };
528
529                         mvsdio@d4000 {
530                                 compatible = "marvell,orion-sdio";
531                                 reg = <0xd4000 0x200>;
532                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
533                                 clocks = <&gateclk 17>;
534                                 bus-width = <4>;
535                                 cap-sdio-irq;
536                                 cap-sd-highspeed;
537                                 cap-mmc-highspeed;
538                                 status = "disabled";
539                         };
540
541                         thermal@e8078 {
542                                 compatible = "marvell,armada375-thermal";
543                                 reg = <0xe8078 0x4>, <0xe807c 0x8>;
544                                 status = "okay";
545                         };
546
547                         coreclk: mvebu-sar@e8204 {
548                                 compatible = "marvell,armada-375-core-clock";
549                                 reg = <0xe8204 0x04>;
550                                 #clock-cells = <1>;
551                         };
552
553                         coredivclk: corediv-clock@e8250 {
554                                 compatible = "marvell,armada-375-corediv-clock";
555                                 reg = <0xe8250 0xc>;
556                                 #clock-cells = <1>;
557                                 clocks = <&mainpll>;
558                                 clock-output-names = "nand";
559                         };
560                 };
561
562                 pcie-controller {
563                         compatible = "marvell,armada-370-pcie";
564                         status = "disabled";
565                         device_type = "pci";
566
567                         #address-cells = <3>;
568                         #size-cells = <2>;
569
570                         msi-parent = <&mpic>;
571                         bus-range = <0x00 0xff>;
572
573                         ranges =
574                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
575                                 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
576                                 0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
577                                 0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
578                                 0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
579                                 0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;
580
581                         pcie@1,0 {
582                                 device_type = "pci";
583                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
584                                 reg = <0x0800 0 0 0 0>;
585                                 #address-cells = <3>;
586                                 #size-cells = <2>;
587                                 #interrupt-cells = <1>;
588                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
589                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
590                                 interrupt-map-mask = <0 0 0 0>;
591                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
592                                 marvell,pcie-port = <0>;
593                                 marvell,pcie-lane = <0>;
594                                 clocks = <&gateclk 5>;
595                                 status = "disabled";
596                         };
597
598                         pcie@2,0 {
599                                 device_type = "pci";
600                                 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
601                                 reg = <0x1000 0 0 0 0>;
602                                 #address-cells = <3>;
603                                 #size-cells = <2>;
604                                 #interrupt-cells = <1>;
605                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
606                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
607                                 interrupt-map-mask = <0 0 0 0>;
608                                 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
609                                 marvell,pcie-port = <0>;
610                                 marvell,pcie-lane = <1>;
611                                 clocks = <&gateclk 6>;
612                                 status = "disabled";
613                         };
614
615                 };
616         };
617 };