arch/arm/boot/dts/armada-370-xp.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 370 and Armada XP SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  * Ben Dooks <ben.dooks@codethink.co.uk>
  10  *
  11  * This file is dual-licensed: you can use it either under the terms
  12  * of the GPL or the X11 license, at your option. Note that this dual
  13  * licensing only applies to this file, and not this project as a
  14  * whole.
  15  *
  16  *  a) This file is free software; you can redistribute it and/or
  17  *     modify it under the terms of the GNU General Public License as
  18  *     published by the Free Software Foundation; either version 2 of the
  19  *     License, or (at your option) any later version.
  20  *
  21  *     This file is distributed in the hope that it will be useful,
  22  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  *     GNU General Public License for more details.
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  *
  49  * This file contains the definitions that are common to the Armada
  50  * 370 and Armada XP SoC.
  51  */
  52
  53 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
  54
  55 / {
  56         model = "Marvell Armada 370 and XP SoC";
  57         compatible = "marvell,armada-370-xp";
  58
  59         aliases {
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62         };
  63
  64         cpus {
  65                 #address-cells = <1>;
  66                 #size-cells = <0>;
  67                 cpu@0 {
  68                         compatible = "marvell,sheeva-v7";
  69                         device_type = "cpu";
  70                         reg = <0>;
  71                 };
  72         };
  73
  74         pmu {
  75                 compatible = "arm,cortex-a9-pmu";
  76                 interrupts-extended = <&mpic 3>;
  77         };
  78
  79         soc {
  80                 #address-cells = <2>;
  81                 #size-cells = <1>;
  82                 controller = <&mbusc>;
  83                 interrupt-parent = <&mpic>;
  84                 pcie-mem-aperture = <0xf8000000 0x7e00000>;
  85                 pcie-io-aperture  = <0xffe00000 0x100000>;
  86
  87                 devbus_bootcs: devbus-bootcs {
  88                         compatible = "marvell,mvebu-devbus";
  89                         reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
  90                         ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
  91                         #address-cells = <1>;
  92                         #size-cells = <1>;
  93                         clocks = <&coreclk 0>;
  94                         status = "disabled";
  95                 };
  96
  97                 devbus_cs0: devbus-cs0 {
  98                         compatible = "marvell,mvebu-devbus";
  99                         reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
 100                         ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
 101                         #address-cells = <1>;
 102                         #size-cells = <1>;
 103                         clocks = <&coreclk 0>;
 104                         status = "disabled";
 105                 };
 106
 107                 devbus_cs1: devbus-cs1 {
 108                         compatible = "marvell,mvebu-devbus";
 109                         reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
 110                         ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
 111                         #address-cells = <1>;
 112                         #size-cells = <1>;
 113                         clocks = <&coreclk 0>;
 114                         status = "disabled";
 115                 };
 116
 117                 devbus_cs2: devbus-cs2 {
 118                         compatible = "marvell,mvebu-devbus";
 119                         reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
 120                         ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
 121                         #address-cells = <1>;
 122                         #size-cells = <1>;
 123                         clocks = <&coreclk 0>;
 124                         status = "disabled";
 125                 };
 126
 127                 devbus_cs3: devbus-cs3 {
 128                         compatible = "marvell,mvebu-devbus";
 129                         reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
 130                         ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
 131                         #address-cells = <1>;
 132                         #size-cells = <1>;
 133                         clocks = <&coreclk 0>;
 134                         status = "disabled";
 135                 };
 136
 137                 internal-regs {
 138                         compatible = "simple-bus";
 139                         #address-cells = <1>;
 140                         #size-cells = <1>;
 141                         ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
 142
 143                         rtc: rtc@10300 {
 144                                 compatible = "marvell,orion-rtc";
 145                                 reg = <0x10300 0x20>;
 146                                 interrupts = <50>;
 147                         };
 148
 149                         i2c0: i2c@11000 {
 150                                 compatible = "marvell,mv64xxx-i2c";
 151                                 #address-cells = <1>;
 152                                 #size-cells = <0>;
 153                                 interrupts = <31>;
 154                                 timeout-ms = <1000>;
 155                                 clocks = <&coreclk 0>;
 156                                 status = "disabled";
 157                         };
 158
 159                         i2c1: i2c@11100 {
 160                                 compatible = "marvell,mv64xxx-i2c";
 161                                 #address-cells = <1>;
 162                                 #size-cells = <0>;
 163                                 interrupts = <32>;
 164                                 timeout-ms = <1000>;
 165                                 clocks = <&coreclk 0>;
 166                                 status = "disabled";
 167                         };
 168
 169                         uart0: serial@12000 {
 170                                 compatible = "snps,dw-apb-uart";
 171                                 reg = <0x12000 0x100>;
 172                                 reg-shift = <2>;
 173                                 interrupts = <41>;
 174                                 reg-io-width = <1>;
 175                                 clocks = <&coreclk 0>;
 176                                 status = "disabled";
 177                         };
 178
 179                         uart1: serial@12100 {
 180                                 compatible = "snps,dw-apb-uart";
 181                                 reg = <0x12100 0x100>;
 182                                 reg-shift = <2>;
 183                                 interrupts = <42>;
 184                                 reg-io-width = <1>;
 185                                 clocks = <&coreclk 0>;
 186                                 status = "disabled";
 187                         };
 188
 189                         pinctrl: pin-ctrl@18000 {
 190                                 reg = <0x18000 0x38>;
 191                         };
 192
 193                         coredivclk: corediv-clock@18740 {
 194                                 compatible = "marvell,armada-370-corediv-clock";
 195                                 reg = <0x18740 0xc>;
 196                                 #clock-cells = <1>;
 197                                 clocks = <&mainpll>;
 198                                 clock-output-names = "nand";
 199                         };
 200
 201                         mbusc: mbus-controller@20000 {
 202                                 compatible = "marvell,mbus-controller";
 203                                 reg = <0x20000 0x100>, <0x20180 0x20>,
 204                                       <0x20250 0x8>;
 205                         };
 206
 207                         mpic: interrupt-controller@20a00 {
 208                                 compatible = "marvell,mpic";
 209                                 #interrupt-cells = <1>;
 210                                 #size-cells = <1>;
 211                                 interrupt-controller;
 212                                 msi-controller;
 213                         };
 214
 215                         coherencyfab: coherency-fabric@20200 {
 216                                 compatible = "marvell,coherency-fabric";
 217                                 reg = <0x20200 0xb0>, <0x21010 0x1c>;
 218                         };
 219
 220                         timer: timer@20300 {
 221                                 reg = <0x20300 0x30>, <0x21040 0x30>;
 222                                 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
 223                         };
 224
 225                         watchdog: watchdog@20300 {
 226                                 reg = <0x20300 0x34>, <0x20704 0x4>;
 227                         };
 228
 229                         cpurst: cpurst@20800 {
 230                                 compatible = "marvell,armada-370-cpu-reset";
 231                                 reg = <0x20800 0x8>;
 232                         };
 233
 234                         pmsu: pmsu@22000 {
 235                                 compatible = "marvell,armada-370-pmsu";
 236                                 reg = <0x22000 0x1000>;
 237                         };
 238
 239                         usb0: usb@50000 {
 240                                 compatible = "marvell,orion-ehci";
 241                                 reg = <0x50000 0x500>;
 242                                 interrupts = <45>;
 243                                 status = "disabled";
 244                         };
 245
 246                         usb1: usb@51000 {
 247                                 compatible = "marvell,orion-ehci";
 248                                 reg = <0x51000 0x500>;
 249                                 interrupts = <46>;
 250                                 status = "disabled";
 251                         };
 252
 253                         eth0: ethernet@70000 {
 254                                 reg = <0x70000 0x4000>;
 255                                 interrupts = <8>;
 256                                 clocks = <&gateclk 4>;
 257                                 status = "disabled";
 258                         };
 259
 260                         mdio: mdio@72004 {
 261                                 #address-cells = <1>;
 262                                 #size-cells = <0>;
 263                                 compatible = "marvell,orion-mdio";
 264                                 reg = <0x72004 0x4>;
 265                                 clocks = <&gateclk 4>;
 266                         };
 267
 268                         eth1: ethernet@74000 {
 269                                 reg = <0x74000 0x4000>;
 270                                 interrupts = <10>;
 271                                 clocks = <&gateclk 3>;
 272                                 status = "disabled";
 273                         };
 274
 275                         sata: sata@a0000 {
 276                                 compatible = "marvell,armada-370-sata";
 277                                 reg = <0xa0000 0x5000>;
 278                                 interrupts = <55>;
 279                                 clocks = <&gateclk 15>, <&gateclk 30>;
 280                                 clock-names = "0", "1";
 281                                 status = "disabled";
 282                         };
 283
 284                         nand: nand@d0000 {
 285                                 compatible = "marvell,armada370-nand";
 286                                 reg = <0xd0000 0x54>;
 287                                 #address-cells = <1>;
 288                                 #size-cells = <1>;
 289                                 interrupts = <113>;
 290                                 clocks = <&coredivclk 0>;
 291                                 status = "disabled";
 292                         };
 293
 294                         sdio: mvsdio@d4000 {
 295                                 compatible = "marvell,orion-sdio";
 296                                 reg = <0xd4000 0x200>;
 297                                 interrupts = <54>;
 298                                 clocks = <&gateclk 17>;
 299                                 bus-width = <4>;
 300                                 cap-sdio-irq;
 301                                 cap-sd-highspeed;
 302                                 cap-mmc-highspeed;
 303                                 status = "disabled";
 304                         };
 305                 };
 306
 307                 spi0: spi@10600 {
 308                         reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */
 309                               <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */
 310                               <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
 311                               <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
 312                               <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */
 313                               <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */
 314                               <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */
 315                               <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */
 316                               <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */
 317                         #address-cells = <1>;
 318                         #size-cells = <0>;
 319                         cell-index = <0>;
 320                         interrupts = <30>;
 321                         clocks = <&coreclk 0>;
 322                         status = "disabled";
 323                 };
 324
 325                 spi1: spi@10680 {
 326                         reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x28>, /* control */
 327                               <MBUS_ID(0x01, 0x1a) 0 0xffffffff>, /* CS0 */
 328                               <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
 329                               <MBUS_ID(0x01, 0x9a) 0 0xffffffff>, /* CS2 */
 330                               <MBUS_ID(0x01, 0xda) 0 0xffffffff>, /* CS3 */
 331                               <MBUS_ID(0x01, 0x1b) 0 0xffffffff>, /* CS4 */
 332                               <MBUS_ID(0x01, 0x5b) 0 0xffffffff>, /* CS5 */
 333                               <MBUS_ID(0x01, 0x9b) 0 0xffffffff>, /* CS6 */
 334                               <MBUS_ID(0x01, 0xdb) 0 0xffffffff>; /* CS7 */
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         cell-index = <1>;
 338                         interrupts = <92>;
 339                         clocks = <&coreclk 0>;
 340                         status = "disabled";
 341                 };
 342         };
 343
 344         clocks {
 345                 /* 2 GHz fixed main PLL */
 346                 mainpll: mainpll {
 347                         compatible = "fixed-clock";
 348                         #clock-cells = <0>;
 349                         clock-frequency = <2000000000>;
 350                 };
 351         };
 352  };