Merge tag 'iwlwifi-next-for-kalle-2016-07-01' of git://git.kernel.org/pub/scm/linux...
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / arm-realview-pbx.dtsi
1 /*
2  * Copyright 2016 Linaro Ltd
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a copy
5  * of this software and associated documentation files (the "Software"), to deal
6  * in the Software without restriction, including without limitation the rights
7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8  * copies of the Software, and to permit persons to whom the Software is
9  * furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20  * THE SOFTWARE.
21  */
22
23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "skeleton.dtsi"
26
27 / {
28         compatible = "arm,realview-pbx";
29
30         chosen { };
31
32         aliases {
33                 serial0 = &serial0;
34                 serial1 = &serial1;
35                 serial2 = &serial2;
36                 serial3 = &serial3;
37                 i2c0 = &i2c;
38         };
39
40         memory {
41                 /* 128 MiB memory @ 0x0 */
42                 reg = <0x00000000 0x08000000>;
43         };
44
45         /* The voltage to the MMC card is hardwired at 3.3V */
46         vmmc: fixedregulator@0 {
47                 compatible = "regulator-fixed";
48                 regulator-name = "vmmc";
49                 regulator-min-microvolt = <3300000>;
50                 regulator-max-microvolt = <3300000>;
51                 regulator-boot-on;
52         };
53
54         veth: fixedregulator@0 {
55                 compatible = "regulator-fixed";
56                 regulator-name = "veth";
57                 regulator-min-microvolt = <3300000>;
58                 regulator-max-microvolt = <3300000>;
59                 regulator-boot-on;
60         };
61
62         xtal24mhz: xtal24mhz@24M {
63                 #clock-cells = <0>;
64                 compatible = "fixed-clock";
65                 clock-frequency = <24000000>;
66         };
67
68         refclk32khz: refclk32khz {
69                 #clock-cells = <0>;
70                 compatible = "fixed-clock";
71                 clock-frequency = <32768>;
72         };
73
74         timclk: timclk@1M {
75                 #clock-cells = <0>;
76                 compatible = "fixed-factor-clock";
77                 clock-div = <24>;
78                 clock-mult = <1>;
79                 clocks = <&xtal24mhz>;
80         };
81
82         mclk: mclk@24M {
83                 #clock-cells = <0>;
84                 compatible = "fixed-factor-clock";
85                 clock-div = <1>;
86                 clock-mult = <1>;
87                 clocks = <&xtal24mhz>;
88         };
89
90         kmiclk: kmiclk@24M {
91                 #clock-cells = <0>;
92                 compatible = "fixed-factor-clock";
93                 clock-div = <1>;
94                 clock-mult = <1>;
95                 clocks = <&xtal24mhz>;
96         };
97
98         sspclk: sspclk@24M {
99                 #clock-cells = <0>;
100                 compatible = "fixed-factor-clock";
101                 clock-div = <1>;
102                 clock-mult = <1>;
103                 clocks = <&xtal24mhz>;
104         };
105
106         uartclk: uartclk@24M {
107                 #clock-cells = <0>;
108                 compatible = "fixed-factor-clock";
109                 clock-div = <1>;
110                 clock-mult = <1>;
111                 clocks = <&xtal24mhz>;
112         };
113
114         wdogclk: wdogclk@24M {
115                 #clock-cells = <0>;
116                 compatible = "fixed-factor-clock";
117                 clock-div = <1>;
118                 clock-mult = <1>;
119                 clocks = <&xtal24mhz>;
120         };
121
122         /* FIXME: this actually hangs off the PLL clocks */
123         pclk: pclk@0 {
124                 #clock-cells = <0>;
125                 compatible = "fixed-clock";
126                 clock-frequency = <0>;
127         };
128
129         flash0@40000000 {
130                 /* 2 * 32MiB NOR Flash memory */
131                 compatible = "arm,versatile-flash", "cfi-flash";
132                 reg = <0x40000000 0x04000000>;
133                 bank-width = <4>;
134         };
135
136         flash1@44000000 {
137                 /* 2 * 32MiB NOR Flash memory */
138                 compatible = "arm,versatile-flash", "cfi-flash";
139                 reg = <0x44000000 0x04000000>;
140                 bank-width = <4>;
141         };
142
143         /* SMSC 9118 ethernet with PHY and EEPROM */
144         ethernet: ethernet@4e000000 {
145                 compatible = "smsc,lan9118", "smsc,lan9115";
146                 reg = <0x4e000000 0x10000>;
147                 phy-mode = "mii";
148                 reg-io-width = <4>;
149                 smsc,irq-active-high;
150                 smsc,irq-push-pull;
151                 vdd33a-supply = <&veth>;
152                 vddvario-supply = <&veth>;
153         };
154
155         usb: usb@4f000000 {
156                 compatible = "nxp,usb-isp1761";
157                 reg = <0x4f000000 0x20000>;
158                 port1-otg;
159         };
160
161         soc: soc@0 {
162                 compatible = "arm,realview-pbx-soc", "simple-bus";
163                 #address-cells = <1>;
164                 #size-cells = <1>;
165                 regmap = <&syscon>;
166                 ranges;
167
168                 syscon: syscon@10000000 {
169                         compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
170                         reg = <0x10000000 0x1000>;
171
172                         led@08.0 {
173                                 compatible = "register-bit-led";
174                                 offset = <0x08>;
175                                 mask = <0x01>;
176                                 label = "versatile:0";
177                                 linux,default-trigger = "heartbeat";
178                                 default-state = "on";
179                         };
180                         led@08.1 {
181                                 compatible = "register-bit-led";
182                                 offset = <0x08>;
183                                 mask = <0x02>;
184                                 label = "versatile:1";
185                                 linux,default-trigger = "mmc0";
186                                 default-state = "off";
187                         };
188                         led@08.2 {
189                                 compatible = "register-bit-led";
190                                 offset = <0x08>;
191                                 mask = <0x04>;
192                                 label = "versatile:2";
193                                 linux,default-trigger = "cpu0";
194                                 default-state = "off";
195                         };
196                         led@08.3 {
197                                 compatible = "register-bit-led";
198                                 offset = <0x08>;
199                                 mask = <0x08>;
200                                 label = "versatile:3";
201                                 default-state = "off";
202                         };
203                         led@08.4 {
204                                 compatible = "register-bit-led";
205                                 offset = <0x08>;
206                                 mask = <0x10>;
207                                 label = "versatile:4";
208                                 default-state = "off";
209                         };
210                         led@08.5 {
211                                 compatible = "register-bit-led";
212                                 offset = <0x08>;
213                                 mask = <0x20>;
214                                 label = "versatile:5";
215                                 default-state = "off";
216                         };
217                         led@08.6 {
218                                 compatible = "register-bit-led";
219                                 offset = <0x08>;
220                                 mask = <0x40>;
221                                 label = "versatile:6";
222                                 default-state = "off";
223                         };
224                         led@08.7 {
225                                 compatible = "register-bit-led";
226                                 offset = <0x08>;
227                                 mask = <0x80>;
228                                 label = "versatile:7";
229                                 default-state = "off";
230                         };
231                         oscclk0: osc0@0c {
232                                 compatible = "arm,syscon-icst307";
233                                 #clock-cells = <0>;
234                                 lock-offset = <0x20>;
235                                 vco-offset = <0x0C>;
236                                 clocks = <&xtal24mhz>;
237                         };
238                         oscclk1: osc1@10 {
239                                 compatible = "arm,syscon-icst307";
240                                 #clock-cells = <0>;
241                                 lock-offset = <0x20>;
242                                 vco-offset = <0x10>;
243                                 clocks = <&xtal24mhz>;
244                         };
245                         oscclk2: osc2@14 {
246                                 compatible = "arm,syscon-icst307";
247                                 #clock-cells = <0>;
248                                 lock-offset = <0x20>;
249                                 vco-offset = <0x14>;
250                                 clocks = <&xtal24mhz>;
251                         };
252                         oscclk3: osc3@18 {
253                                 compatible = "arm,syscon-icst307";
254                                 #clock-cells = <0>;
255                                 lock-offset = <0x20>;
256                                 vco-offset = <0x18>;
257                                 clocks = <&xtal24mhz>;
258                         };
259                         oscclk4: osc4@1c {
260                                 compatible = "arm,syscon-icst307";
261                                 #clock-cells = <0>;
262                                 lock-offset = <0x20>;
263                                 vco-offset = <0x1c>;
264                                 clocks = <&xtal24mhz>;
265                         };
266                 };
267
268                 sp810_syscon0: sysctl@10001000 {
269                         compatible = "arm,sp810", "arm,primecell";
270                         reg = <0x10001000 0x1000>;
271                         clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
272                         clock-names = "refclk", "timclk", "apb_pclk";
273                         #clock-cells = <1>;
274                         clock-output-names = "timerclk0",
275                                              "timerclk1",
276                                              "timerclk2",
277                                              "timerclk3";
278                         assigned-clocks = <&sp810_syscon0 0>,
279                                           <&sp810_syscon0 1>,
280                                           <&sp810_syscon0 2>,
281                                           <&sp810_syscon0 3>;
282                         assigned-clock-parents = <&timclk>,
283                                                <&timclk>,
284                                                <&timclk>,
285                                                <&timclk>;
286                 };
287
288                 i2c: i2c@10002000 {
289                         #address-cells = <1>;
290                         #size-cells = <0>;
291                         compatible = "arm,versatile-i2c";
292                         reg = <0x10002000 0x1000>;
293
294                         rtc@68 {
295                                 compatible = "dallas,ds1338";
296                                 reg = <0x68>;
297                         };
298                 };
299
300                 serial0: serial@10009000 {
301                         compatible = "arm,pl011", "arm,primecell";
302                         reg = <0x10009000 0x1000>;
303                         clocks = <&uartclk>, <&pclk>;
304                         clock-names = "uartclk", "apb_pclk";
305                 };
306
307                 serial1: serial@1000a000 {
308                         compatible = "arm,pl011", "arm,primecell";
309                         reg = <0x1000a000 0x1000>;
310                         clocks = <&uartclk>, <&pclk>;
311                         clock-names = "uartclk", "apb_pclk";
312                 };
313
314                 serial2: serial@1000b000 {
315                         compatible = "arm,pl011", "arm,primecell";
316                         reg = <0x1000b000 0x1000>;
317                         clocks = <&uartclk>, <&pclk>;
318                         clock-names = "uartclk", "apb_pclk";
319                 };
320
321                 ssp: ssp@1000d000 {
322                         compatible = "arm,pl022", "arm,primecell";
323                         reg = <0x1000d000 0x1000>;
324                         clocks = <&sspclk>, <&pclk>;
325                         clock-names = "SSPCLK", "apb_pclk";
326                 };
327
328                 wdog0: watchdog@1000f000 {
329                         compatible = "arm,sp805", "arm,primecell";
330                         reg = <0x1000f000 0x1000>;
331                         clocks = <&wdogclk>, <&pclk>;
332                         clock-names = "wdogclk", "apb_pclk";
333                         status = "disabled";
334                 };
335
336                 wdog1: watchdog@10010000 {
337                         compatible = "arm,sp805", "arm,primecell";
338                         reg = <0x10010000 0x1000>;
339                         clocks = <&wdogclk>, <&pclk>;
340                         clock-names = "wdogclk", "apb_pclk";
341                         status = "disabled";
342                 };
343
344                 timer01: timer@10011000 {
345                         compatible = "arm,sp804", "arm,primecell";
346                         reg = <0x10011000 0x1000>;
347                         clocks = <&sp810_syscon0 0>,
348                                  <&sp810_syscon0 1>,
349                                  <&pclk>;
350                         clock-names = "timerclk0",
351                                     "timerclk1",
352                                     "apb_pclk";
353                 };
354
355                 timer23: timer@10012000 {
356                         compatible = "arm,sp804", "arm,primecell";
357                         reg = <0x10012000 0x1000>;
358                         clocks = <&sp810_syscon0 2>,
359                                  <&sp810_syscon0 3>,
360                                  <&pclk>;
361                         clock-names = "timerclk2",
362                                     "timerclk3",
363                                     "apb_pclk";
364                 };
365
366                 gpio0: gpio@10013000 {
367                         compatible = "arm,pl061", "arm,primecell";
368                         reg = <0x10013000 0x1000>;
369                         gpio-controller;
370                         #gpio-cells = <2>;
371                         interrupt-controller;
372                         #interrupt-cells = <2>;
373                         clocks = <&pclk>;
374                         clock-names = "apb_pclk";
375                 };
376
377                 gpio1: gpio@10014000 {
378                         compatible = "arm,pl061", "arm,primecell";
379                         reg = <0x10014000 0x1000>;
380                         gpio-controller;
381                         #gpio-cells = <2>;
382                         interrupt-controller;
383                         #interrupt-cells = <2>;
384                         clocks = <&pclk>;
385                         clock-names = "apb_pclk";
386                 };
387
388                 gpio2: gpio@10015000 {
389                         compatible = "arm,pl061", "arm,primecell";
390                         reg = <0x10015000 0x1000>;
391                         gpio-controller;
392                         #gpio-cells = <2>;
393                         interrupt-controller;
394                         #interrupt-cells = <2>;
395                         clocks = <&pclk>;
396                         clock-names = "apb_pclk";
397                 };
398
399                 /* DVI serial bus control is at 10016000 */
400
401                 rtc: rtc@10017000 {
402                         compatible = "arm,pl031", "arm,primecell";
403                         reg = <0x10017000 0x1000>;
404                         clocks = <&pclk>;
405                         clock-names = "apb_pclk";
406                 };
407
408                 timer45: timer@10018000 {
409                         compatible = "arm,sp804", "arm,primecell";
410                         reg = <0x10018000 0x1000>;
411                         clocks = <&timclk>, <&timclk>, <&pclk>;
412                         clock-names = "timerclk4", "timerclk5", "apb_pclk";
413                 };
414
415                 timer67: timer@10019000 {
416                         compatible = "arm,sp804", "arm,primecell";
417                         reg = <0x10019000 0x1000>;
418                         clocks = <&timclk>, <&timclk>, <&pclk>;
419                         clock-names = "timerclk6", "timerclk7", "apb_pclk";
420                 };
421
422                 sp810_syscon1: sysctl@1001a000 {
423                         compatible = "arm,sp810", "arm,primecell";
424                         reg = <0x1001a000 0x1000>;
425                         clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
426                         clock-names = "refclk", "timclk", "apb_pclk";
427                         #clock-cells = <1>;
428                         clock-output-names = "timerclk4",
429                                              "timerclk5",
430                                              "timerclk6",
431                                              "timerclk7";
432                         assigned-clocks = <&sp810_syscon1 0>,
433                                           <&sp810_syscon1 1>,
434                                           <&sp810_syscon1 2>,
435                                           <&sp810_syscon1 3>;
436                         assigned-clock-parents = <&timclk>,
437                                                <&timclk>,
438                                                <&timclk>,
439                                                <&timclk>;
440                 };
441         };
442
443
444         /* These peripherals are inside the FPGA */
445         fpga {
446                 #address-cells = <1>;
447                 #size-cells = <1>;
448                 compatible = "simple-bus";
449                 ranges;
450
451                 aaci: aaci@10004000 {
452                         compatible = "arm,pl041", "arm,primecell";
453                         reg = <0x10004000 0x1000>;
454                         clocks = <&pclk>;
455                         clock-names = "apb_pclk";
456                 };
457
458                 mmc: mmcsd@10005000 {
459                         compatible = "arm,pl18x", "arm,primecell";
460                         reg = <0x10005000 0x1000>;
461
462                         /* Due to frequent FIFO overruns, use just 500 kHz */
463                         max-frequency = <500000>;
464                         bus-width = <4>;
465                         cap-sd-highspeed;
466                         cap-mmc-highspeed;
467                         clocks = <&mclk>, <&pclk>;
468                         clock-names = "mclk", "apb_pclk";
469                         vmmc-supply = <&vmmc>;
470                         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
471                         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
472                 };
473
474                 kmi0: kmi@10006000 {
475                         compatible = "arm,pl050", "arm,primecell";
476                         reg = <0x10006000 0x1000>;
477                         clocks = <&kmiclk>, <&pclk>;
478                         clock-names = "KMIREFCLK", "apb_pclk";
479                 };
480
481                 kmi1: kmi@10007000 {
482                         compatible = "arm,pl050", "arm,primecell";
483                         reg = <0x10007000 0x1000>;
484                         clocks = <&kmiclk>, <&pclk>;
485                         clock-names = "KMIREFCLK", "apb_pclk";
486                 };
487
488                 serial3: serial@1000c000 {
489                         compatible = "arm,pl011", "arm,primecell";
490                         reg = <0x1000c000 0x1000>;
491                         clocks = <&uartclk>, <&pclk>;
492                         clock-names = "uartclk", "apb_pclk";
493                 };
494         };
495
496         /* These peripherals are inside the NEC ISSP */
497         issp {
498                 #address-cells = <1>;
499                 #size-cells = <1>;
500                 compatible = "simple-bus";
501                 ranges;
502
503                 clcd: clcd@10020000 {
504                         compatible = "arm,pl111", "arm,primecell";
505                         reg = <0x10020000 0x1000>;
506                         interrupt-names = "combined";
507                         clocks = <&oscclk4>, <&pclk>;
508                         clock-names = "clcdclk", "apb_pclk";
509
510                         port {
511                                 clcd_pads: endpoint {
512                                         remote-endpoint = <&clcd_panel>;
513                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
514                                 };
515                         };
516
517                         panel {
518                                 compatible = "panel-dpi";
519
520                                 port {
521                                         clcd_panel: endpoint {
522                                                 remote-endpoint = <&clcd_pads>;
523                                         };
524                                 };
525
526                                 /* Standard 640x480 VGA timings */
527                                 panel-timing {
528                                         clock-frequency = <25175000>;
529                                         hactive = <640>;
530                                         hback-porch = <48>;
531                                         hfront-porch = <16>;
532                                         hsync-len = <96>;
533                                         vactive = <480>;
534                                         vback-porch = <33>;
535                                         vfront-porch = <10>;
536                                         vsync-len = <2>;
537                                 };
538                         };
539                 };
540         };
541 };
542