arch/arm/boot/dts/arm-realview-pbx.dtsi

   1 /*
   2  * Copyright 2016 Linaro Ltd
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a copy
   5  * of this software and associated documentation files (the "Software"), to deal
   6  * in the Software without restriction, including without limitation the rights
   7  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   8  * copies of the Software, and to permit persons to whom the Software is
   9  * furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  19  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  20  * THE SOFTWARE.
  21  */
  22
  23 #include <dt-bindings/interrupt-controller/irq.h>
  24 #include <dt-bindings/gpio/gpio.h>
  25
  26 / {
  27         #address-cells = <1>;
  28         #size-cells = <1>;
  29         compatible = "arm,realview-pbx";
  30
  31         chosen { };
  32
  33         aliases {
  34                 serial0 = &serial0;
  35                 serial1 = &serial1;
  36                 serial2 = &serial2;
  37                 serial3 = &serial3;
  38                 i2c0 = &i2c0;
  39                 i2c1 = &i2c1;
  40         };
  41
  42         memory {
  43                 device_type = "memory";
  44                 /* 128 MiB memory @ 0x0 */
  45                 reg = <0x00000000 0x08000000>;
  46         };
  47
  48         /* The voltage to the MMC card is hardwired at 3.3V */
  49         vmmc: regulator-vmmc {
  50                 compatible = "regulator-fixed";
  51                 regulator-name = "vmmc";
  52                 regulator-min-microvolt = <3300000>;
  53                 regulator-max-microvolt = <3300000>;
  54                 regulator-boot-on;
  55         };
  56
  57         veth: regulator-veth {
  58                 compatible = "regulator-fixed";
  59                 regulator-name = "veth";
  60                 regulator-min-microvolt = <3300000>;
  61                 regulator-max-microvolt = <3300000>;
  62                 regulator-boot-on;
  63         };
  64
  65         xtal24mhz: xtal24mhz@24M {
  66                 #clock-cells = <0>;
  67                 compatible = "fixed-clock";
  68                 clock-frequency = <24000000>;
  69         };
  70
  71         refclk32khz: refclk32khz {
  72                 #clock-cells = <0>;
  73                 compatible = "fixed-clock";
  74                 clock-frequency = <32768>;
  75         };
  76
  77         timclk: timclk@1M {
  78                 #clock-cells = <0>;
  79                 compatible = "fixed-factor-clock";
  80                 clock-div = <24>;
  81                 clock-mult = <1>;
  82                 clocks = <&xtal24mhz>;
  83         };
  84
  85         mclk: mclk@24M {
  86                 #clock-cells = <0>;
  87                 compatible = "fixed-factor-clock";
  88                 clock-div = <1>;
  89                 clock-mult = <1>;
  90                 clocks = <&xtal24mhz>;
  91         };
  92
  93         kmiclk: kmiclk@24M {
  94                 #clock-cells = <0>;
  95                 compatible = "fixed-factor-clock";
  96                 clock-div = <1>;
  97                 clock-mult = <1>;
  98                 clocks = <&xtal24mhz>;
  99         };
 100
 101         sspclk: sspclk@24M {
 102                 #clock-cells = <0>;
 103                 compatible = "fixed-factor-clock";
 104                 clock-div = <1>;
 105                 clock-mult = <1>;
 106                 clocks = <&xtal24mhz>;
 107         };
 108
 109         uartclk: uartclk@24M {
 110                 #clock-cells = <0>;
 111                 compatible = "fixed-factor-clock";
 112                 clock-div = <1>;
 113                 clock-mult = <1>;
 114                 clocks = <&xtal24mhz>;
 115         };
 116
 117         wdogclk: wdogclk@24M {
 118                 #clock-cells = <0>;
 119                 compatible = "fixed-factor-clock";
 120                 clock-div = <1>;
 121                 clock-mult = <1>;
 122                 clocks = <&xtal24mhz>;
 123         };
 124
 125         /* FIXME: this actually hangs off the PLL clocks */
 126         pclk: pclk@0 {
 127                 #clock-cells = <0>;
 128                 compatible = "fixed-clock";
 129                 clock-frequency = <0>;
 130         };
 131
 132         flash0@40000000 {
 133                 /* 2 * 32MiB NOR Flash memory */
 134                 compatible = "arm,versatile-flash", "cfi-flash";
 135                 reg = <0x40000000 0x04000000>;
 136                 bank-width = <4>;
 137         };
 138
 139         flash1@44000000 {
 140                 /* 2 * 32MiB NOR Flash memory */
 141                 compatible = "arm,versatile-flash", "cfi-flash";
 142                 reg = <0x44000000 0x04000000>;
 143                 bank-width = <4>;
 144         };
 145
 146         /* SMSC 9118 ethernet with PHY and EEPROM */
 147         ethernet: ethernet@4e000000 {
 148                 compatible = "smsc,lan9118", "smsc,lan9115";
 149                 reg = <0x4e000000 0x10000>;
 150                 phy-mode = "mii";
 151                 reg-io-width = <4>;
 152                 smsc,irq-active-high;
 153                 smsc,irq-push-pull;
 154                 vdd33a-supply = <&veth>;
 155                 vddvario-supply = <&veth>;
 156         };
 157
 158         usb: usb@4f000000 {
 159                 compatible = "nxp,usb-isp1761";
 160                 reg = <0x4f000000 0x20000>;
 161                 port1-otg;
 162         };
 163
 164         bridge {
 165                 compatible = "ti,ths8134a", "ti,ths8134";
 166                 #address-cells = <1>;
 167                 #size-cells = <0>;
 168
 169                 ports {
 170                         #address-cells = <1>;
 171                         #size-cells = <0>;
 172
 173                         port@0 {
 174                                 reg = <0>;
 175
 176                                 vga_bridge_in: endpoint {
 177                                         remote-endpoint = <&clcd_pads>;
 178                                 };
 179                         };
 180
 181                         port@1 {
 182                                 reg = <1>;
 183
 184                                 vga_bridge_out: endpoint {
 185                                         remote-endpoint = <&vga_con_in>;
 186                                 };
 187                         };
 188                 };
 189         };
 190
 191         vga {
 192                 /*
 193                  * This DDC I2C is connected directly to the DVI portions
 194                  * of the connector, so it's not really working when the
 195                  * monitor is connected to the VGA connector.
 196                  */
 197                 compatible = "vga-connector";
 198                 ddc-i2c-bus = <&i2c1>;
 199
 200                 port {
 201                         vga_con_in: endpoint {
 202                                 remote-endpoint = <&vga_bridge_out>;
 203                         };
 204                 };
 205         };
 206
 207         soc: soc@0 {
 208                 compatible = "arm,realview-pbx-soc", "simple-bus";
 209                 #address-cells = <1>;
 210                 #size-cells = <1>;
 211                 regmap = <&syscon>;
 212                 ranges;
 213
 214                 syscon: syscon@10000000 {
 215                         compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd";
 216                         reg = <0x10000000 0x1000>;
 217
 218                         led@08.0 {
 219                                 compatible = "register-bit-led";
 220                                 offset = <0x08>;
 221                                 mask = <0x01>;
 222                                 label = "versatile:0";
 223                                 linux,default-trigger = "heartbeat";
 224                                 default-state = "on";
 225                         };
 226                         led@08.1 {
 227                                 compatible = "register-bit-led";
 228                                 offset = <0x08>;
 229                                 mask = <0x02>;
 230                                 label = "versatile:1";
 231                                 linux,default-trigger = "mmc0";
 232                                 default-state = "off";
 233                         };
 234                         led@08.2 {
 235                                 compatible = "register-bit-led";
 236                                 offset = <0x08>;
 237                                 mask = <0x04>;
 238                                 label = "versatile:2";
 239                                 linux,default-trigger = "cpu0";
 240                                 default-state = "off";
 241                         };
 242                         led@08.3 {
 243                                 compatible = "register-bit-led";
 244                                 offset = <0x08>;
 245                                 mask = <0x08>;
 246                                 label = "versatile:3";
 247                                 default-state = "off";
 248                         };
 249                         led@08.4 {
 250                                 compatible = "register-bit-led";
 251                                 offset = <0x08>;
 252                                 mask = <0x10>;
 253                                 label = "versatile:4";
 254                                 default-state = "off";
 255                         };
 256                         led@08.5 {
 257                                 compatible = "register-bit-led";
 258                                 offset = <0x08>;
 259                                 mask = <0x20>;
 260                                 label = "versatile:5";
 261                                 default-state = "off";
 262                         };
 263                         led@08.6 {
 264                                 compatible = "register-bit-led";
 265                                 offset = <0x08>;
 266                                 mask = <0x40>;
 267                                 label = "versatile:6";
 268                                 default-state = "off";
 269                         };
 270                         led@08.7 {
 271                                 compatible = "register-bit-led";
 272                                 offset = <0x08>;
 273                                 mask = <0x80>;
 274                                 label = "versatile:7";
 275                                 default-state = "off";
 276                         };
 277                         oscclk0: osc0@0c {
 278                                 compatible = "arm,syscon-icst307";
 279                                 #clock-cells = <0>;
 280                                 lock-offset = <0x20>;
 281                                 vco-offset = <0x0C>;
 282                                 clocks = <&xtal24mhz>;
 283                         };
 284                         oscclk1: osc1@10 {
 285                                 compatible = "arm,syscon-icst307";
 286                                 #clock-cells = <0>;
 287                                 lock-offset = <0x20>;
 288                                 vco-offset = <0x10>;
 289                                 clocks = <&xtal24mhz>;
 290                         };
 291                         oscclk2: osc2@14 {
 292                                 compatible = "arm,syscon-icst307";
 293                                 #clock-cells = <0>;
 294                                 lock-offset = <0x20>;
 295                                 vco-offset = <0x14>;
 296                                 clocks = <&xtal24mhz>;
 297                         };
 298                         oscclk3: osc3@18 {
 299                                 compatible = "arm,syscon-icst307";
 300                                 #clock-cells = <0>;
 301                                 lock-offset = <0x20>;
 302                                 vco-offset = <0x18>;
 303                                 clocks = <&xtal24mhz>;
 304                         };
 305                         oscclk4: osc4@1c {
 306                                 compatible = "arm,syscon-icst307";
 307                                 #clock-cells = <0>;
 308                                 lock-offset = <0x20>;
 309                                 vco-offset = <0x1c>;
 310                                 clocks = <&xtal24mhz>;
 311                         };
 312                 };
 313
 314                 sp810_syscon0: sysctl@10001000 {
 315                         compatible = "arm,sp810", "arm,primecell";
 316                         reg = <0x10001000 0x1000>;
 317                         clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
 318                         clock-names = "refclk", "timclk", "apb_pclk";
 319                         #clock-cells = <1>;
 320                         clock-output-names = "timerclk0",
 321                                              "timerclk1",
 322                                              "timerclk2",
 323                                              "timerclk3";
 324                         assigned-clocks = <&sp810_syscon0 0>,
 325                                           <&sp810_syscon0 1>,
 326                                           <&sp810_syscon0 2>,
 327                                           <&sp810_syscon0 3>;
 328                         assigned-clock-parents = <&timclk>,
 329                                                <&timclk>,
 330                                                <&timclk>,
 331                                                <&timclk>;
 332                 };
 333
 334                 i2c0: i2c@10002000 {
 335                         #address-cells = <1>;
 336                         #size-cells = <0>;
 337                         compatible = "arm,versatile-i2c";
 338                         reg = <0x10002000 0x1000>;
 339
 340                         rtc@68 {
 341                                 compatible = "dallas,ds1338";
 342                                 reg = <0x68>;
 343                         };
 344                 };
 345
 346                 serial0: serial@10009000 {
 347                         compatible = "arm,pl011", "arm,primecell";
 348                         reg = <0x10009000 0x1000>;
 349                         clocks = <&uartclk>, <&pclk>;
 350                         clock-names = "uartclk", "apb_pclk";
 351                 };
 352
 353                 serial1: serial@1000a000 {
 354                         compatible = "arm,pl011", "arm,primecell";
 355                         reg = <0x1000a000 0x1000>;
 356                         clocks = <&uartclk>, <&pclk>;
 357                         clock-names = "uartclk", "apb_pclk";
 358                 };
 359
 360                 serial2: serial@1000b000 {
 361                         compatible = "arm,pl011", "arm,primecell";
 362                         reg = <0x1000b000 0x1000>;
 363                         clocks = <&uartclk>, <&pclk>;
 364                         clock-names = "uartclk", "apb_pclk";
 365                 };
 366
 367                 ssp: spi@1000d000 {
 368                         compatible = "arm,pl022", "arm,primecell";
 369                         reg = <0x1000d000 0x1000>;
 370                         clocks = <&sspclk>, <&pclk>;
 371                         clock-names = "SSPCLK", "apb_pclk";
 372                 };
 373
 374                 wdog0: watchdog@1000f000 {
 375                         compatible = "arm,sp805", "arm,primecell";
 376                         reg = <0x1000f000 0x1000>;
 377                         clocks = <&wdogclk>, <&pclk>;
 378                         clock-names = "wdogclk", "apb_pclk";
 379                         status = "disabled";
 380                 };
 381
 382                 wdog1: watchdog@10010000 {
 383                         compatible = "arm,sp805", "arm,primecell";
 384                         reg = <0x10010000 0x1000>;
 385                         clocks = <&wdogclk>, <&pclk>;
 386                         clock-names = "wdogclk", "apb_pclk";
 387                         status = "disabled";
 388                 };
 389
 390                 timer01: timer@10011000 {
 391                         compatible = "arm,sp804", "arm,primecell";
 392                         reg = <0x10011000 0x1000>;
 393                         clocks = <&sp810_syscon0 0>,
 394                                  <&sp810_syscon0 1>,
 395                                  <&pclk>;
 396                         clock-names = "timerclk0",
 397                                     "timerclk1",
 398                                     "apb_pclk";
 399                 };
 400
 401                 timer23: timer@10012000 {
 402                         compatible = "arm,sp804", "arm,primecell";
 403                         reg = <0x10012000 0x1000>;
 404                         clocks = <&sp810_syscon0 2>,
 405                                  <&sp810_syscon0 3>,
 406                                  <&pclk>;
 407                         clock-names = "timerclk2",
 408                                     "timerclk3",
 409                                     "apb_pclk";
 410                 };
 411
 412                 gpio0: gpio@10013000 {
 413                         compatible = "arm,pl061", "arm,primecell";
 414                         reg = <0x10013000 0x1000>;
 415                         gpio-controller;
 416                         #gpio-cells = <2>;
 417                         interrupt-controller;
 418                         #interrupt-cells = <2>;
 419                         clocks = <&pclk>;
 420                         clock-names = "apb_pclk";
 421                 };
 422
 423                 gpio1: gpio@10014000 {
 424                         compatible = "arm,pl061", "arm,primecell";
 425                         reg = <0x10014000 0x1000>;
 426                         gpio-controller;
 427                         #gpio-cells = <2>;
 428                         interrupt-controller;
 429                         #interrupt-cells = <2>;
 430                         clocks = <&pclk>;
 431                         clock-names = "apb_pclk";
 432                 };
 433
 434                 gpio2: gpio@10015000 {
 435                         compatible = "arm,pl061", "arm,primecell";
 436                         reg = <0x10015000 0x1000>;
 437                         gpio-controller;
 438                         #gpio-cells = <2>;
 439                         interrupt-controller;
 440                         #interrupt-cells = <2>;
 441                         clocks = <&pclk>;
 442                         clock-names = "apb_pclk";
 443                 };
 444
 445                 i2c1: i2c@10016000 {
 446                         #address-cells = <1>;
 447                         #size-cells = <0>;
 448                         compatible = "arm,versatile-i2c";
 449                         reg = <0x10016000 0x1000>;
 450                 };
 451
 452                 rtc: rtc@10017000 {
 453                         compatible = "arm,pl031", "arm,primecell";
 454                         reg = <0x10017000 0x1000>;
 455                         clocks = <&pclk>;
 456                         clock-names = "apb_pclk";
 457                 };
 458
 459                 timer45: timer@10018000 {
 460                         compatible = "arm,sp804", "arm,primecell";
 461                         reg = <0x10018000 0x1000>;
 462                         clocks = <&timclk>, <&timclk>, <&pclk>;
 463                         clock-names = "timerclk4", "timerclk5", "apb_pclk";
 464                 };
 465
 466                 timer67: timer@10019000 {
 467                         compatible = "arm,sp804", "arm,primecell";
 468                         reg = <0x10019000 0x1000>;
 469                         clocks = <&timclk>, <&timclk>, <&pclk>;
 470                         clock-names = "timerclk6", "timerclk7", "apb_pclk";
 471                 };
 472
 473                 sp810_syscon1: sysctl@1001a000 {
 474                         compatible = "arm,sp810", "arm,primecell";
 475                         reg = <0x1001a000 0x1000>;
 476                         clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
 477                         clock-names = "refclk", "timclk", "apb_pclk";
 478                         #clock-cells = <1>;
 479                         clock-output-names = "timerclk4",
 480                                              "timerclk5",
 481                                              "timerclk6",
 482                                              "timerclk7";
 483                         assigned-clocks = <&sp810_syscon1 0>,
 484                                           <&sp810_syscon1 1>,
 485                                           <&sp810_syscon1 2>,
 486                                           <&sp810_syscon1 3>;
 487                         assigned-clock-parents = <&timclk>,
 488                                                <&timclk>,
 489                                                <&timclk>,
 490                                                <&timclk>;
 491                 };
 492         };
 493
 494
 495         /* These peripherals are inside the FPGA */
 496         fpga {
 497                 #address-cells = <1>;
 498                 #size-cells = <1>;
 499                 compatible = "simple-bus";
 500                 ranges;
 501
 502                 aaci: aaci@10004000 {
 503                         compatible = "arm,pl041", "arm,primecell";
 504                         reg = <0x10004000 0x1000>;
 505                         clocks = <&pclk>;
 506                         clock-names = "apb_pclk";
 507                 };
 508
 509                 mmc: mmcsd@10005000 {
 510                         compatible = "arm,pl18x", "arm,primecell";
 511                         reg = <0x10005000 0x1000>;
 512
 513                         /* Due to frequent FIFO overruns, use just 500 kHz */
 514                         max-frequency = <500000>;
 515                         bus-width = <4>;
 516                         cap-sd-highspeed;
 517                         cap-mmc-highspeed;
 518                         clocks = <&mclk>, <&pclk>;
 519                         clock-names = "mclk", "apb_pclk";
 520                         vmmc-supply = <&vmmc>;
 521                         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 522                         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 523                 };
 524
 525                 kmi0: kmi@10006000 {
 526                         compatible = "arm,pl050", "arm,primecell";
 527                         reg = <0x10006000 0x1000>;
 528                         clocks = <&kmiclk>, <&pclk>;
 529                         clock-names = "KMIREFCLK", "apb_pclk";
 530                 };
 531
 532                 kmi1: kmi@10007000 {
 533                         compatible = "arm,pl050", "arm,primecell";
 534                         reg = <0x10007000 0x1000>;
 535                         clocks = <&kmiclk>, <&pclk>;
 536                         clock-names = "KMIREFCLK", "apb_pclk";
 537                 };
 538
 539                 serial3: serial@1000c000 {
 540                         compatible = "arm,pl011", "arm,primecell";
 541                         reg = <0x1000c000 0x1000>;
 542                         clocks = <&uartclk>, <&pclk>;
 543                         clock-names = "uartclk", "apb_pclk";
 544                 };
 545         };
 546
 547         /* These peripherals are inside the NEC ISSP */
 548         issp {
 549                 #address-cells = <1>;
 550                 #size-cells = <1>;
 551                 compatible = "simple-bus";
 552                 ranges;
 553
 554                 clcd: clcd@10020000 {
 555                         compatible = "arm,pl111", "arm,primecell";
 556                         reg = <0x10020000 0x1000>;
 557                         interrupt-names = "combined";
 558                         clocks = <&oscclk4>, <&pclk>;
 559                         clock-names = "clcdclk", "apb_pclk";
 560                         /* 1024x768 16bpp @65MHz works fine */
 561                         max-memory-bandwidth = <95000000>;
 562
 563                         port {
 564                                 clcd_pads: endpoint {
 565                                         remote-endpoint = <&vga_bridge_in>;
 566                                         arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
 567                                 };
 568                         };
 569                 };
 570         };
 571 };