2 * Copyright 2015 Linaro Ltd
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5 * of this software and associated documentation files (the "Software"), to deal
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9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
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14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
30 model = "ARM RealView PB11MPcore";
31 compatible = "arm,realview-pb11mp";
36 serial0 = &pb11mp_serial0;
37 serial1 = &pb11mp_serial1;
38 serial2 = &pb11mp_serial2;
39 serial3 = &pb11mp_serial3;
43 device_type = "memory";
45 * The PB11MPCore has 512 MiB memory @ 0x70000000
46 * and the first 256 are also remapped @ 0x00000000
48 reg = <0x70000000 0x20000000>;
54 enable-method = "arm,realview-smp";
58 compatible = "arm,arm11mpcore";
60 next-level-cache = <&L2>;
65 compatible = "arm,arm11mpcore";
67 next-level-cache = <&L2>;
72 compatible = "arm,arm11mpcore";
74 next-level-cache = <&L2>;
79 compatible = "arm,arm11mpcore";
81 next-level-cache = <&L2>;
85 /* Primary TestChip GIC synthesized with the CPU */
86 intc_tc11mp: interrupt-controller@1f000100 {
87 compatible = "arm,tc11mp-gic";
88 #interrupt-cells = <3>;
91 reg = <0x1f001000 0x1000>,
96 compatible = "arm,l220-cache";
97 reg = <0x1f002000 0x1000>;
98 interrupt-parent = <&intc_tc11mp>;
99 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>,
100 <0 30 IRQ_TYPE_LEVEL_HIGH>,
101 <0 31 IRQ_TYPE_LEVEL_HIGH>;
105 * Override default cache size, sets and
106 * associativity as these may be erroneously set
107 * up by boot loader(s), probably for safety
108 * since th outer sync operation can cause the
109 * cache to hang unless disabled.
111 cache-size = <1048576>; // 1MB
113 cache-line-size = <32>;
116 arm,outer-sync-disable;
120 compatible = "arm,arm11mp-scu";
121 reg = <0x1f000000 0x100>;
125 compatible = "arm,arm11mp-twd-timer";
126 reg = <0x1f000600 0x20>;
127 interrupt-parent = <&intc_tc11mp>;
128 interrupts = <1 13 0xf04>;
132 compatible = "arm,arm11mp-twd-wdt";
133 reg = <0x1f000620 0x20>;
134 interrupt-parent = <&intc_tc11mp>;
135 interrupts = <1 14 0xf04>;
138 /* PMU with one IRQ line per core */
140 compatible = "arm,arm11mpcore-pmu";
141 interrupt-parent = <&intc_tc11mp>;
142 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>,
143 <0 18 IRQ_TYPE_LEVEL_HIGH>,
144 <0 19 IRQ_TYPE_LEVEL_HIGH>,
145 <0 20 IRQ_TYPE_LEVEL_HIGH>;
146 interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>;
149 /* The voltage to the MMC card is hardwired at 3.3V */
150 vmmc: regulator-vmmc {
151 compatible = "regulator-fixed";
152 regulator-name = "vmmc";
153 regulator-min-microvolt = <3300000>;
154 regulator-max-microvolt = <3300000>;
158 veth: regulator-veth {
159 compatible = "regulator-fixed";
160 regulator-name = "veth";
161 regulator-min-microvolt = <3300000>;
162 regulator-max-microvolt = <3300000>;
166 xtal24mhz: xtal24mhz@24M {
168 compatible = "fixed-clock";
169 clock-frequency = <24000000>;
172 refclk32khz: refclk32khz {
173 compatible = "fixed-clock";
175 clock-frequency = <32768>;
180 compatible = "fixed-factor-clock";
183 clocks = <&xtal24mhz>;
188 compatible = "fixed-factor-clock";
191 clocks = <&xtal24mhz>;
196 compatible = "fixed-factor-clock";
199 clocks = <&xtal24mhz>;
204 compatible = "fixed-factor-clock";
207 clocks = <&xtal24mhz>;
210 uartclk: uartclk@24M {
212 compatible = "fixed-factor-clock";
215 clocks = <&xtal24mhz>;
218 wdogclk: wdogclk@24M {
220 compatible = "fixed-factor-clock";
223 clocks = <&xtal24mhz>;
226 /* FIXME: this actually hangs off the PLL clocks */
229 compatible = "fixed-clock";
230 clock-frequency = <0>;
234 /* 2 * 32MiB NOR Flash memory */
235 compatible = "arm,versatile-flash", "cfi-flash";
236 reg = <0x40000000 0x04000000>;
241 // 2 * 32MiB NOR Flash memory
242 compatible = "arm,versatile-flash", "cfi-flash";
243 reg = <0x44000000 0x04000000>;
248 compatible = "ti,ths8134a", "ti,ths8134";
249 #address-cells = <1>;
253 #address-cells = <1>;
259 vga_bridge_in: endpoint {
260 remote-endpoint = <&clcd_pads>;
267 vga_bridge_out: endpoint {
268 remote-endpoint = <&vga_con_in>;
276 * This DDC I2C is connected directly to the DVI portions
277 * of the connector, so it's not really working when the
278 * monitor is connected to the VGA connector.
280 compatible = "vga-connector";
281 ddc-i2c-bus = <&i2c1>;
284 vga_con_in: endpoint {
285 remote-endpoint = <&vga_bridge_out>;
291 #address-cells = <1>;
293 compatible = "arm,realview-pb11mp-soc", "simple-bus";
294 regmap = <&pb11mp_syscon>;
297 pb11mp_syscon: syscon@10000000 {
298 compatible = "arm,realview-pb11mp-syscon", "syscon", "simple-mfd";
299 reg = <0x10000000 0x1000>;
302 compatible = "register-bit-led";
305 label = "versatile:0";
306 linux,default-trigger = "heartbeat";
307 default-state = "on";
310 compatible = "register-bit-led";
313 label = "versatile:1";
314 linux,default-trigger = "mmc0";
315 default-state = "off";
318 compatible = "register-bit-led";
321 label = "versatile:2";
322 linux,default-trigger = "cpu0";
323 default-state = "off";
326 compatible = "register-bit-led";
329 label = "versatile:3";
330 linux,default-trigger = "cpu1";
331 default-state = "off";
334 compatible = "register-bit-led";
337 label = "versatile:4";
338 linux,default-trigger = "cpu2";
339 default-state = "off";
342 compatible = "register-bit-led";
345 label = "versatile:5";
346 linux,default-trigger = "cpu3";
347 default-state = "off";
350 compatible = "register-bit-led";
353 label = "versatile:6";
354 default-state = "off";
357 compatible = "register-bit-led";
360 label = "versatile:7";
361 default-state = "off";
365 compatible = "arm,syscon-icst307";
367 lock-offset = <0x20>;
369 clocks = <&xtal24mhz>;
372 compatible = "arm,syscon-icst307";
374 lock-offset = <0x20>;
376 clocks = <&xtal24mhz>;
379 compatible = "arm,syscon-icst307";
381 lock-offset = <0x20>;
383 clocks = <&xtal24mhz>;
386 compatible = "arm,syscon-icst307";
388 lock-offset = <0x20>;
390 clocks = <&xtal24mhz>;
393 compatible = "arm,syscon-icst307";
395 lock-offset = <0x20>;
397 clocks = <&xtal24mhz>;
400 compatible = "arm,syscon-icst307";
402 lock-offset = <0x20>;
404 clocks = <&xtal24mhz>;
407 compatible = "arm,syscon-icst307";
409 lock-offset = <0x20>;
411 clocks = <&xtal24mhz>;
415 sp810_syscon: sysctl@10001000 {
416 compatible = "arm,sp810", "arm,primecell";
417 reg = <0x10001000 0x1000>;
418 clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>;
419 clock-names = "refclk", "timclk", "apb_pclk";
421 clock-output-names = "timerclk0",
425 assigned-clocks = <&sp810_syscon 0>,
429 assigned-clock-parents = <&timclk>,
436 #address-cells = <1>;
438 compatible = "arm,versatile-i2c";
439 reg = <0x10002000 0x1000>;
442 compatible = "dallas,ds1338";
447 aaci: aaci@10004000 {
448 compatible = "arm,pl041", "arm,primecell";
449 reg = <0x10004000 0x1000>;
450 interrupt-parent = <&intc_tc11mp>;
451 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
453 clock-names = "apb_pclk";
456 mci: mmcsd@10005000 {
457 compatible = "arm,pl18x", "arm,primecell";
458 reg = <0x10005000 0x1000>;
459 interrupt-parent = <&intc_tc11mp>;
460 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>,
461 <0 15 IRQ_TYPE_LEVEL_HIGH>;
462 /* Due to frequent FIFO overruns, use just 500 kHz */
463 max-frequency = <500000>;
467 clocks = <&mclk>, <&pclk>;
468 clock-names = "mclk", "apb_pclk";
469 vmmc-supply = <&vmmc>;
470 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
471 wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
475 compatible = "arm,pl050", "arm,primecell";
476 reg = <0x10006000 0x1000>;
477 interrupt-parent = <&intc_tc11mp>;
478 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
479 clocks = <&kmiclk>, <&pclk>;
480 clock-names = "KMIREFCLK", "apb_pclk";
484 compatible = "arm,pl050", "arm,primecell";
485 reg = <0x10007000 0x1000>;
486 interrupt-parent = <&intc_tc11mp>;
487 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&kmiclk>, <&pclk>;
489 clock-names = "KMIREFCLK", "apb_pclk";
492 pb11mp_serial0: serial@10009000 {
493 compatible = "arm,pl011", "arm,primecell";
494 reg = <0x10009000 0x1000>;
495 interrupt-parent = <&intc_tc11mp>;
496 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&uartclk>, <&pclk>;
498 clock-names = "uartclk", "apb_pclk";
501 pb11mp_serial1: serial@1000a000 {
502 compatible = "arm,pl011", "arm,primecell";
503 reg = <0x1000a000 0x1000>;
504 interrupt-parent = <&intc_tc11mp>;
505 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&uartclk>, <&pclk>;
507 clock-names = "uartclk", "apb_pclk";
510 pb11mp_serial2: serial@1000b000 {
511 compatible = "arm,pl011", "arm,primecell";
512 reg = <0x1000b000 0x1000>;
513 interrupt-parent = <&intc_pb11mp>;
514 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&uartclk>, <&pclk>;
516 clock-names = "uartclk", "apb_pclk";
519 pb11mp_serial3: serial@1000c000 {
520 compatible = "arm,pl011", "arm,primecell";
521 reg = <0x1000c000 0x1000>;
522 interrupt-parent = <&intc_pb11mp>;
523 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&uartclk>, <&pclk>;
525 clock-names = "uartclk", "apb_pclk";
529 compatible = "arm,pl022", "arm,primecell";
530 reg = <0x1000d000 0x1000>;
531 interrupt-parent = <&intc_pb11mp>;
532 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&sspclk>, <&pclk>;
534 clock-names = "SSPCLK", "apb_pclk";
538 compatible = "arm,sp805", "arm,primecell";
539 reg = <0x1000f000 0x1000>;
540 interrupt-parent = <&intc_pb11mp>;
541 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&wdogclk>, <&pclk>;
543 clock-names = "wdogclk", "apb_pclk";
548 compatible = "arm,sp805", "arm,primecell";
549 reg = <0x10010000 0x1000>;
550 interrupt-parent = <&intc_pb11mp>;
551 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&wdogclk>, <&pclk>;
553 clock-names = "wdogclk", "apb_pclk";
556 timer01: timer@10011000 {
557 compatible = "arm,sp804", "arm,primecell";
558 reg = <0x10011000 0x1000>;
559 interrupt-parent = <&intc_tc11mp>;
560 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>;
561 arm,sp804-has-irq = <1>;
562 clocks = <&sp810_syscon 0>,
565 clock-names = "timerclk0",
570 timer23: timer@10012000 {
571 compatible = "arm,sp804", "arm,primecell";
572 reg = <0x10012000 0x1000>;
573 interrupt-parent = <&intc_tc11mp>;
574 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
575 arm,sp804-has-irq = <1>;
576 clocks = <&sp810_syscon 2>,
579 clock-names = "timerclk2",
584 gpio0: gpio@10013000 {
585 compatible = "arm,pl061", "arm,primecell";
586 reg = <0x10013000 0x1000>;
588 interrupt-parent = <&intc_pb11mp>;
589 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
591 interrupt-controller;
592 #interrupt-cells = <2>;
594 clock-names = "apb_pclk";
597 gpio1: gpio@10014000 {
598 compatible = "arm,pl061", "arm,primecell";
599 reg = <0x10014000 0x1000>;
601 interrupt-parent = <&intc_pb11mp>;
602 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
604 interrupt-controller;
605 #interrupt-cells = <2>;
607 clock-names = "apb_pclk";
610 gpio2: gpio@10015000 {
611 compatible = "arm,pl061", "arm,primecell";
612 reg = <0x10015000 0x1000>;
614 interrupt-parent = <&intc_pb11mp>;
615 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-controller;
618 #interrupt-cells = <2>;
620 clock-names = "apb_pclk";
624 #address-cells = <1>;
626 compatible = "arm,versatile-i2c";
627 reg = <0x10016000 0x1000>;
631 compatible = "arm,pl031", "arm,primecell";
632 reg = <0x10017000 0x1000>;
633 interrupt-parent = <&intc_tc11mp>;
634 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
636 clock-names = "apb_pclk";
639 timer45: timer@10018000 {
640 compatible = "arm,sp804", "arm,primecell";
641 reg = <0x10018000 0x1000>;
642 clocks = <&timclk>, <&pclk>;
643 clock-names = "timer", "apb_pclk";
647 timer67: timer@10019000 {
648 compatible = "arm,sp804", "arm,primecell";
649 reg = <0x10019000 0x1000>;
650 clocks = <&timclk>, <&pclk>;
651 clock-names = "timer", "apb_pclk";
657 compatible = "arm,pl111", "arm,primecell";
658 reg = <0x10020000 0x1000>;
659 interrupt-parent = <&intc_pb11mp>;
660 interrupt-names = "combined";
661 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&oscclk4>, <&pclk>;
663 clock-names = "clcdclk", "apb_pclk";
664 /* 1024x768 16bpp @65MHz works fine */
665 max-memory-bandwidth = <95000000>;
668 clcd_pads: endpoint {
669 remote-endpoint = <&vga_bridge_in>;
670 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
676 * This GIC on the Platform Baseboard is cascaded off the
679 intc_pb11mp: interrupt-controller@1e000000 {
680 compatible = "arm,arm11mp-gic";
681 #interrupt-cells = <3>;
682 #address-cells = <1>;
683 interrupt-controller;
684 reg = <0x1e001000 0x1000>,
686 interrupt-parent = <&intc_tc11mp>;
687 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
690 /* SMSC 9118 ethernet with PHY and EEPROM */
692 compatible = "smsc,lan9118", "smsc,lan9115";
693 reg = <0x4e000000 0x10000>;
694 interrupt-parent = <&intc_tc11mp>;
695 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
698 smsc,irq-active-high;
700 vdd33a-supply = <&veth>;
701 vddvario-supply = <&veth>;
705 compatible = "nxp,usb-isp1761";
706 reg = <0x4f000000 0x20000>;
707 interrupt-parent = <&intc_tc11mp>;
708 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;