arch/arm/boot/dts/am43x-epos-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /* AM43x EPOS EVM */
  10
  11 /dts-v1/;
  12
  13 #include "am4372.dtsi"
  14 #include <dt-bindings/pinctrl/am43xx.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/pwm/pwm.h>
  17
  18 / {
  19         model = "TI AM43x EPOS EVM";
  20         compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
  21
  22         aliases {
  23                 display0 = &lcd0;
  24         };
  25
  26         vmmcsd_fixed: fixedregulator-sd {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "vmmcsd_fixed";
  29                 regulator-min-microvolt = <3300000>;
  30                 regulator-max-microvolt = <3300000>;
  31                 enable-active-high;
  32         };
  33
  34         lcd0: display {
  35                 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
  36                 label = "lcd";
  37
  38                 pinctrl-names = "default";
  39                 pinctrl-0 = <&lcd_pins>;
  40
  41                 /*
  42                  * SelLCDorHDMI, LOW to select HDMI. This is not really the
  43                  * panel's enable GPIO, but we don't have HDMI driver support nor
  44                  * support to switch between two displays, so using this gpio as
  45                  * panel's enable should be safe.
  46                  */
  47                 enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
  48
  49                 panel-timing {
  50                         clock-frequency = <33000000>;
  51                         hactive = <800>;
  52                         vactive = <480>;
  53                         hfront-porch = <210>;
  54                         hback-porch = <16>;
  55                         hsync-len = <30>;
  56                         vback-porch = <10>;
  57                         vfront-porch = <22>;
  58                         vsync-len = <13>;
  59                         hsync-active = <0>;
  60                         vsync-active = <0>;
  61                         de-active = <1>;
  62                         pixelclk-active = <1>;
  63                 };
  64
  65                 port {
  66                         lcd_in: endpoint {
  67                                 remote-endpoint = <&dpi_out>;
  68                         };
  69                 };
  70         };
  71
  72         am43xx_pinmux: pinmux@44e10800 {
  73                 cpsw_default: cpsw_default {
  74                         pinctrl-single,pins = <
  75                                 /* Slave 1 */
  76                                 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */
  77                                 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxerr.rmii1_rxerr */
  78                                 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
  79                                 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxdv.rmii1_rxdv */
  80                                 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
  81                                 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
  82                                 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxd1.rmii1_rxd1 */
  83                                 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_rxd0.rmii1_rxd0 */
  84                                 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0)  /* rmii1_refclk.rmii1_refclk */
  85                         >;
  86                 };
  87
  88                 cpsw_sleep: cpsw_sleep {
  89                         pinctrl-single,pins = <
  90                                 /* Slave 1 reset value */
  91                                 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  92                                 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  93                                 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  94                                 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  95                                 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  96                                 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  97                                 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
  98                                 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
  99                                 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 100                         >;
 101                 };
 102
 103                 davinci_mdio_default: davinci_mdio_default {
 104                         pinctrl-single,pins = <
 105                                 /* MDIO */
 106                                 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
 107                                 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
 108                         >;
 109                 };
 110
 111                 davinci_mdio_sleep: davinci_mdio_sleep {
 112                         pinctrl-single,pins = <
 113                                 /* MDIO reset value */
 114                                 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 115                                 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 116                         >;
 117                 };
 118
 119                 i2c0_pins: pinmux_i2c0_pins {
 120                         pinctrl-single,pins = <
 121                                 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_sda.i2c0_sda */
 122                                 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* i2c0_scl.i2c0_scl */
 123                         >;
 124                 };
 125
 126                 nand_flash_x8: nand_flash_x8 {
 127                         pinctrl-single,pins = <
 128                                 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a0.SELQSPIorNAND/GPIO */
 129                                 0x0  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
 130                                 0x4  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
 131                                 0x8  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
 132                                 0xc  (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
 133                                 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
 134                                 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
 135                                 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
 136                                 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
 137                                 0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
 138                                 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_wpn.gpmc_wpn */
 139                                 0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
 140                                 0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
 141                                 0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
 142                                 0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
 143                                 0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
 144                         >;
 145                 };
 146
 147                 ecap0_pins: backlight_pins {
 148                         pinctrl-single,pins = <
 149                                 0x164 MUX_MODE0         /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 150                         >;
 151                 };
 152
 153                 i2c2_pins: pinmux_i2c2_pins {
 154                         pinctrl-single,pins = <
 155                                 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_sda.i2c2_sda */
 156                                 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8)    /* i2c2_scl.i2c2_scl */
 157                         >;
 158                 };
 159
 160                 spi0_pins: pinmux_spi0_pins {
 161                         pinctrl-single,pins = <
 162                                 0x150 (PIN_INPUT | MUX_MODE0)           /* spi0_clk.spi0_clk */
 163                                 0x154 (PIN_OUTPUT | MUX_MODE0)           /* spi0_d0.spi0_d0 */
 164                                 0x158 (PIN_INPUT | MUX_MODE0)           /* spi0_d1.spi0_d1 */
 165                                 0x15c (PIN_OUTPUT | MUX_MODE0)          /* spi0_cs0.spi0_cs0 */
 166                         >;
 167                 };
 168
 169                 spi1_pins: pinmux_spi1_pins {
 170                         pinctrl-single,pins = <
 171                                 0x190 (PIN_INPUT | MUX_MODE3)           /* mcasp0_aclkx.spi1_clk */
 172                                 0x194 (PIN_OUTPUT | MUX_MODE3)           /* mcasp0_fsx.spi1_d0 */
 173                                 0x198 (PIN_INPUT | MUX_MODE3)           /* mcasp0_axr0.spi1_d1 */
 174                                 0x19c (PIN_OUTPUT | MUX_MODE3)          /* mcasp0_ahclkr.spi1_cs0 */
 175                         >;
 176                 };
 177
 178                 mmc1_pins: pinmux_mmc1_pins {
 179                         pinctrl-single,pins = <
 180                                 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 181                         >;
 182                 };
 183
 184                 qspi1_default: qspi1_default {
 185                         pinctrl-single,pins = <
 186                                 0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
 187                                 0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
 188                                 0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
 189                                 0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
 190                                 0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
 191                                 0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
 192                         >;
 193                 };
 194
 195                 pixcir_ts_pins: pixcir_ts_pins {
 196                         pinctrl-single,pins = <
 197                                 0x44 (PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_a1.gpio1_17 */
 198                         >;
 199                 };
 200
 201                 hdq_pins: pinmux_hdq_pins {
 202                         pinctrl-single,pins = <
 203                                 0x234 (PIN_INPUT_PULLUP | MUX_MODE1)    /* cam1_wen.hdq_gpio */
 204                         >;
 205                 };
 206
 207                 dss_pins: dss_pins {
 208                         pinctrl-single,pins = <
 209                                 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
 210                                 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 211                                 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 212                                 0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)
 213                                 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 214                                 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 215                                 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 216                                 0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
 217                                 0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
 218                                 0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 219                                 0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 220                                 0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)
 221                                 0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 222                                 0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 223                                 0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 224                                 0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)
 225                                 0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 226                                 0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 227                                 0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 228                                 0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)
 229                                 0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 230                                 0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 231                                 0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 232                                 0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
 233                                 0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
 234                                 0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
 235                                 0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
 236                                 0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
 237                         >;
 238                 };
 239
 240                 lcd_pins: lcd_pins {
 241                         pinctrl-single,pins = <
 242                                 /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
 243                                 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7)
 244                         >;
 245                 };
 246         };
 247
 248         matrix_keypad: matrix_keypad@0 {
 249                         compatible = "gpio-matrix-keypad";
 250                         debounce-delay-ms = <5>;
 251                         col-scan-delay-us = <2>;
 252
 253                         row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH         /* Bank0, pin12 */
 254                                      &gpio0 13 GPIO_ACTIVE_HIGH         /* Bank0, pin13 */
 255                                      &gpio0 14 GPIO_ACTIVE_HIGH         /* Bank0, pin14 */
 256                                      &gpio0 15 GPIO_ACTIVE_HIGH>;       /* Bank0, pin15 */
 257
 258                         col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH          /* Bank3, pin9 */
 259                                      &gpio3 10 GPIO_ACTIVE_HIGH         /* Bank3, pin10 */
 260                                      &gpio2 18 GPIO_ACTIVE_HIGH         /* Bank2, pin18 */
 261                                      &gpio2 19 GPIO_ACTIVE_HIGH>;       /* Bank2, pin19 */
 262
 263                         linux,keymap = <0x00000201      /* P1 */
 264                                 0x01000204      /* P4 */
 265                                 0x02000207      /* P7 */
 266                                 0x0300020a      /* NUMERIC_STAR */
 267                                 0x00010202      /* P2 */
 268                                 0x01010205      /* P5 */
 269                                 0x02010208      /* P8 */
 270                                 0x03010200      /* P0 */
 271                                 0x00020203      /* P3 */
 272                                 0x01020206      /* P6 */
 273                                 0x02020209      /* P9 */
 274                                 0x0302020b      /* NUMERIC_POUND */
 275                                 0x00030067      /* UP */
 276                                 0x0103006a      /* RIGHT */
 277                                 0x0203006c      /* DOWN */
 278                                 0x03030069>;    /* LEFT */
 279                 };
 280
 281         backlight {
 282                 compatible = "pwm-backlight";
 283                 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
 284                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
 285                 default-brightness-level = <8>;
 286         };
 287 };
 288
 289 &mmc1 {
 290         status = "okay";
 291         vmmc-supply = <&vmmcsd_fixed>;
 292         bus-width = <4>;
 293         pinctrl-names = "default";
 294         pinctrl-0 = <&mmc1_pins>;
 295         cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 296 };
 297
 298 &mac {
 299         pinctrl-names = "default", "sleep";
 300         pinctrl-0 = <&cpsw_default>;
 301         pinctrl-1 = <&cpsw_sleep>;
 302         status = "okay";
 303 };
 304
 305 &davinci_mdio {
 306         pinctrl-names = "default", "sleep";
 307         pinctrl-0 = <&davinci_mdio_default>;
 308         pinctrl-1 = <&davinci_mdio_sleep>;
 309         status = "okay";
 310 };
 311
 312 &cpsw_emac0 {
 313         phy_id = <&davinci_mdio>, <16>;
 314         phy-mode = "rmii";
 315 };
 316
 317 &cpsw_emac1 {
 318         phy_id = <&davinci_mdio>, <1>;
 319         phy-mode = "rmii";
 320 };
 321
 322 &phy_sel {
 323         rmii-clock-ext;
 324 };
 325
 326 &i2c0 {
 327         status = "okay";
 328         pinctrl-names = "default";
 329         pinctrl-0 = <&i2c0_pins>;
 330
 331         at24@50 {
 332                 compatible = "at24,24c256";
 333                 pagesize = <64>;
 334                 reg = <0x50>;
 335         };
 336
 337         pixcir_ts@5c {
 338                 compatible = "pixcir,pixcir_tangoc";
 339                 pinctrl-names = "default";
 340                 pinctrl-0 = <&pixcir_ts_pins>;
 341                 reg = <0x5c>;
 342                 interrupt-parent = <&gpio1>;
 343                 interrupts = <17 0>;
 344
 345                 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
 346
 347                 x-size = <1024>;
 348                 y-size = <600>;
 349         };
 350 };
 351
 352 &i2c2 {
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&i2c2_pins>;
 355         status = "okay";
 356 };
 357
 358 &gpio0 {
 359         status = "okay";
 360 };
 361
 362 &gpio1 {
 363         status = "okay";
 364 };
 365
 366 &gpio2 {
 367         status = "okay";
 368 };
 369
 370 &gpio3 {
 371         status = "okay";
 372 };
 373
 374 &elm {
 375         status = "okay";
 376 };
 377
 378 &gpmc {
 379         status = "okay";
 380         pinctrl-names = "default";
 381         pinctrl-0 = <&nand_flash_x8>;
 382         ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
 383         nand@0,0 {
 384                 reg = <0 0 0>; /* CS0, offset 0 */
 385                 ti,nand-ecc-opt = "bch8";
 386                 ti,elm-id = <&elm>;
 387                 nand-bus-width = <8>;
 388                 gpmc,device-width = <1>;
 389                 gpmc,sync-clk-ps = <0>;
 390                 gpmc,cs-on-ns = <0>;
 391                 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
 392                 gpmc,cs-wr-off-ns = <40>;
 393                 gpmc,adv-on-ns = <0>;  /* cs-on-ns */
 394                 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
 395                 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
 396                 gpmc,we-on-ns = <0>;   /* cs-on-ns */
 397                 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
 398                 gpmc,oe-on-ns = <3>;  /* cs-on-ns + tRR + 2 */
 399                 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
 400                 gpmc,access-ns = <30>; /* tCEA + 4*/
 401                 gpmc,rd-cycle-ns = <40>;
 402                 gpmc,wr-cycle-ns = <40>;
 403                 gpmc,wait-on-read = "true";
 404                 gpmc,wait-on-write = "true";
 405                 gpmc,bus-turnaround-ns = <0>;
 406                 gpmc,cycle2cycle-delay-ns = <0>;
 407                 gpmc,clk-activation-ns = <0>;
 408                 gpmc,wait-monitoring-ns = <0>;
 409                 gpmc,wr-access-ns = <40>;
 410                 gpmc,wr-data-mux-bus-ns = <0>;
 411                 /* MTD partition table */
 412                 /* All SPL-* partitions are sized to minimal length
 413                  * which can be independently programmable. For
 414                  * NAND flash this is equal to size of erase-block */
 415                 #address-cells = <1>;
 416                 #size-cells = <1>;
 417                 partition@0 {
 418                         label = "NAND.SPL";
 419                         reg = <0x00000000 0x00040000>;
 420                 };
 421                 partition@1 {
 422                         label = "NAND.SPL.backup1";
 423                         reg = <0x00040000 0x00040000>;
 424                 };
 425                 partition@2 {
 426                         label = "NAND.SPL.backup2";
 427                         reg = <0x00080000 0x00040000>;
 428                 };
 429                 partition@3 {
 430                         label = "NAND.SPL.backup3";
 431                         reg = <0x000C0000 0x00040000>;
 432                 };
 433                 partition@4 {
 434                         label = "NAND.u-boot-spl-os";
 435                         reg = <0x00100000 0x00080000>;
 436                 };
 437                 partition@5 {
 438                         label = "NAND.u-boot";
 439                         reg = <0x00180000 0x00100000>;
 440                 };
 441                 partition@6 {
 442                         label = "NAND.u-boot-env";
 443                         reg = <0x00280000 0x00040000>;
 444                 };
 445                 partition@7 {
 446                         label = "NAND.u-boot-env.backup1";
 447                         reg = <0x002C0000 0x00040000>;
 448                 };
 449                 partition@8 {
 450                         label = "NAND.kernel";
 451                         reg = <0x00300000 0x00700000>;
 452                 };
 453                 partition@9 {
 454                         label = "NAND.file-system";
 455                         reg = <0x00a00000 0x1f600000>;
 456                 };
 457         };
 458 };
 459
 460 &epwmss0 {
 461         status = "okay";
 462 };
 463
 464 &ecap0 {
 465                 status = "okay";
 466                 pinctrl-names = "default";
 467                 pinctrl-0 = <&ecap0_pins>;
 468 };
 469
 470 &spi0 {
 471         pinctrl-names = "default";
 472         pinctrl-0 = <&spi0_pins>;
 473         status = "okay";
 474 };
 475
 476 &spi1 {
 477         pinctrl-names = "default";
 478         pinctrl-0 = <&spi1_pins>;
 479         status = "okay";
 480 };
 481
 482 &usb2_phy1 {
 483         status = "okay";
 484 };
 485
 486 &usb1 {
 487         dr_mode = "peripheral";
 488         status = "okay";
 489 };
 490
 491 &usb2_phy2 {
 492         status = "okay";
 493 };
 494
 495 &usb2 {
 496         dr_mode = "host";
 497         status = "okay";
 498 };
 499
 500 &qspi {
 501         status = "okay";
 502         pinctrl-names = "default";
 503         pinctrl-0 = <&qspi1_default>;
 504
 505         spi-max-frequency = <48000000>;
 506         m25p80@0 {
 507                 compatible = "mx66l51235l";
 508                 spi-max-frequency = <48000000>;
 509                 reg = <0>;
 510                 spi-cpol;
 511                 spi-cpha;
 512                 spi-tx-bus-width = <1>;
 513                 spi-rx-bus-width = <4>;
 514                 #address-cells = <1>;
 515                 #size-cells = <1>;
 516
 517                 /* MTD partition table.
 518                  * The ROM checks the first 512KiB
 519                  * for a valid file to boot(XIP).
 520                  */
 521                 partition@0 {
 522                         label = "QSPI.U_BOOT";
 523                         reg = <0x00000000 0x000080000>;
 524                 };
 525                 partition@1 {
 526                         label = "QSPI.U_BOOT.backup";
 527                         reg = <0x00080000 0x00080000>;
 528                 };
 529                 partition@2 {
 530                         label = "QSPI.U-BOOT-SPL_OS";
 531                         reg = <0x00100000 0x00010000>;
 532                 };
 533                 partition@3 {
 534                         label = "QSPI.U_BOOT_ENV";
 535                         reg = <0x00110000 0x00010000>;
 536                 };
 537                 partition@4 {
 538                         label = "QSPI.U-BOOT-ENV.backup";
 539                         reg = <0x00120000 0x00010000>;
 540                 };
 541                 partition@5 {
 542                         label = "QSPI.KERNEL";
 543                         reg = <0x00130000 0x0800000>;
 544                 };
 545                 partition@6 {
 546                         label = "QSPI.FILESYSTEM";
 547                         reg = <0x00930000 0x36D0000>;
 548                 };
 549         };
 550 };
 551
 552 &hdq {
 553         status = "okay";
 554         pinctrl-names = "default";
 555         pinctrl-0 = <&hdq_pins>;
 556 };
 557
 558 &dss {
 559         status = "ok";
 560
 561         pinctrl-names = "default";
 562         pinctrl-0 = <&dss_pins>;
 563
 564         port {
 565                 dpi_out: endpoint@0 {
 566                         remote-endpoint = <&lcd_in>;
 567                         data-lines = <24>;
 568                 };
 569         };
 570 };