arch/arm/boot/dts/am437x-gp-evm.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5
   6 /* AM437x GP EVM */
   7
   8 /dts-v1/;
   9
  10 #include "am4372.dtsi"
  11 #include <dt-bindings/pinctrl/am43xx.h>
  12 #include <dt-bindings/pwm/pwm.h>
  13 #include <dt-bindings/gpio/gpio.h>
  14
  15 / {
  16         model = "TI AM437x GP EVM";
  17         compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
  18
  19         aliases {
  20                 display0 = &lcd0;
  21         };
  22
  23         chosen {
  24                 stdout-path = &uart0;
  25         };
  26
  27         evm_v3_3d: fixedregulator-v3_3d {
  28                 compatible = "regulator-fixed";
  29                 regulator-name = "evm_v3_3d";
  30                 regulator-min-microvolt = <3300000>;
  31                 regulator-max-microvolt = <3300000>;
  32                 enable-active-high;
  33         };
  34
  35         vtt_fixed: fixedregulator-vtt {
  36                 compatible = "regulator-fixed";
  37                 regulator-name = "vtt_fixed";
  38                 regulator-min-microvolt = <1500000>;
  39                 regulator-max-microvolt = <1500000>;
  40                 regulator-always-on;
  41                 regulator-boot-on;
  42                 enable-active-high;
  43                 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
  44         };
  45
  46         vmmcwl_fixed: fixedregulator-mmcwl {
  47                 compatible = "regulator-fixed";
  48                 regulator-name = "vmmcwl_fixed";
  49                 regulator-min-microvolt = <1800000>;
  50                 regulator-max-microvolt = <1800000>;
  51                 gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>;
  52                 enable-active-high;
  53         };
  54
  55         lcd_bl: backlight {
  56                 compatible = "pwm-backlight";
  57                 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
  58                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
  59                 default-brightness-level = <8>;
  60         };
  61
  62         matrix_keypad: matrix_keypad0 {
  63                 compatible = "gpio-matrix-keypad";
  64                 debounce-delay-ms = <5>;
  65                 col-scan-delay-us = <2>;
  66
  67                 pinctrl-names = "default", "sleep";
  68                 pinctrl-0 = <&matrix_keypad_default>;
  69                 pinctrl-1 = <&matrix_keypad_sleep>;
  70
  71                 wakeup-source;
  72
  73                 row-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH /* Bank0, pin3 */
  74                                 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
  75                                 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
  76
  77                 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
  78                                 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
  79
  80                 linux,keymap = <0x00000201      /* P1 */
  81                                 0x00010202      /* P2 */
  82                                 0x01000067      /* UP */
  83                                 0x0101006a      /* RIGHT */
  84                                 0x02000069      /* LEFT */
  85                                 0x0201006c>;      /* DOWN */
  86                 };
  87
  88         lcd0: display {
  89                 compatible = "osddisplays,osd070t1718-19ts", "panel-dpi";
  90                 label = "lcd";
  91
  92                 backlight = <&lcd_bl>;
  93
  94                 panel-timing {
  95                         clock-frequency = <33000000>;
  96                         hactive = <800>;
  97                         vactive = <480>;
  98                         hfront-porch = <210>;
  99                         hback-porch = <16>;
 100                         hsync-len = <30>;
 101                         vback-porch = <10>;
 102                         vfront-porch = <22>;
 103                         vsync-len = <13>;
 104                         hsync-active = <0>;
 105                         vsync-active = <0>;
 106                         de-active = <1>;
 107                         pixelclk-active = <1>;
 108                 };
 109
 110                 port {
 111                         lcd_in: endpoint {
 112                                 remote-endpoint = <&dpi_out>;
 113                         };
 114                 };
 115         };
 116
 117         /* fixed 12MHz oscillator */
 118         refclk: oscillator {
 119                 #clock-cells = <0>;
 120                 compatible = "fixed-clock";
 121                 clock-frequency = <12000000>;
 122         };
 123
 124         /* fixed 32k external oscillator clock */
 125         clk_32k_rtc: clk_32k_rtc {
 126                 #clock-cells = <0>;
 127                 compatible = "fixed-clock";
 128                 clock-frequency = <32768>;
 129         };
 130
 131         sound0: sound0 {
 132                 compatible = "simple-audio-card";
 133                 simple-audio-card,name = "AM437x-GP-EVM";
 134                 simple-audio-card,widgets =
 135                         "Headphone", "Headphone Jack",
 136                         "Line", "Line In";
 137                 simple-audio-card,routing =
 138                         "Headphone Jack",       "HPLOUT",
 139                         "Headphone Jack",       "HPROUT",
 140                         "LINE1L",               "Line In",
 141                         "LINE1R",               "Line In";
 142                 simple-audio-card,format = "dsp_b";
 143                 simple-audio-card,bitclock-master = <&sound0_master>;
 144                 simple-audio-card,frame-master = <&sound0_master>;
 145                 simple-audio-card,bitclock-inversion;
 146
 147                 simple-audio-card,cpu {
 148                         sound-dai = <&mcasp1>;
 149                         system-clock-frequency = <12000000>;
 150                 };
 151
 152                 sound0_master: simple-audio-card,codec {
 153                         sound-dai = <&tlv320aic3106>;
 154                         system-clock-frequency = <12000000>;
 155                 };
 156         };
 157
 158         beeper: beeper {
 159                 compatible = "gpio-beeper";
 160                 pinctrl-names = "default";
 161                 pinctrl-0 = <&beeper_pins_default>;
 162                 pinctrl-1 = <&beeper_pins_sleep>;
 163                 gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
 164         };
 165 };
 166
 167 &am43xx_pinmux {
 168         pinctrl-names = "default", "sleep";
 169         pinctrl-0 = <&wlan_pins_default &ddr3_vtt_toggle_default &unused_pins &debugss_pins>;
 170         pinctrl-1 = <&wlan_pins_sleep>;
 171
 172         ddr3_vtt_toggle_default: ddr_vtt_toggle_default {
 173                 pinctrl-single,pins = <
 174                         0x25C (DS0_PULL_UP_DOWN_EN | PIN_OUTPUT_PULLUP | DS0_FORCE_OFF_MODE | MUX_MODE7) /* spi0_cs0.gpio5_7 */
 175                 >;
 176         };
 177
 178         i2c0_pins: i2c0_pins {
 179                 pinctrl-single,pins = <
 180                         AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
 181                         AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
 182                 >;
 183         };
 184
 185         i2c1_pins: i2c1_pins {
 186                 pinctrl-single,pins = <
 187                         AM4372_IOPAD(0x95c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
 188                         AM4372_IOPAD(0x958, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
 189                 >;
 190         };
 191
 192         mmc1_pins: pinmux_mmc1_pins {
 193                 pinctrl-single,pins = <
 194                         AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 195                 >;
 196         };
 197
 198         ecap0_pins: backlight_pins {
 199                 pinctrl-single,pins = <
 200                         AM4372_IOPAD(0x964, MUX_MODE0)       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 201                 >;
 202         };
 203
 204         pixcir_ts_pins: pixcir_ts_pins {
 205                 pinctrl-single,pins = <
 206                         AM4372_IOPAD(0xa64, PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
 207                 >;
 208         };
 209
 210         cpsw_default: cpsw_default {
 211                 pinctrl-single,pins = <
 212                         /* Slave 1 */
 213                         AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txen.rgmii1_txen */
 214                         AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxdv.rgmii1_rxctl */
 215                         AM4372_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_txd3 */
 216                         AM4372_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_txd2 */
 217                         AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd1.rgmii1_txd1 */
 218                         AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txd0.rgmii1_txd0 */
 219                         AM4372_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)    /* mii1_txclk.rmii1_tclk */
 220                         AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxclk.rmii1_rclk */
 221                         AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd1.rgmii1_rxd3 */
 222                         AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd0.rgmii1_rxd2 */
 223                         AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd1.rgmii1_rxd1 */
 224                         AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)     /* mii1_rxd0.rgmii1_rxd0 */
 225                 >;
 226         };
 227
 228         cpsw_sleep: cpsw_sleep {
 229                 pinctrl-single,pins = <
 230                         /* Slave 1 reset value */
 231                         AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
 232                         AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
 233                         AM4372_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 234                         AM4372_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
 235                         AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
 236                         AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
 237                         AM4372_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 238                         AM4372_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
 239                         AM4372_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
 240                         AM4372_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
 241                         AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 242                         AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
 243                 >;
 244         };
 245
 246         davinci_mdio_default: davinci_mdio_default {
 247                 pinctrl-single,pins = <
 248                         /* MDIO */
 249                         AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)       /* mdio_data.mdio_data */
 250                         AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)                      /* mdio_clk.mdio_clk */
 251                 >;
 252         };
 253
 254         davinci_mdio_sleep: davinci_mdio_sleep {
 255                 pinctrl-single,pins = <
 256                         /* MDIO reset value */
 257                         AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
 258                         AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 259                 >;
 260         };
 261
 262         nand_flash_x8: nand_flash_x8 {
 263                 pinctrl-single,pins = <
 264                         AM4372_IOPAD(0x800, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad0.gpmc_ad0 */
 265                         AM4372_IOPAD(0x804, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad1.gpmc_ad1 */
 266                         AM4372_IOPAD(0x808, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad2.gpmc_ad2 */
 267                         AM4372_IOPAD(0x80c, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad3.gpmc_ad3 */
 268                         AM4372_IOPAD(0x810, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad4.gpmc_ad4 */
 269                         AM4372_IOPAD(0x814, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad5.gpmc_ad5 */
 270                         AM4372_IOPAD(0x818, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad6.gpmc_ad6 */
 271                         AM4372_IOPAD(0x81c, PIN_INPUT  | MUX_MODE0)     /* gpmc_ad7.gpmc_ad7 */
 272                         AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)       /* gpmc_wait0.gpmc_wait0 */
 273                         AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gpmc_wpn.gpmc_wpn */
 274                         AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_csn0.gpmc_csn0  */
 275                         AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)             /* gpmc_advn_ale.gpmc_advn_ale */
 276                         AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)             /* gpmc_oen_ren.gpmc_oen_ren */
 277                         AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)             /* gpmc_wen.gpmc_wen */
 278                         AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)             /* gpmc_be0n_cle.gpmc_be0n_cle */
 279                 >;
 280         };
 281
 282         dss_pins: dss_pins {
 283                 pinctrl-single,pins = <
 284                         AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
 285                         AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1)
 286                         AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1)
 287                         AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1)
 288                         AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1)
 289                         AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1)
 290                         AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1)
 291                         AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
 292                         AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
 293                         AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 294                         AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 295                         AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0)
 296                         AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0)
 297                         AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 298                         AM4372_IOPAD(0x8b8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 299                         AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0)
 300                         AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0)
 301                         AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 302                         AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 303                         AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0)
 304                         AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0)
 305                         AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0)
 306                         AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0)
 307                         AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
 308                         AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
 309                         AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
 310                         AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
 311                         AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
 312
 313                 >;
 314         };
 315
 316         display_mux_pins: display_mux_pins {
 317                 pinctrl-single,pins = <
 318                         /* GPIO 5_8 to select LCD / HDMI */
 319                         AM4372_IOPAD(0xa38, PIN_OUTPUT_PULLUP | MUX_MODE7)
 320                 >;
 321         };
 322
 323         dcan0_default: dcan0_default_pins {
 324                 pinctrl-single,pins = <
 325                         AM4372_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)             /* uart1_ctsn.d_can0_tx */
 326                         AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE2)       /* uart1_rtsn.d_can0_rx */
 327                 >;
 328         };
 329
 330         dcan0_sleep: dcan0_sleep_pins {
 331                 pinctrl-single,pins = <
 332                         AM4372_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE7)       /* uart1_ctsn.gpio0_12 */
 333                         AM4372_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE7)       /* uart1_rtsn.gpio0_13 */
 334                 >;
 335         };
 336
 337         dcan1_default: dcan1_default_pins {
 338                 pinctrl-single,pins = <
 339                         AM4372_IOPAD(0x980, PIN_OUTPUT | MUX_MODE2)             /* uart1_rxd.d_can1_tx */
 340                         AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE2)       /* uart1_txd.d_can1_rx */
 341                 >;
 342         };
 343
 344         dcan1_sleep: dcan1_sleep_pins {
 345                 pinctrl-single,pins = <
 346                         AM4372_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE7)       /* uart1_rxd.gpio0_14 */
 347                         AM4372_IOPAD(0x984, PIN_INPUT_PULLUP | MUX_MODE7)       /* uart1_txd.gpio0_15 */
 348                 >;
 349         };
 350
 351         vpfe0_pins_default: vpfe0_pins_default {
 352                 pinctrl-single,pins = <
 353                         AM4372_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_hd mode 0*/
 354                         AM4372_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_vd mode 0*/
 355                         AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_pclk mode 0*/
 356                         AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data8 mode 0*/
 357                         AM4372_IOPAD(0x9c8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data9 mode 0*/
 358                         AM4372_IOPAD(0xa08, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data0 mode 0*/
 359                         AM4372_IOPAD(0xa0c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data1 mode 0*/
 360                         AM4372_IOPAD(0xa10, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data2 mode 0*/
 361                         AM4372_IOPAD(0xa14, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data3 mode 0*/
 362                         AM4372_IOPAD(0xa18, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data4 mode 0*/
 363                         AM4372_IOPAD(0xa1c, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data5 mode 0*/
 364                         AM4372_IOPAD(0xa20, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data6 mode 0*/
 365                         AM4372_IOPAD(0xa24, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam0_data7 mode 0*/
 366                 >;
 367         };
 368
 369         vpfe0_pins_sleep: vpfe0_pins_sleep {
 370                 pinctrl-single,pins = <
 371                         AM4372_IOPAD(0x9b0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_hd mode 0*/
 372                         AM4372_IOPAD(0x9b4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_vd mode 0*/
 373                         AM4372_IOPAD(0x9c0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_pclk mode 0*/
 374                         AM4372_IOPAD(0x9c4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data8 mode 0*/
 375                         AM4372_IOPAD(0x9c8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data9 mode 0*/
 376                         AM4372_IOPAD(0xa08, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data0 mode 0*/
 377                         AM4372_IOPAD(0xa0c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data1 mode 0*/
 378                         AM4372_IOPAD(0xa10, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data2 mode 0*/
 379                         AM4372_IOPAD(0xa14, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data3 mode 0*/
 380                         AM4372_IOPAD(0xa18, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data4 mode 0*/
 381                         AM4372_IOPAD(0xa1c, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data5 mode 0*/
 382                         AM4372_IOPAD(0xa20, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data6 mode 0*/
 383                         AM4372_IOPAD(0xa24, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam0_data7 mode 0*/
 384                 >;
 385         };
 386
 387         vpfe1_pins_default: vpfe1_pins_default {
 388                 pinctrl-single,pins = <
 389                         AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data9 mode 0*/
 390                         AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data8 mode 0*/
 391                         AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_hd mode 0*/
 392                         AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_vd mode 0*/
 393                         AM4372_IOPAD(0x9dC, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_pclk mode 0*/
 394                         AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data0 mode 0*/
 395                         AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data1 mode 0*/
 396                         AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data2 mode 0*/
 397                         AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data3 mode 0*/
 398                         AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data4 mode 0*/
 399                         AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data5 mode 0*/
 400                         AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data6 mode 0*/
 401                         AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0)  /* cam1_data7 mode 0*/
 402                 >;
 403         };
 404
 405         vpfe1_pins_sleep: vpfe1_pins_sleep {
 406                 pinctrl-single,pins = <
 407                         AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data9 mode 0*/
 408                         AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data8 mode 0*/
 409                         AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_hd mode 0*/
 410                         AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_vd mode 0*/
 411                         AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_pclk mode 0*/
 412                         AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data0 mode 0*/
 413                         AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data1 mode 0*/
 414                         AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data2 mode 0*/
 415                         AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data3 mode 0*/
 416                         AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data4 mode 0*/
 417                         AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data5 mode 0*/
 418                         AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data6 mode 0*/
 419                         AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)  /* cam1_data7 mode 0*/
 420                 >;
 421         };
 422
 423         mmc3_pins_default: pinmux_mmc3_pins_default {
 424                 pinctrl-single,pins = <
 425                         AM4372_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_clk.mmc2_clk */
 426                         AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_csn3.mmc2_cmd */
 427                         AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a1.mmc2_dat0 */
 428                         AM4372_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a2.mmc2_dat1 */
 429                         AM4372_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_a3.mmc2_dat2 */
 430                         AM4372_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3)      /* gpmc_be1n.mmc2_dat3 */
 431                 >;
 432         };
 433
 434         mmc3_pins_sleep: pinmux_mmc3_pins_sleep {
 435                 pinctrl-single,pins = <
 436                         AM4372_IOPAD(0x88c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_clk.mmc2_clk */
 437                         AM4372_IOPAD(0x888, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_csn3.mmc2_cmd */
 438                         AM4372_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a1.mmc2_dat0 */
 439                         AM4372_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a2.mmc2_dat1 */
 440                         AM4372_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_a3.mmc2_dat2 */
 441                         AM4372_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* gpmc_be1n.mmc2_dat3 */
 442                 >;
 443         };
 444
 445         wlan_pins_default: pinmux_wlan_pins_default {
 446                 pinctrl-single,pins = <
 447                         AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)            /* gpmc_a4.gpio1_20 WL_EN */
 448                         AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)      /* gpmc_a7.gpio1_23 WL_IRQ*/
 449                         AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7)            /* gpmc_a0.gpio1_16 BT_EN*/
 450                 >;
 451         };
 452
 453         wlan_pins_sleep: pinmux_wlan_pins_sleep {
 454                 pinctrl-single,pins = <
 455                         AM4372_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)            /* gpmc_a4.gpio1_20 WL_EN */
 456                         AM4372_IOPAD(0x85c, PIN_INPUT | WAKEUP_ENABLE | MUX_MODE7)      /* gpmc_a7.gpio1_23 WL_IRQ*/
 457                         AM4372_IOPAD(0x840, PIN_OUTPUT_PULLUP | MUX_MODE7)              /* gpmc_a0.gpio1_16 BT_EN*/
 458                 >;
 459         };
 460
 461         uart3_pins: uart3_pins {
 462                 pinctrl-single,pins = <
 463                         AM4372_IOPAD(0xa28, PIN_INPUT | MUX_MODE0)              /* uart3_rxd.uart3_rxd */
 464                         AM4372_IOPAD(0xa2c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_txd.uart3_txd */
 465                         AM4372_IOPAD(0xa30, PIN_INPUT_PULLUP | MUX_MODE0)       /* uart3_ctsn.uart3_ctsn */
 466                         AM4372_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
 467                 >;
 468         };
 469
 470         mcasp1_pins: mcasp1_pins {
 471                 pinctrl-single,pins = <
 472                         AM4372_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4)    /* mii1_col.mcasp1_axr2 */
 473                         AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4)     /* mii1_crs.mcasp1_aclkx */
 474                         AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4)     /* mii1_rxerr.mcasp1_fsx */
 475                         AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4)     /* rmii1_ref_clk.mcasp1_axr3 */
 476                 >;
 477         };
 478
 479         mcasp1_sleep_pins: mcasp1_sleep_pins {
 480                 pinctrl-single,pins = <
 481                         AM4372_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
 482                         AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 483                         AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
 484                         AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
 485                 >;
 486         };
 487
 488         gpio0_pins: gpio0_pins {
 489                 pinctrl-single,pins = <
 490                         AM4372_IOPAD(0xa6c, PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
 491                 >;
 492         };
 493
 494         emmc_pins_default: emmc_pins_default {
 495                 pinctrl-single,pins = <
 496                         AM4372_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
 497                         AM4372_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
 498                         AM4372_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
 499                         AM4372_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
 500                         AM4372_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
 501                         AM4372_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
 502                         AM4372_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
 503                         AM4372_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
 504                         AM4372_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
 505                         AM4372_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
 506                 >;
 507         };
 508
 509         emmc_pins_sleep: emmc_pins_sleep {
 510                 pinctrl-single,pins = <
 511                         AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
 512                         AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
 513                         AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
 514                         AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
 515                         AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
 516                         AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
 517                         AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
 518                         AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
 519                         AM4372_IOPAD(0x880, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
 520                         AM4372_IOPAD(0x884, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
 521                 >;
 522         };
 523
 524         beeper_pins_default: beeper_pins_default {
 525                 pinctrl-single,pins = <
 526                         AM4372_IOPAD(0x9e0, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* cam1_field.gpio4_12 */
 527                 >;
 528         };
 529
 530         beeper_pins_sleep: beeper_pins_sleep {
 531                 pinctrl-single,pins = <
 532                         AM4372_IOPAD(0x9e0, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* cam1_field.gpio4_12 */
 533                 >;
 534         };
 535
 536         unused_pins: unused_pins {
 537                 pinctrl-single,pins = <
 538                         AM4372_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
 539                         AM4372_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
 540                         AM4372_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
 541                         AM4372_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
 542                         AM4372_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
 543                         AM4372_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 544                         AM4372_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7)
 545                         AM4372_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE7)
 546                         AM4372_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE7)
 547                         AM4372_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE7)
 548                         AM4372_IOPAD(0x99c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 549                         AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7)
 550                         AM4372_IOPAD(0xa3c, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
 551                         AM4372_IOPAD(0xa40, PIN_INPUT_PULLDOWN | MUX_MODE7)
 552                         AM4372_IOPAD(0xa44, PIN_INPUT_PULLDOWN | MUX_MODE7)
 553                         AM4372_IOPAD(0xa48, PIN_INPUT_PULLDOWN | MUX_MODE7)
 554                         AM4372_IOPAD(0xa4c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 555                         AM4372_IOPAD(0xa50, PIN_INPUT_PULLDOWN | MUX_MODE7)
 556                         AM4372_IOPAD(0xa54, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
 557                         AM4372_IOPAD(0xa58, PIN_INPUT_PULLDOWN | MUX_MODE7)
 558                         AM4372_IOPAD(0xa60, PIN_INPUT | PULL_DISABLE | MUX_MODE7)
 559                         AM4372_IOPAD(0xa68, PIN_INPUT_PULLDOWN | MUX_MODE7)
 560                         AM4372_IOPAD(0xa70, PIN_INPUT_PULLDOWN | MUX_MODE7)
 561                         AM4372_IOPAD(0xa78, PIN_INPUT_PULLDOWN | MUX_MODE7)
 562                         AM4372_IOPAD(0xa7c, PIN_INPUT | PULL_DISABLE)
 563                         AM4372_IOPAD(0xac8, PIN_INPUT_PULLDOWN)
 564                         AM4372_IOPAD(0xad4, PIN_INPUT_PULLDOWN)
 565                         AM4372_IOPAD(0xad8, PIN_INPUT_PULLDOWN | MUX_MODE7)
 566                         AM4372_IOPAD(0xadc, PIN_INPUT_PULLDOWN | MUX_MODE7)
 567                         AM4372_IOPAD(0xae0, PIN_INPUT_PULLDOWN | MUX_MODE7)
 568                         AM4372_IOPAD(0xae4, PIN_INPUT_PULLDOWN | MUX_MODE7)
 569                         AM4372_IOPAD(0xae8, PIN_INPUT_PULLDOWN | MUX_MODE7)
 570                         AM4372_IOPAD(0xaec, PIN_INPUT_PULLDOWN | MUX_MODE7)
 571                         AM4372_IOPAD(0xaf0, PIN_INPUT_PULLDOWN | MUX_MODE7)
 572                         AM4372_IOPAD(0xaf4, PIN_INPUT_PULLDOWN | MUX_MODE7)
 573                         AM4372_IOPAD(0xaf8, PIN_INPUT_PULLDOWN | MUX_MODE7)
 574                         AM4372_IOPAD(0xafc, PIN_INPUT_PULLDOWN | MUX_MODE7)
 575                         AM4372_IOPAD(0xb00, PIN_INPUT_PULLDOWN | MUX_MODE7)
 576                         AM4372_IOPAD(0xb04, PIN_INPUT_PULLDOWN | MUX_MODE7)
 577                         AM4372_IOPAD(0xb08, PIN_INPUT_PULLDOWN | MUX_MODE7)
 578                         AM4372_IOPAD(0xb0c, PIN_INPUT_PULLDOWN | MUX_MODE7)
 579                         AM4372_IOPAD(0xb10, PIN_INPUT_PULLDOWN | MUX_MODE7)
 580                         AM4372_IOPAD(0xb14, PIN_INPUT_PULLDOWN | MUX_MODE7)
 581                         AM4372_IOPAD(0xb18, PIN_INPUT_PULLDOWN | MUX_MODE7)
 582                 >;
 583         };
 584
 585         debugss_pins: pinmux_debugss_pins {
 586                 pinctrl-single,pins = <
 587                         AM4372_IOPAD(0xa90, PIN_INPUT_PULLDOWN)
 588                         AM4372_IOPAD(0xa94, PIN_INPUT_PULLDOWN)
 589                         AM4372_IOPAD(0xa98, PIN_INPUT_PULLDOWN)
 590                         AM4372_IOPAD(0xa9c, PIN_INPUT_PULLDOWN)
 591                         AM4372_IOPAD(0xaa0, PIN_INPUT_PULLDOWN)
 592                         AM4372_IOPAD(0xaa4, PIN_INPUT_PULLDOWN)
 593                         AM4372_IOPAD(0xaa8, PIN_INPUT_PULLDOWN)
 594                 >;
 595         };
 596
 597         uart0_pins_default: uart0_pins_default {
 598                 pinctrl-single,pins = <
 599                         AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */
 600                         AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */
 601                         AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
 602                         AM4372_IOPAD(0x974, PIN_INPUT | PULL_DISABLE | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
 603                 >;
 604         };
 605
 606         uart0_pins_sleep: uart0_pins_sleep {
 607                 pinctrl-single,pins = <
 608                         AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_ctsn.uart0_ctsn */
 609                         AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* uart0_rtsn.uart0_rtsn */
 610                         AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */
 611                         AM4372_IOPAD(0x974, PIN_INPUT_PULLDOWN | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */
 612                 >;
 613         };
 614
 615         matrix_keypad_default: matrix_keypad_default {
 616                 pinctrl-single,pins = <
 617                         AM4372_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7)
 618                         AM4372_IOPAD(0x9a8, PIN_OUTPUT | MUX_MODE7)
 619                         AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9)
 620                         AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)
 621                 >;
 622         };
 623
 624         matrix_keypad_sleep: matrix_keypad_sleep {
 625                 pinctrl-single,pins = <
 626                         AM4372_IOPAD(0x9a4, PULL_UP | MUX_MODE7)
 627                         AM4372_IOPAD(0x9a8, PULL_UP | MUX_MODE7)
 628                         AM4372_IOPAD(0x9ac, PIN_INPUT | PULL_DISABLE | MUX_MODE9)
 629                         AM4372_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)
 630                 >;
 631         };
 632 };
 633
 634 &uart0 {
 635         status = "okay";
 636         pinctrl-names = "default", "sleep";
 637         pinctrl-0 = <&uart0_pins_default>;
 638         pinctrl-1 = <&uart0_pins_sleep>;
 639 };
 640
 641 &i2c0 {
 642         status = "okay";
 643         pinctrl-names = "default";
 644         pinctrl-0 = <&i2c0_pins>;
 645         clock-frequency = <100000>;
 646
 647         tps65218: tps65218@24 {
 648                 reg = <0x24>;
 649                 compatible = "ti,tps65218";
 650                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */
 651                 interrupt-controller;
 652                 #interrupt-cells = <2>;
 653
 654                 dcdc1: regulator-dcdc1 {
 655                         regulator-name = "vdd_core";
 656                         regulator-min-microvolt = <912000>;
 657                         regulator-max-microvolt = <1144000>;
 658                         regulator-boot-on;
 659                         regulator-always-on;
 660                 };
 661
 662                 dcdc2: regulator-dcdc2 {
 663                         regulator-name = "vdd_mpu";
 664                         regulator-min-microvolt = <912000>;
 665                         regulator-max-microvolt = <1378000>;
 666                         regulator-boot-on;
 667                         regulator-always-on;
 668                 };
 669
 670                 dcdc3: regulator-dcdc3 {
 671                         regulator-name = "vdcdc3";
 672                         regulator-boot-on;
 673                         regulator-always-on;
 674                         regulator-state-mem {
 675                                 regulator-on-in-suspend;
 676                         };
 677                         regulator-state-disk {
 678                                 regulator-off-in-suspend;
 679                         };
 680                 };
 681
 682                 dcdc5: regulator-dcdc5 {
 683                         regulator-name = "v1_0bat";
 684                         regulator-min-microvolt = <1000000>;
 685                         regulator-max-microvolt = <1000000>;
 686                         regulator-boot-on;
 687                         regulator-always-on;
 688                         regulator-state-mem {
 689                                 regulator-on-in-suspend;
 690                         };
 691                 };
 692
 693                 dcdc6: regulator-dcdc6 {
 694                         regulator-name = "v1_8bat";
 695                         regulator-min-microvolt = <1800000>;
 696                         regulator-max-microvolt = <1800000>;
 697                         regulator-boot-on;
 698                         regulator-always-on;
 699                         regulator-state-mem {
 700                                 regulator-on-in-suspend;
 701                         };
 702                 };
 703
 704                 ldo1: regulator-ldo1 {
 705                         regulator-min-microvolt = <1800000>;
 706                         regulator-max-microvolt = <1800000>;
 707                         regulator-boot-on;
 708                         regulator-always-on;
 709                 };
 710         };
 711
 712         ov2659@30 {
 713                 compatible = "ovti,ov2659";
 714                 reg = <0x30>;
 715
 716                 clocks = <&refclk 0>;
 717                 clock-names = "xvclk";
 718
 719                 port {
 720                         ov2659_0: endpoint {
 721                                 remote-endpoint = <&vpfe1_ep>;
 722                                 link-frequencies = /bits/ 64 <70000000>;
 723                         };
 724                 };
 725         };
 726 };
 727
 728 &i2c1 {
 729         status = "okay";
 730         pinctrl-names = "default";
 731         pinctrl-0 = <&i2c1_pins>;
 732         pixcir_ts@5c {
 733                 compatible = "pixcir,pixcir_tangoc";
 734                 pinctrl-names = "default";
 735                 pinctrl-0 = <&pixcir_ts_pins>;
 736                 reg = <0x5c>;
 737
 738                 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 739
 740                 /*
 741                  * 0x264 represents the offset of padconf register of
 742                  * gpio3_22 from am43xx_pinmux base.
 743                  */
 744                 interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>,
 745                                       <&am43xx_pinmux 0x264>;
 746                 interrupt-names = "tsc", "wakeup";
 747
 748                 touchscreen-size-x = <1024>;
 749                 touchscreen-size-y = <600>;
 750                 wakeup-source;
 751         };
 752
 753         ov2659@30 {
 754                 compatible = "ovti,ov2659";
 755                 reg = <0x30>;
 756
 757                 clocks = <&refclk 0>;
 758                 clock-names = "xvclk";
 759
 760                 port {
 761                         ov2659_1: endpoint {
 762                                 remote-endpoint = <&vpfe0_ep>;
 763                                 link-frequencies = /bits/ 64 <70000000>;
 764                         };
 765                 };
 766         };
 767
 768         tlv320aic3106: tlv320aic3106@1b {
 769                 #sound-dai-cells = <0>;
 770                 compatible = "ti,tlv320aic3106";
 771                 reg = <0x1b>;
 772                 status = "okay";
 773
 774                 /* Regulators */
 775                 IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
 776                 AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
 777                 DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
 778                 DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
 779         };
 780 };
 781
 782 &epwmss0 {
 783         status = "okay";
 784 };
 785
 786 &tscadc {
 787         status = "okay";
 788
 789         adc {
 790                 ti,adc-channels = <0 1 2 3 4 5 6 7>;
 791         };
 792 };
 793
 794 &ecap0 {
 795         status = "okay";
 796         pinctrl-names = "default";
 797         pinctrl-0 = <&ecap0_pins>;
 798 };
 799
 800 &gpio0 {
 801         pinctrl-names = "default";
 802         pinctrl-0 = <&gpio0_pins>;
 803         status = "okay";
 804
 805         p23 {
 806                 gpio-hog;
 807                 gpios = <23 GPIO_ACTIVE_HIGH>;
 808                 /* SelEMMCorNAND selects between eMMC and NAND:
 809                  * Low: NAND
 810                  * High: eMMC
 811                  * When changing this line make sure the newly
 812                  * selected device node is enabled and the previously
 813                  * selected device node is disabled.
 814                  */
 815                 output-low;
 816                 line-name = "SelEMMCorNAND";
 817         };
 818 };
 819
 820 &gpio1 {
 821         status = "okay";
 822 };
 823
 824 &gpio3 {
 825         status = "okay";
 826 };
 827
 828 &gpio4 {
 829         status = "okay";
 830 };
 831
 832 &gpio5 {
 833         pinctrl-names = "default";
 834         pinctrl-0 = <&display_mux_pins>;
 835         status = "okay";
 836         ti,no-reset-on-init;
 837
 838         p8 {
 839                 /*
 840                  * SelLCDorHDMI selects between display and audio paths:
 841                  * Low: HDMI display with audio via HDMI
 842                  * High: LCD display with analog audio via aic3111 codec
 843                  */
 844                 gpio-hog;
 845                 gpios = <8 GPIO_ACTIVE_HIGH>;
 846                 output-high;
 847                 line-name = "SelLCDorHDMI";
 848         };
 849 };
 850
 851 &mmc1 {
 852         status = "okay";
 853         vmmc-supply = <&evm_v3_3d>;
 854         bus-width = <4>;
 855         pinctrl-names = "default";
 856         pinctrl-0 = <&mmc1_pins>;
 857         cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 858 };
 859
 860 /* eMMC sits on mmc2 */
 861 &mmc2 {
 862         /*
 863          * When enabling eMMC, disable GPMC/NAND and set
 864          * SelEMMCorNAND to output-high
 865          */
 866         status = "disabled";
 867         vmmc-supply = <&evm_v3_3d>;
 868         bus-width = <8>;
 869         pinctrl-names = "default", "sleep";
 870         pinctrl-0 = <&emmc_pins_default>;
 871         pinctrl-1 = <&emmc_pins_sleep>;
 872         ti,non-removable;
 873 };
 874
 875 &mmc3 {
 876         status = "okay";
 877         /* these are on the crossbar and are outlined in the
 878            xbar-event-map element */
 879         dmas = <&edma_xbar 30 0 1>,
 880                 <&edma_xbar 31 0 2>;
 881         dma-names = "tx", "rx";
 882         vmmc-supply = <&vmmcwl_fixed>;
 883         bus-width = <4>;
 884         pinctrl-names = "default", "sleep";
 885         pinctrl-0 = <&mmc3_pins_default>;
 886         pinctrl-1 = <&mmc3_pins_sleep>;
 887         cap-power-off-card;
 888         keep-power-in-suspend;
 889         ti,non-removable;
 890
 891         #address-cells = <1>;
 892         #size-cells = <0>;
 893         wlcore: wlcore@0 {
 894                 compatible = "ti,wl1835";
 895                 reg = <2>;
 896                 interrupt-parent = <&gpio1>;
 897                 interrupts = <23 IRQ_TYPE_EDGE_RISING>;
 898         };
 899 };
 900
 901 &uart3 {
 902         status = "okay";
 903         pinctrl-names = "default";
 904         pinctrl-0 = <&uart3_pins>;
 905 };
 906
 907 &usb2_phy1 {
 908         status = "okay";
 909 };
 910
 911 &usb1 {
 912         dr_mode = "otg";
 913         status = "okay";
 914 };
 915
 916 &usb2_phy2 {
 917         status = "okay";
 918 };
 919
 920 &usb2 {
 921         dr_mode = "host";
 922         status = "okay";
 923 };
 924
 925 &mac {
 926         slaves = <1>;
 927         pinctrl-names = "default", "sleep";
 928         pinctrl-0 = <&cpsw_default>;
 929         pinctrl-1 = <&cpsw_sleep>;
 930         status = "okay";
 931 };
 932
 933 &davinci_mdio {
 934         pinctrl-names = "default", "sleep";
 935         pinctrl-0 = <&davinci_mdio_default>;
 936         pinctrl-1 = <&davinci_mdio_sleep>;
 937         status = "okay";
 938
 939         ethphy0: ethernet-phy@0 {
 940                 reg = <0>;
 941         };
 942 };
 943
 944 &cpsw_emac0 {
 945         phy-handle = <&ethphy0>;
 946         phy-mode = "rgmii";
 947 };
 948
 949 &elm {
 950         status = "okay";
 951 };
 952
 953 &gpmc {
 954         /*
 955          * When enabling GPMC, disable eMMC and set
 956          * SelEMMCorNAND to output-low
 957          */
 958         status = "okay";
 959         pinctrl-names = "default";
 960         pinctrl-0 = <&nand_flash_x8>;
 961         ranges = <0 0 0x08000000 0x01000000>;   /* CS0 space. Min partition = 16MB */
 962         nand@0,0 {
 963                 compatible = "ti,omap2-nand";
 964                 reg = <0 0 4>;          /* device IO registers */
 965                 interrupt-parent = <&gpmc>;
 966                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 967                              <1 IRQ_TYPE_NONE>; /* termcount */
 968                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>;  /* gpmc_wait0 */
 969                 ti,nand-xfer-type = "prefetch-dma";
 970                 ti,nand-ecc-opt = "bch16";
 971                 ti,elm-id = <&elm>;
 972                 nand-bus-width = <8>;
 973                 gpmc,device-width = <1>;
 974                 gpmc,sync-clk-ps = <0>;
 975                 gpmc,cs-on-ns = <0>;
 976                 gpmc,cs-rd-off-ns = <40>;
 977                 gpmc,cs-wr-off-ns = <40>;
 978                 gpmc,adv-on-ns = <0>;
 979                 gpmc,adv-rd-off-ns = <25>;
 980                 gpmc,adv-wr-off-ns = <25>;
 981                 gpmc,we-on-ns = <0>;
 982                 gpmc,we-off-ns = <20>;
 983                 gpmc,oe-on-ns = <3>;
 984                 gpmc,oe-off-ns = <30>;
 985                 gpmc,access-ns = <30>;
 986                 gpmc,rd-cycle-ns = <40>;
 987                 gpmc,wr-cycle-ns = <40>;
 988                 gpmc,bus-turnaround-ns = <0>;
 989                 gpmc,cycle2cycle-delay-ns = <0>;
 990                 gpmc,clk-activation-ns = <0>;
 991                 gpmc,wr-access-ns = <40>;
 992                 gpmc,wr-data-mux-bus-ns = <0>;
 993                 /* MTD partition table */
 994                 /* All SPL-* partitions are sized to minimal length
 995                  * which can be independently programmable. For
 996                  * NAND flash this is equal to size of erase-block */
 997                 #address-cells = <1>;
 998                 #size-cells = <1>;
 999                 partition@0 {
1000                         label = "NAND.SPL";
1001                         reg = <0x00000000 0x00040000>;
1002                 };
1003                 partition@1 {
1004                         label = "NAND.SPL.backup1";
1005                         reg = <0x00040000 0x00040000>;
1006                 };
1007                 partition@2 {
1008                         label = "NAND.SPL.backup2";
1009                         reg = <0x00080000 0x00040000>;
1010                 };
1011                 partition@3 {
1012                         label = "NAND.SPL.backup3";
1013                         reg = <0x000c0000 0x00040000>;
1014                 };
1015                 partition@4 {
1016                         label = "NAND.u-boot-spl-os";
1017                         reg = <0x00100000 0x00080000>;
1018                 };
1019                 partition@5 {
1020                         label = "NAND.u-boot";
1021                         reg = <0x00180000 0x00100000>;
1022                 };
1023                 partition@6 {
1024                         label = "NAND.u-boot-env";
1025                         reg = <0x00280000 0x00040000>;
1026                 };
1027                 partition@7 {
1028                         label = "NAND.u-boot-env.backup1";
1029                         reg = <0x002c0000 0x00040000>;
1030                 };
1031                 partition@8 {
1032                         label = "NAND.kernel";
1033                         reg = <0x00300000 0x00700000>;
1034                 };
1035                 partition@9 {
1036                         label = "NAND.file-system";
1037                         reg = <0x00a00000 0x1f600000>;
1038                 };
1039         };
1040 };
1041
1042 &dss {
1043         status = "ok";
1044
1045         pinctrl-names = "default";
1046         pinctrl-0 = <&dss_pins>;
1047
1048         port {
1049                 dpi_out: endpoint {
1050                         remote-endpoint = <&lcd_in>;
1051                         data-lines = <24>;
1052                 };
1053         };
1054 };
1055
1056 &dcan0 {
1057         pinctrl-names = "default", "sleep";
1058         pinctrl-0 = <&dcan0_default>;
1059         pinctrl-1 = <&dcan0_sleep>;
1060         status = "okay";
1061 };
1062
1063 &dcan1 {
1064         pinctrl-names = "default", "sleep";
1065         pinctrl-0 = <&dcan1_default>;
1066         pinctrl-1 = <&dcan1_sleep>;
1067         status = "okay";
1068 };
1069
1070 &vpfe0 {
1071         status = "okay";
1072         pinctrl-names = "default", "sleep";
1073         pinctrl-0 = <&vpfe0_pins_default>;
1074         pinctrl-1 = <&vpfe0_pins_sleep>;
1075
1076         port {
1077                 vpfe0_ep: endpoint {
1078                         remote-endpoint = <&ov2659_1>;
1079                         ti,am437x-vpfe-interface = <0>;
1080                         bus-width = <8>;
1081                         hsync-active = <0>;
1082                         vsync-active = <0>;
1083                 };
1084         };
1085 };
1086
1087 &vpfe1 {
1088         status = "okay";
1089         pinctrl-names = "default", "sleep";
1090         pinctrl-0 = <&vpfe1_pins_default>;
1091         pinctrl-1 = <&vpfe1_pins_sleep>;
1092
1093         port {
1094                 vpfe1_ep: endpoint {
1095                         remote-endpoint = <&ov2659_0>;
1096                         ti,am437x-vpfe-interface = <0>;
1097                         bus-width = <8>;
1098                         hsync-active = <0>;
1099                         vsync-active = <0>;
1100                 };
1101         };
1102 };
1103
1104 &mcasp1 {
1105         #sound-dai-cells = <0>;
1106         pinctrl-names = "default", "sleep";
1107         pinctrl-0 = <&mcasp1_pins>;
1108         pinctrl-1 = <&mcasp1_sleep_pins>;
1109
1110         status = "okay";
1111
1112         op-mode = <0>; /* MCASP_IIS_MODE */
1113         tdm-slots = <2>;
1114         /* 4 serializers */
1115         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
1116                 0 0 1 2
1117         >;
1118         tx-num-evt = <32>;
1119         rx-num-evt = <32>;
1120 };
1121
1122 &rtc {
1123         clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
1124         clock-names = "ext-clk", "int-clk";
1125         status = "okay";
1126 };
1127
1128 &cpu {
1129         cpu0-supply = <&dcdc2>;
1130 };