arch/arm/boot/dts/am437x-gp-evm.dts

   1 /*
   2  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /* AM437x GP EVM */
  10
  11 /dts-v1/;
  12
  13 #include "am4372.dtsi"
  14 #include <dt-bindings/pinctrl/am43xx.h>
  15 #include <dt-bindings/pwm/pwm.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17
  18 / {
  19         model = "TI AM437x GP EVM";
  20         compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
  21
  22         aliases {
  23                 display0 = &lcd0;
  24         };
  25
  26         vmmcsd_fixed: fixedregulator-sd {
  27                 compatible = "regulator-fixed";
  28                 regulator-name = "vmmcsd_fixed";
  29                 regulator-min-microvolt = <3300000>;
  30                 regulator-max-microvolt = <3300000>;
  31                 enable-active-high;
  32         };
  33
  34         vtt_fixed: fixedregulator-vtt {
  35                 compatible = "regulator-fixed";
  36                 regulator-name = "vtt_fixed";
  37                 regulator-min-microvolt = <1500000>;
  38                 regulator-max-microvolt = <1500000>;
  39                 regulator-always-on;
  40                 regulator-boot-on;
  41                 enable-active-high;
  42                 gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
  43         };
  44
  45         backlight {
  46                 compatible = "pwm-backlight";
  47                 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
  48                 brightness-levels = <0 51 53 56 62 75 101 152 255>;
  49                 default-brightness-level = <8>;
  50         };
  51
  52         matrix_keypad: matrix_keypad@0 {
  53                 compatible = "gpio-matrix-keypad";
  54                 debounce-delay-ms = <5>;
  55                 col-scan-delay-us = <2>;
  56
  57                 row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
  58                                 &gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
  59                                 &gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
  60
  61                 col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
  62                                 &gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
  63
  64                 linux,keymap = <0x00000201      /* P1 */
  65                                 0x00010202      /* P2 */
  66                                 0x01000067      /* UP */
  67                                 0x0101006a      /* RIGHT */
  68                                 0x02000069      /* LEFT */
  69                                 0x0201006c>;      /* DOWN */
  70                 };
  71
  72         lcd0: display {
  73                 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
  74                 label = "lcd";
  75
  76                 pinctrl-names = "default";
  77                 pinctrl-0 = <&lcd_pins>;
  78
  79                 /*
  80                  * SelLCDorHDMI, LOW to select HDMI. This is not really the
  81                  * panel's enable GPIO, but we don't have HDMI driver support nor
  82                  * support to switch between two displays, so using this gpio as
  83                  * panel's enable should be safe.
  84                  */
  85                 enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
  86
  87                 panel-timing {
  88                         clock-frequency = <33000000>;
  89                         hactive = <800>;
  90                         vactive = <480>;
  91                         hfront-porch = <210>;
  92                         hback-porch = <16>;
  93                         hsync-len = <30>;
  94                         vback-porch = <10>;
  95                         vfront-porch = <22>;
  96                         vsync-len = <13>;
  97                         hsync-active = <0>;
  98                         vsync-active = <0>;
  99                         de-active = <1>;
 100                         pixelclk-active = <1>;
 101                 };
 102
 103                 port {
 104                         lcd_in: endpoint {
 105                                 remote-endpoint = <&dpi_out>;
 106                         };
 107                 };
 108         };
 109 };
 110
 111 &am43xx_pinmux {
 112         i2c0_pins: i2c0_pins {
 113                 pinctrl-single,pins = <
 114                         0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_sda.i2c0_sda */
 115                         0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)  /* i2c0_scl.i2c0_scl */
 116                 >;
 117         };
 118
 119         i2c1_pins: i2c1_pins {
 120                 pinctrl-single,pins = <
 121                         0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_cs0.i2c1_scl */
 122                         0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2)  /* spi0_d1.i2c1_sda  */
 123                 >;
 124         };
 125
 126         mmc1_pins: pinmux_mmc1_pins {
 127                 pinctrl-single,pins = <
 128                         0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
 129                 >;
 130         };
 131
 132         ecap0_pins: backlight_pins {
 133                 pinctrl-single,pins = <
 134                         0x164 MUX_MODE0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
 135                 >;
 136         };
 137
 138         pixcir_ts_pins: pixcir_ts_pins {
 139                 pinctrl-single,pins = <
 140                         0x264 (PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
 141                 >;
 142         };
 143
 144         cpsw_default: cpsw_default {
 145                 pinctrl-single,pins = <
 146                         /* Slave 1 */
 147                         0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
 148                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rxctl */
 149                         0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
 150                         0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
 151                         0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
 152                         0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
 153                         0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
 154                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rmii1_rclk */
 155                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd3 */
 156                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd2 */
 157                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd1 */
 158                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd0 */
 159                 >;
 160         };
 161
 162         cpsw_sleep: cpsw_sleep {
 163                 pinctrl-single,pins = <
 164                         /* Slave 1 reset value */
 165                         0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 166                         0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 167                         0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 168                         0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 169                         0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 170                         0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 171                         0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 172                         0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 173                         0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 174                         0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 175                         0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 176                         0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 177                 >;
 178         };
 179
 180         davinci_mdio_default: davinci_mdio_default {
 181                 pinctrl-single,pins = <
 182                         /* MDIO */
 183                         0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
 184                         0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
 185                 >;
 186         };
 187
 188         davinci_mdio_sleep: davinci_mdio_sleep {
 189                 pinctrl-single,pins = <
 190                         /* MDIO reset value */
 191                         0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
 192                         0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
 193                 >;
 194         };
 195
 196         nand_flash_x8: nand_flash_x8 {
 197                 pinctrl-single,pins = <
 198                         0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* spi2_cs0.gpio/eMMCorNANDsel */
 199                         0x0  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
 200                         0x4  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
 201                         0x8  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
 202                         0xc  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
 203                         0x10 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
 204                         0x14 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
 205                         0x18 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
 206                         0x1c (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
 207                         0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
 208                         0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_wpn.gpmc_wpn */
 209                         0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
 210                         0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
 211                         0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
 212                         0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
 213                         0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
 214                 >;
 215         };
 216
 217         dss_pins: dss_pins {
 218                 pinctrl-single,pins = <
 219                         0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
 220                         0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 221                         0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 222                         0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
 223                         0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 224                         0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 225                         0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
 226                         0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
 227                         0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
 228                         0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 229                         0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 230                         0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
 231                         0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 232                         0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 233                         0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 234                         0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
 235                         0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 236                         0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 237                         0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 238                         0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
 239                         0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 240                         0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 241                         0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
 242                         0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
 243                         0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
 244                         0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
 245                         0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
 246                         0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
 247
 248                 >;
 249         };
 250
 251         lcd_pins: lcd_pins {
 252                 pinctrl-single,pins = <
 253                         /* GPIO 5_8 to select LCD / HDMI */
 254                         0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
 255                 >;
 256         };
 257 };
 258
 259 &i2c0 {
 260         status = "okay";
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&i2c0_pins>;
 263 };
 264
 265 &i2c1 {
 266         status = "okay";
 267         pinctrl-names = "default";
 268         pinctrl-0 = <&i2c1_pins>;
 269
 270         pixcir_ts@5c {
 271                 compatible = "pixcir,pixcir_tangoc";
 272                 pinctrl-names = "default";
 273                 pinctrl-0 = <&pixcir_ts_pins>;
 274                 reg = <0x5c>;
 275                 interrupt-parent = <&gpio3>;
 276                 interrupts = <22 0>;
 277
 278                 attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 279
 280                 x-size = <1024>;
 281                 y-size = <600>;
 282         };
 283 };
 284
 285 &epwmss0 {
 286         status = "okay";
 287 };
 288
 289 &ecap0 {
 290         status = "okay";
 291         pinctrl-names = "default";
 292         pinctrl-0 = <&ecap0_pins>;
 293 };
 294
 295 &gpio0 {
 296         status = "okay";
 297 };
 298
 299 &gpio3 {
 300         status = "okay";
 301 };
 302
 303 &gpio4 {
 304         status = "okay";
 305 };
 306
 307 &gpio5 {
 308         status = "okay";
 309         ti,no-reset-on-init;
 310 };
 311
 312 &mmc1 {
 313         status = "okay";
 314         vmmc-supply = <&vmmcsd_fixed>;
 315         bus-width = <4>;
 316         pinctrl-names = "default";
 317         pinctrl-0 = <&mmc1_pins>;
 318         cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 319 };
 320
 321 &usb2_phy1 {
 322         status = "okay";
 323 };
 324
 325 &usb1 {
 326         dr_mode = "peripheral";
 327         status = "okay";
 328 };
 329
 330 &usb2_phy2 {
 331         status = "okay";
 332 };
 333
 334 &usb2 {
 335         dr_mode = "host";
 336         status = "okay";
 337 };
 338
 339 &mac {
 340         slaves = <1>;
 341         pinctrl-names = "default", "sleep";
 342         pinctrl-0 = <&cpsw_default>;
 343         pinctrl-1 = <&cpsw_sleep>;
 344         status = "okay";
 345 };
 346
 347 &davinci_mdio {
 348         pinctrl-names = "default", "sleep";
 349         pinctrl-0 = <&davinci_mdio_default>;
 350         pinctrl-1 = <&davinci_mdio_sleep>;
 351         status = "okay";
 352 };
 353
 354 &cpsw_emac0 {
 355         phy_id = <&davinci_mdio>, <0>;
 356         phy-mode = "rgmii";
 357 };
 358
 359 &elm {
 360         status = "okay";
 361 };
 362
 363 &gpmc {
 364         status = "okay";
 365         pinctrl-names = "default";
 366         pinctrl-0 = <&nand_flash_x8>;
 367         ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
 368         nand@0,0 {
 369                 reg = <0 0 4>;          /* device IO registers */
 370                 ti,nand-ecc-opt = "bch8";
 371                 ti,elm-id = <&elm>;
 372                 nand-bus-width = <8>;
 373                 gpmc,device-width = <1>;
 374                 gpmc,sync-clk-ps = <0>;
 375                 gpmc,cs-on-ns = <0>;
 376                 gpmc,cs-rd-off-ns = <40>;
 377                 gpmc,cs-wr-off-ns = <40>;
 378                 gpmc,adv-on-ns = <0>;
 379                 gpmc,adv-rd-off-ns = <25>;
 380                 gpmc,adv-wr-off-ns = <25>;
 381                 gpmc,we-on-ns = <0>;
 382                 gpmc,we-off-ns = <20>;
 383                 gpmc,oe-on-ns = <3>;
 384                 gpmc,oe-off-ns = <30>;
 385                 gpmc,access-ns = <30>;
 386                 gpmc,rd-cycle-ns = <40>;
 387                 gpmc,wr-cycle-ns = <40>;
 388                 gpmc,wait-pin = <0>;
 389                 gpmc,wait-on-read;
 390                 gpmc,wait-on-write;
 391                 gpmc,bus-turnaround-ns = <0>;
 392                 gpmc,cycle2cycle-delay-ns = <0>;
 393                 gpmc,clk-activation-ns = <0>;
 394                 gpmc,wait-monitoring-ns = <0>;
 395                 gpmc,wr-access-ns = <40>;
 396                 gpmc,wr-data-mux-bus-ns = <0>;
 397                 /* MTD partition table */
 398                 /* All SPL-* partitions are sized to minimal length
 399                  * which can be independently programmable. For
 400                  * NAND flash this is equal to size of erase-block */
 401                 #address-cells = <1>;
 402                 #size-cells = <1>;
 403                 partition@0 {
 404                         label = "NAND.SPL";
 405                         reg = <0x00000000 0x00040000>;
 406                 };
 407                 partition@1 {
 408                         label = "NAND.SPL.backup1";
 409                         reg = <0x00040000 0x00040000>;
 410                 };
 411                 partition@2 {
 412                         label = "NAND.SPL.backup2";
 413                         reg = <0x00080000 0x00040000>;
 414                 };
 415                 partition@3 {
 416                         label = "NAND.SPL.backup3";
 417                         reg = <0x000c0000 0x00040000>;
 418                 };
 419                 partition@4 {
 420                         label = "NAND.u-boot-spl-os";
 421                         reg = <0x00100000 0x00080000>;
 422                 };
 423                 partition@5 {
 424                         label = "NAND.u-boot";
 425                         reg = <0x00180000 0x00100000>;
 426                 };
 427                 partition@6 {
 428                         label = "NAND.u-boot-env";
 429                         reg = <0x00280000 0x00040000>;
 430                 };
 431                 partition@7 {
 432                         label = "NAND.u-boot-env.backup1";
 433                         reg = <0x002c0000 0x00040000>;
 434                 };
 435                 partition@8 {
 436                         label = "NAND.kernel";
 437                         reg = <0x00300000 0x00700000>;
 438                 };
 439                 partition@9 {
 440                         label = "NAND.file-system";
 441                         reg = <0x00a00000 0x1f600000>;
 442                 };
 443         };
 444 };
 445
 446 &dss {
 447         status = "ok";
 448
 449         pinctrl-names = "default";
 450         pinctrl-0 = <&dss_pins>;
 451
 452         port {
 453                 dpi_out: endpoint@0 {
 454                         remote-endpoint = <&lcd_in>;
 455                         data-lines = <24>;
 456                 };
 457         };
 458 };