arch/arm/boot/dts/am335x-wega.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Phytec Messtechnik GmbH
   4  * Author: Teresa Remmet <t.remmet@phytec.de>
   5  */
   6
   7 / {
   8         model = "Phytec AM335x phyBOARD-WEGA";
   9         compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
  10
  11         sound: sound_iface {
  12                 compatible = "ti,da830-evm-audio";
  13         };
  14
  15         regulators {
  16                 compatible = "simple-bus";
  17
  18                 vcc3v3: fixedregulator1 {
  19                         compatible = "regulator-fixed";
  20                         regulator-name = "vcc3v3";
  21                         regulator-min-microvolt = <3300000>;
  22                         regulator-max-microvolt = <3300000>;
  23                         regulator-boot-on;
  24                 };
  25         };
  26 };
  27
  28 /* Audio */
  29 &am33xx_pinmux {
  30         mcasp0_pins: pinmux_mcasp0 {
  31                 pinctrl-single,pins = <
  32                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  33                         AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
  34                         AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
  35                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
  36                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  37                 >;
  38         };
  39 };
  40
  41 &i2c0 {
  42         tlv320aic3007: tlv320aic3007@18 {
  43                 compatible = "ti,tlv320aic3007";
  44                 reg = <0x18>;
  45                 AVDD-supply = <&vcc3v3>;
  46                 IOVDD-supply = <&vcc3v3>;
  47                 DRVDD-supply = <&vcc3v3>;
  48                 DVDD-supply = <&vdig1_reg>;
  49                 status = "okay";
  50         };
  51 };
  52
  53 &mcasp0 {
  54         pinctrl-names = "default";
  55         pinctrl-0 = <&mcasp0_pins>;
  56         op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
  57         tdm-slots = <2>;
  58         serial-dir = <
  59                 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */
  60         >;
  61         tx-num-evt = <16>;
  62         rt-num-evt = <16>;
  63         status = "okay";
  64 };
  65
  66 &sound {
  67         ti,model = "AM335x-Wega";
  68         ti,audio-codec = <&tlv320aic3007>;
  69         ti,mcasp-controller = <&mcasp0>;
  70         ti,audio-routing =
  71                 "Line Out",             "LLOUT",
  72                 "Line Out",             "RLOUT",
  73                 "LINE1L",               "Line In",
  74                 "LINE1R",               "Line In";
  75         clocks = <&mcasp0_fck>;
  76         clock-names = "mclk";
  77         status = "okay";
  78 };
  79
  80 /* CAN Busses */
  81 &am33xx_pinmux {
  82         dcan1_pins: pinmux_dcan1 {
  83                 pinctrl-single,pins = <
  84                         AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
  85                         AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
  86                 >;
  87         };
  88 };
  89
  90 &dcan1 {
  91         pinctrl-names = "default";
  92         pinctrl-0 = <&dcan1_pins>;
  93         status = "okay";
  94 };
  95
  96 /* Ethernet */
  97 &am33xx_pinmux {
  98         ethernet1_pins: pinmux_ethernet1 {
  99                 pinctrl-single,pins = <
 100                         AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a0.mii2_txen */
 101                         AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a1.mii2_rxdv */
 102                         AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a2.mii2_txd3 */
 103                         AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a3.mii2_txd2 */
 104                         AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a4.mii2_txd1 */
 105                         AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)               /* gpmc_a5.mii2_txd0 */
 106                         AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a6.mii2_txclk */
 107                         AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a7.mii2_rxclk */
 108                         AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a8.mii2_rxd3 */
 109                         AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* gpmc_a9.mii2_rxd2 */
 110                         AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_a10.mii2_rxd1 */
 111                         AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_a11.mii2_rxd0 */
 112                         AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* gpmc_wpn.mii2_rxerr */
 113                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1)     /* gpmc_ben1.mii2_col */
 114                 >;
 115         };
 116 };
 117
 118 &cpsw_emac1 {
 119         phy-handle = <&phy1>;
 120         phy-mode = "mii";
 121         dual_emac_res_vlan = <2>;
 122 };
 123
 124 &davinci_mdio {
 125         phy1: ethernet-phy@1 {
 126                 reg = <1>;
 127         };
 128 };
 129
 130 &mac {
 131         slaves = <2>;
 132         pinctrl-names = "default";
 133         pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
 134         dual_emac = <1>;
 135 };
 136
 137 /* MMC */
 138 &am33xx_pinmux {
 139         mmc1_pins: pinmux_mmc1 {
 140                 pinctrl-single,pins = <
 141                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
 142                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
 143                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
 144                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
 145                         AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
 146                         AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
 147                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)        /* spi0_cs1.mmc0_sdcd */
 148                 >;
 149         };
 150 };
 151
 152 &mmc1 {
 153         vmmc-supply = <&vcc3v3>;
 154         bus-width = <4>;
 155         pinctrl-names = "default";
 156         pinctrl-0 = <&mmc1_pins>;
 157         cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
 158         status = "okay";
 159 };
 160
 161 /* Power */
 162 &vdig1_reg {
 163         regulator-boot-on;
 164         regulator-always-on;
 165 };
 166
 167 /* UARTs */
 168 &am33xx_pinmux {
 169         uart0_pins: pinmux_uart0 {
 170                 pinctrl-single,pins = <
 171                         AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
 172                         AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 173                 >;
 174         };
 175
 176         uart1_pins: pinmux_uart1_pins {
 177                 pinctrl-single,pins = <
 178                         AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
 179                         AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 180                         AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
 181                         AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
 182                 >;
 183         };
 184 };
 185
 186 &uart0 {
 187         pinctrl-names = "default";
 188         pinctrl-0 = <&uart0_pins>;
 189         status = "okay";
 190 };
 191
 192 &uart1 {
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&uart1_pins>;
 195         status = "okay";
 196 };
 197
 198 /* USB */
 199 &cppi41dma {
 200         status = "okay";
 201 };
 202
 203 &usb_ctrl_mod {
 204         status = "okay";
 205 };
 206
 207 &usb {
 208         status = "okay";
 209 };
 210
 211 &usb0 {
 212         status = "okay";
 213 };
 214
 215 &usb0_phy {
 216         status = "okay";
 217 };
 218
 219 &usb1 {
 220         dr_mode = "host";
 221         status = "okay";
 222 };
 223
 224 &usb1_phy {
 225         status = "okay";
 226 };