arch/arm/boot/dts/am335x-phycore-som.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Phytec Messtechnik GmbH
   4  * Author: Teresa Remmet <t.remmet@phytec.de>
   5  */
   6
   7 #include "am33xx.dtsi"
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9
  10 / {
  11         model = "Phytec AM335x phyCORE";
  12         compatible = "phytec,am335x-phycore-som", "ti,am33xx";
  13
  14         aliases {
  15                 rtc0 = &i2c_rtc;
  16                 rtc1 = &rtc;
  17         };
  18
  19         cpus {
  20                 cpu@0 {
  21                         cpu0-supply = <&vdd1_reg>;
  22                 };
  23         };
  24
  25         memory@80000000 {
  26                 device_type = "memory";
  27                 reg = <0x80000000 0x10000000>; /* 256 MB */
  28         };
  29
  30         regulators {
  31                 compatible = "simple-bus";
  32
  33                 vcc5v: fixedregulator0 {
  34                         compatible = "regulator-fixed";
  35                         regulator-name = "vcc5v";
  36                         regulator-min-microvolt = <5000000>;
  37                         regulator-max-microvolt = <5000000>;
  38                         regulator-boot-on;
  39                         regulator-always-on;
  40                 };
  41         };
  42 };
  43
  44 /* Crypto Module */
  45 &aes {
  46         status = "okay";
  47 };
  48
  49 &sham {
  50         status = "okay";
  51 };
  52
  53 /* Ethernet */
  54 &am33xx_pinmux {
  55         ethernet0_pins: pinmux_ethernet0 {
  56                 pinctrl-single,pins = <
  57                         AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
  58                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1)
  59                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1)
  60                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1)
  61                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1)
  62                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)
  63                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)
  64                         AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
  65                 >;
  66         };
  67
  68         mdio_pins: pinmux_mdio {
  69                 pinctrl-single,pins = <
  70                         /* MDIO */
  71                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
  72                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
  73                 >;
  74         };
  75 };
  76
  77 &cpsw_emac0 {
  78         phy-handle = <&phy0>;
  79         phy-mode = "rmii";
  80         dual_emac_res_vlan = <1>;
  81 };
  82
  83 &davinci_mdio {
  84         pinctrl-names = "default";
  85         pinctrl-0 = <&mdio_pins>;
  86         status = "okay";
  87
  88         phy0: ethernet-phy@0 {
  89                 reg = <0>;
  90         };
  91 };
  92
  93 &mac {
  94         slaves = <1>;
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&ethernet0_pins>;
  97         status = "okay";
  98 };
  99
 100 /* I2C Busses */
 101 &am33xx_pinmux {
 102         i2c0_pins: pinmux_i2c0 {
 103                 pinctrl-single,pins = <
 104                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
 105                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
 106                 >;
 107         };
 108 };
 109
 110 &i2c0 {
 111         pinctrl-names = "default";
 112         pinctrl-0 = <&i2c0_pins>;
 113         clock-frequency = <400000>;
 114         status = "okay";
 115
 116         tps: pmic@2d {
 117                 reg = <0x2d>;
 118         };
 119
 120         i2c_tmp102: temp@4b {
 121                 compatible = "ti,tmp102";
 122                 reg = <0x4b>;
 123                 status = "disabled";
 124         };
 125
 126         i2c_eeprom: eeprom@52 {
 127                 compatible = "atmel,24c32";
 128                 pagesize = <32>;
 129                 reg = <0x52>;
 130                 status = "disabled";
 131         };
 132
 133         i2c_rtc: rtc@68 {
 134                 compatible = "microcrystal,rv4162";
 135                 reg = <0x68>;
 136                 status = "disabled";
 137         };
 138 };
 139
 140 /* NAND memory */
 141 &am33xx_pinmux {
 142                 nandflash_pins: pinmux_nandflash {
 143                         pinctrl-single,pins = <
 144                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
 145                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
 146                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
 147                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
 148                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
 149                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
 150                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
 151                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
 152                         AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
 153                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
 154                         AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
 155                         AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
 156                         AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
 157                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
 158                 >;
 159         };
 160 };
 161
 162 &elm {
 163         status = "okay";
 164 };
 165
 166 &gpmc {
 167         status = "okay";
 168         pinctrl-names = "default";
 169         pinctrl-0 = <&nandflash_pins>;
 170         ranges = <0 0 0x08000000 0x1000000>;   /* CS0: NAND */
 171         nandflash: nand@0,0 {
 172                 compatible = "ti,omap2-nand";
 173                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 174                 interrupt-parent = <&gpmc>;
 175                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 176                              <1 IRQ_TYPE_NONE>; /* termcount */
 177                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 178                 nand-bus-width = <8>;
 179                 ti,nand-ecc-opt = "bch8";
 180                 gpmc,device-nand = "true";
 181                 gpmc,device-width = <1>;
 182                 gpmc,sync-clk-ps = <0>;
 183                 gpmc,cs-on-ns = <0>;
 184                 gpmc,cs-rd-off-ns = <30>;
 185                 gpmc,cs-wr-off-ns = <30>;
 186                 gpmc,adv-on-ns = <0>;
 187                 gpmc,adv-rd-off-ns = <30>;
 188                 gpmc,adv-wr-off-ns = <30>;
 189                 gpmc,we-on-ns = <0>;
 190                 gpmc,we-off-ns = <20>;
 191                 gpmc,oe-on-ns = <10>;
 192                 gpmc,oe-off-ns = <30>;
 193                 gpmc,access-ns = <30>;
 194                 gpmc,rd-cycle-ns = <30>;
 195                 gpmc,wr-cycle-ns = <30>;
 196                 gpmc,bus-turnaround-ns = <0>;
 197                 gpmc,cycle2cycle-delay-ns = <50>;
 198                 gpmc,cycle2cycle-diffcsen;
 199                 gpmc,clk-activation-ns = <0>;
 200                 gpmc,wr-access-ns = <30>;
 201                 gpmc,wr-data-mux-bus-ns = <0>;
 202
 203                 ti,elm-id = <&elm>;
 204
 205                 #address-cells = <1>;
 206                 #size-cells = <1>;
 207         };
 208 };
 209
 210 /* Power */
 211 #include "tps65910.dtsi"
 212
 213 &tps {
 214         vcc1-supply = <&vcc5v>;
 215         vcc2-supply = <&vcc5v>;
 216         vcc3-supply = <&vcc5v>;
 217         vcc4-supply = <&vcc5v>;
 218         vcc5-supply = <&vcc5v>;
 219         vcc6-supply = <&vcc5v>;
 220         vcc7-supply = <&vcc5v>;
 221         vccio-supply = <&vcc5v>;
 222
 223         regulators {
 224                 vrtc_reg: regulator@0 {
 225                         regulator-always-on;
 226                 };
 227
 228                 vio_reg: regulator@1 {
 229                         regulator-always-on;
 230                 };
 231
 232                 vdd1_reg: regulator@2 {
 233                         /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
 234                         regulator-name = "vdd_mpu";
 235                         regulator-min-microvolt = <912500>;
 236                         regulator-max-microvolt = <1378000>;
 237                         regulator-boot-on;
 238                         regulator-always-on;
 239                 };
 240
 241                 vdd2_reg: regulator@3 {
 242                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 243                         regulator-name = "vdd_core";
 244                         regulator-min-microvolt = <912500>;
 245                         regulator-max-microvolt = <1150000>;
 246                         regulator-boot-on;
 247                         regulator-always-on;
 248                 };
 249
 250                 vdd3_reg: regulator@4 {
 251                         regulator-always-on;
 252                 };
 253
 254                 vdig1_reg: regulator@5 {
 255                         regulator-name = "vdig1_1p8v";
 256                         regulator-min-microvolt = <1800000>;
 257                         regulator-max-microvolt = <1800000>;
 258                 };
 259
 260                 vdig2_reg: regulator@6 {
 261                         regulator-always-on;
 262                 };
 263
 264                 vpll_reg: regulator@7 {
 265                         regulator-always-on;
 266                 };
 267
 268                 vdac_reg: regulator@8 {
 269                         regulator-always-on;
 270                 };
 271
 272                 vaux1_reg: regulator@9 {
 273                         regulator-always-on;
 274                 };
 275
 276                 vaux2_reg: regulator@10 {
 277                         regulator-always-on;
 278                 };
 279
 280                 vaux33_reg: regulator@11 {
 281                         regulator-always-on;
 282                 };
 283
 284                 vmmc_reg: regulator@12 {
 285                         regulator-min-microvolt = <3300000>;
 286                         regulator-max-microvolt = <3300000>;
 287                         regulator-always-on;
 288                 };
 289         };
 290 };
 291
 292 /* SPI Busses */
 293 &am33xx_pinmux {
 294         spi0_pins: pinmux_spi0 {
 295                 pinctrl-single,pins = <
 296                         AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
 297                         AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0)
 298                         AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
 299                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
 300                 >;
 301         };
 302 };
 303
 304 &spi0 {
 305         pinctrl-names = "default";
 306         pinctrl-0 = <&spi0_pins>;
 307         status = "okay";
 308
 309         serial_flash: m25p80@0 {
 310                 compatible = "jedec,spi-nor";
 311                 spi-max-frequency = <48000000>;
 312                 reg = <0x0>;
 313                 m25p,fast-read;
 314                 status = "disabled";
 315                 #address-cells = <1>;
 316                 #size-cells = <1>;
 317         };
 318 };