Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
[sfrench/cifs-2.6.git] / arch / arm / boot / dts / am335x-evmsk.dts
1 /*
2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8
9 /*
10  * AM335x Starter Kit
11  * http://www.ti.com/tool/tmdssk3358
12  */
13
14 /dts-v1/;
15
16 #include "am33xx.dtsi"
17 #include <dt-bindings/pwm/pwm.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19
20 / {
21         model = "TI AM335x EVM-SK";
22         compatible = "ti,am335x-evmsk", "ti,am33xx";
23
24         cpus {
25                 cpu@0 {
26                         cpu0-supply = <&vdd1_reg>;
27                 };
28         };
29
30         memory@80000000 {
31                 device_type = "memory";
32                 reg = <0x80000000 0x10000000>; /* 256 MB */
33         };
34
35         chosen {
36                 stdout-path = &uart0;
37         };
38
39         vbat: fixedregulator0 {
40                 compatible = "regulator-fixed";
41                 regulator-name = "vbat";
42                 regulator-min-microvolt = <5000000>;
43                 regulator-max-microvolt = <5000000>;
44                 regulator-boot-on;
45         };
46
47         lis3_reg: fixedregulator1 {
48                 compatible = "regulator-fixed";
49                 regulator-name = "lis3_reg";
50                 regulator-boot-on;
51         };
52
53         wl12xx_vmmc: fixedregulator2 {
54                 pinctrl-names = "default";
55                 pinctrl-0 = <&wl12xx_gpio>;
56                 compatible = "regulator-fixed";
57                 regulator-name = "vwl1271";
58                 regulator-min-microvolt = <1800000>;
59                 regulator-max-microvolt = <1800000>;
60                 gpio = <&gpio1 29 0>;
61                 startup-delay-us = <70000>;
62                 enable-active-high;
63         };
64
65         vtt_fixed: fixedregulator3 {
66                 compatible = "regulator-fixed";
67                 regulator-name = "vtt";
68                 regulator-min-microvolt = <1500000>;
69                 regulator-max-microvolt = <1500000>;
70                 gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>;
71                 regulator-always-on;
72                 regulator-boot-on;
73                 enable-active-high;
74         };
75
76         /* TPS79518 */
77         v1_8d_reg: fixedregulator-v1_8d {
78                 compatible = "regulator-fixed";
79                 regulator-name = "v1_8d";
80                 vin-supply = <&vbat>;
81                 regulator-min-microvolt = <1800000>;
82                 regulator-max-microvolt = <1800000>;
83         };
84
85         /* TPS78633 */
86         v3_3d_reg: fixedregulator-v3_3d {
87                 compatible = "regulator-fixed";
88                 regulator-name = "v3_3d";
89                 vin-supply = <&vbat>;
90                 regulator-min-microvolt = <3300000>;
91                 regulator-max-microvolt = <3300000>;
92         };
93
94         leds {
95                 pinctrl-names = "default";
96                 pinctrl-0 = <&user_leds_s0>;
97
98                 compatible = "gpio-leds";
99
100                 led1 {
101                         label = "evmsk:green:usr0";
102                         gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
103                         default-state = "off";
104                 };
105
106                 led2 {
107                         label = "evmsk:green:usr1";
108                         gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
109                         default-state = "off";
110                 };
111
112                 led3 {
113                         label = "evmsk:green:mmc0";
114                         gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
115                         linux,default-trigger = "mmc0";
116                         default-state = "off";
117                 };
118
119                 led4 {
120                         label = "evmsk:green:heartbeat";
121                         gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
122                         linux,default-trigger = "heartbeat";
123                         default-state = "off";
124                 };
125         };
126
127         gpio_buttons: gpio_buttons0 {
128                 compatible = "gpio-keys";
129                 #address-cells = <1>;
130                 #size-cells = <0>;
131
132                 switch1 {
133                         label = "button0";
134                         linux,code = <0x100>;
135                         gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
136                 };
137
138                 switch2 {
139                         label = "button1";
140                         linux,code = <0x101>;
141                         gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
142                 };
143
144                 switch3 {
145                         label = "button2";
146                         linux,code = <0x102>;
147                         gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
148                         wakeup-source;
149                 };
150
151                 switch4 {
152                         label = "button3";
153                         linux,code = <0x103>;
154                         gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
155                 };
156         };
157
158         lcd_bl: backlight {
159                 compatible = "pwm-backlight";
160                 pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>;
161                 brightness-levels = <0 58 61 66 75 90 125 170 255>;
162                 default-brightness-level = <8>;
163         };
164
165         sound {
166                 compatible = "simple-audio-card";
167                 simple-audio-card,name = "AM335x-EVMSK";
168                 simple-audio-card,widgets =
169                         "Headphone", "Headphone Jack";
170                 simple-audio-card,routing =
171                         "Headphone Jack",       "HPLOUT",
172                         "Headphone Jack",       "HPROUT";
173                 simple-audio-card,format = "dsp_b";
174                 simple-audio-card,bitclock-master = <&sound_master>;
175                 simple-audio-card,frame-master = <&sound_master>;
176                 simple-audio-card,bitclock-inversion;
177
178                 simple-audio-card,cpu {
179                         sound-dai = <&mcasp1>;
180                 };
181
182                 sound_master: simple-audio-card,codec {
183                         sound-dai = <&tlv320aic3106>;
184                         system-clock-frequency = <24000000>;
185                 };
186         };
187
188         panel {
189                 compatible = "ti,tilcdc,panel";
190                 pinctrl-names = "default", "sleep";
191                 pinctrl-0 = <&lcd_pins_default>;
192                 pinctrl-1 = <&lcd_pins_sleep>;
193                 backlight = <&lcd_bl>;
194                 status = "okay";
195                 panel-info {
196                         ac-bias         = <255>;
197                         ac-bias-intrpt  = <0>;
198                         dma-burst-sz    = <16>;
199                         bpp             = <32>;
200                         fdd             = <0x80>;
201                         sync-edge       = <0>;
202                         sync-ctrl       = <1>;
203                         raster-order    = <0>;
204                         fifo-th         = <0>;
205                 };
206                 display-timings {
207                         480x272 {
208                                 hactive         = <480>;
209                                 vactive         = <272>;
210                                 hback-porch     = <43>;
211                                 hfront-porch    = <8>;
212                                 hsync-len       = <4>;
213                                 vback-porch     = <12>;
214                                 vfront-porch    = <4>;
215                                 vsync-len       = <10>;
216                                 clock-frequency = <9000000>;
217                                 hsync-active    = <0>;
218                                 vsync-active    = <0>;
219                         };
220                 };
221         };
222 };
223
224 &am33xx_pinmux {
225         pinctrl-names = "default";
226         pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
227
228         lcd_pins_default: lcd_pins_default {
229                 pinctrl-single,pins = <
230                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)      /* gpmc_ad8.lcd_data23 */
231                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)      /* gpmc_ad9.lcd_data22 */
232                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad10.lcd_data21 */
233                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad11.lcd_data20 */
234                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad12.lcd_data19 */
235                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad13.lcd_data18 */
236                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad14.lcd_data17 */
237                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)     /* gpmc_ad15.lcd_data16 */
238                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)
239                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)
240                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)
241                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)
242                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)
243                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)
244                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)
245                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)
246                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)
247                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)
248                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)
249                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)
250                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)
251                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)
252                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)
253                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)
254                         AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)
255                         AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)
256                         AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)
257                         AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)
258                 >;
259         };
260
261         lcd_pins_sleep: lcd_pins_sleep {
262                 pinctrl-single,pins = <
263                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad8.lcd_data23 */
264                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* gpmc_ad9.lcd_data22 */
265                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad10.lcd_data21 */
266                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad11.lcd_data20 */
267                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad12.lcd_data19 */
268                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad13.lcd_data18 */
269                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad14.lcd_data17 */
270                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad15.lcd_data16 */
271                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)
272                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)
273                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)
274                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)
275                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)
276                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)
277                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)
278                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)
279                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)
280                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)
281                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)
282                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)
283                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)
284                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)
285                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)
286                         AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)
287                         AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
288                         AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)
289                         AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
290                         AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
291                 >;
292         };
293
294
295         user_leds_s0: user_leds_s0 {
296                 pinctrl-single,pins = <
297                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad4.gpio1_4 */
298                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad5.gpio1_5 */
299                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad6.gpio1_6 */
300                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)     /* gpmc_ad7.gpio1_7 */
301                 >;
302         };
303
304         gpio_keys_s0: gpio_keys_s0 {
305                 pinctrl-single,pins = <
306                         AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7)  /* gpmc_oen_ren.gpio2_3 */
307                         AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
308                         AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)    /* gpmc_wait0.gpio0_30 */
309                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
310                 >;
311         };
312
313         i2c0_pins: pinmux_i2c0_pins {
314                 pinctrl-single,pins = <
315                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
316                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
317                 >;
318         };
319
320         uart0_pins: pinmux_uart0_pins {
321                 pinctrl-single,pins = <
322                         AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
323                         AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
324                 >;
325         };
326
327         clkout2_pin: pinmux_clkout2_pin {
328                 pinctrl-single,pins = <
329                         AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)     /* xdma_event_intr1.clkout2 */
330                 >;
331         };
332
333         ecap2_pins: backlight_pins {
334                 pinctrl-single,pins = <
335                         AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4)        /* mcasp0_ahclkr.ecap2_in_pwm2_out */
336                 >;
337         };
338
339         cpsw_default: cpsw_default {
340                 pinctrl-single,pins = <
341                         /* Slave 1 */
342                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txen.rgmii1_tctl */
343                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxdv.rgmii1_rctl */
344                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
345                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
346                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
347                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
348                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)  /* mii1_txclk.rgmii1_tclk */
349                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)   /* mii1_rxclk.rgmii1_rclk */
350                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd3.rgmii1_rd3 */
351                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd2.rgmii1_rd2 */
352                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd1.rgmii1_rd1 */
353                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd0.rgmii1_rd0 */
354
355                         /* Slave 2 */
356                         AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a0.rgmii2_tctl */
357                         AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a1.rgmii2_rctl */
358                         AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a2.rgmii2_td3 */
359                         AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a3.rgmii2_td2 */
360                         AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a4.rgmii2_td1 */
361                         AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a5.rgmii2_td0 */
362                         AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a6.rgmii2_tclk */
363                         AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a7.rgmii2_rclk */
364                         AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a8.rgmii2_rd3 */
365                         AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a9.rgmii2_rd2 */
366                         AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a10.rgmii2_rd1 */
367                         AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a11.rgmii2_rd0 */
368                 >;
369         };
370
371         cpsw_sleep: cpsw_sleep {
372                 pinctrl-single,pins = <
373                         /* Slave 1 reset value */
374                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
375                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
376                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
377                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
378                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
379                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
380                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
381                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
382                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
383                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
384                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
385                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
386
387                         /* Slave 2 reset value*/
388                         AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
389                         AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
390                         AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
391                         AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
392                         AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
393                         AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
394                         AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
395                         AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
396                         AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
397                         AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
398                         AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
399                         AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
400                 >;
401         };
402
403         davinci_mdio_default: davinci_mdio_default {
404                 pinctrl-single,pins = <
405                         /* MDIO */
406                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
407                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
408                 >;
409         };
410
411         davinci_mdio_sleep: davinci_mdio_sleep {
412                 pinctrl-single,pins = <
413                         /* MDIO reset value */
414                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
415                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
416                 >;
417         };
418
419         mmc1_pins: pinmux_mmc1_pins {
420                 pinctrl-single,pins = <
421                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)               /* spi0_cs1.gpio0_6 */
422                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
423                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
424                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
425                         AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
426                         AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
427                         AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
428                         AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4)           /* mcasp0_aclkr.mmc0_sdwp */
429                 >;
430         };
431
432         mcasp1_pins: mcasp1_pins {
433                 pinctrl-single,pins = <
434                         AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
435                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
436                         AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */
437                         AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
438                 >;
439         };
440
441         mcasp1_pins_sleep: mcasp1_pins_sleep {
442                 pinctrl-single,pins = <
443                         AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
444                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)
445                         AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)
446                         AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
447                 >;
448         };
449
450         mmc2_pins: pinmux_mmc2_pins {
451                 pinctrl-single,pins = <
452                         AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */
453                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */
454                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
455                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
456                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
457                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
458                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
459                 >;
460         };
461
462         wl12xx_gpio: pinmux_wl12xx_gpio {
463                 pinctrl-single,pins = <
464                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */
465                 >;
466         };
467 };
468
469 &uart0 {
470         pinctrl-names = "default";
471         pinctrl-0 = <&uart0_pins>;
472
473         status = "okay";
474 };
475
476 &i2c0 {
477         pinctrl-names = "default";
478         pinctrl-0 = <&i2c0_pins>;
479
480         status = "okay";
481         clock-frequency = <400000>;
482
483         tps: tps@2d {
484                 reg = <0x2d>;
485         };
486
487         lis331dlh: lis331dlh@18 {
488                 compatible = "st,lis331dlh", "st,lis3lv02d";
489                 reg = <0x18>;
490                 Vdd-supply = <&lis3_reg>;
491                 Vdd_IO-supply = <&lis3_reg>;
492
493                 st,click-single-x;
494                 st,click-single-y;
495                 st,click-single-z;
496                 st,click-thresh-x = <10>;
497                 st,click-thresh-y = <10>;
498                 st,click-thresh-z = <10>;
499                 st,irq1-click;
500                 st,irq2-click;
501                 st,wakeup-x-lo;
502                 st,wakeup-x-hi;
503                 st,wakeup-y-lo;
504                 st,wakeup-y-hi;
505                 st,wakeup-z-lo;
506                 st,wakeup-z-hi;
507                 st,min-limit-x = <120>;
508                 st,min-limit-y = <120>;
509                 st,min-limit-z = <140>;
510                 st,max-limit-x = <550>;
511                 st,max-limit-y = <550>;
512                 st,max-limit-z = <750>;
513         };
514
515         tlv320aic3106: tlv320aic3106@1b {
516                 #sound-dai-cells = <0>;
517                 compatible = "ti,tlv320aic3106";
518                 reg = <0x1b>;
519                 status = "okay";
520
521                 /* Regulators */
522                 AVDD-supply = <&v3_3d_reg>;
523                 IOVDD-supply = <&v3_3d_reg>;
524                 DRVDD-supply = <&v3_3d_reg>;
525                 DVDD-supply = <&v1_8d_reg>;
526         };
527 };
528
529 &usb {
530         status = "okay";
531 };
532
533 &usb_ctrl_mod {
534         status = "okay";
535 };
536
537 &usb0_phy {
538         status = "okay";
539 };
540
541 &usb1_phy {
542         status = "okay";
543 };
544
545 &usb0 {
546         status = "okay";
547 };
548
549 &usb1 {
550         status = "okay";
551         dr_mode = "host";
552 };
553
554 &cppi41dma  {
555         status = "okay";
556 };
557
558 &epwmss2 {
559         status = "okay";
560
561         ecap2: ecap@100 {
562                 status = "okay";
563                 pinctrl-names = "default";
564                 pinctrl-0 = <&ecap2_pins>;
565         };
566 };
567
568 #include "tps65910.dtsi"
569
570 &tps {
571         vcc1-supply = <&vbat>;
572         vcc2-supply = <&vbat>;
573         vcc3-supply = <&vbat>;
574         vcc4-supply = <&vbat>;
575         vcc5-supply = <&vbat>;
576         vcc6-supply = <&vbat>;
577         vcc7-supply = <&vbat>;
578         vccio-supply = <&vbat>;
579
580         regulators {
581                 vrtc_reg: regulator@0 {
582                         regulator-always-on;
583                 };
584
585                 vio_reg: regulator@1 {
586                         regulator-always-on;
587                 };
588
589                 vdd1_reg: regulator@2 {
590                         /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
591                         regulator-name = "vdd_mpu";
592                         regulator-min-microvolt = <912500>;
593                         regulator-max-microvolt = <1351500>;
594                         regulator-boot-on;
595                         regulator-always-on;
596                 };
597
598                 vdd2_reg: regulator@3 {
599                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
600                         regulator-name = "vdd_core";
601                         regulator-min-microvolt = <912500>;
602                         regulator-max-microvolt = <1150000>;
603                         regulator-boot-on;
604                         regulator-always-on;
605                 };
606
607                 vdd3_reg: regulator@4 {
608                         regulator-always-on;
609                 };
610
611                 vdig1_reg: regulator@5 {
612                         regulator-always-on;
613                 };
614
615                 vdig2_reg: regulator@6 {
616                         regulator-always-on;
617                 };
618
619                 vpll_reg: regulator@7 {
620                         regulator-always-on;
621                 };
622
623                 vdac_reg: regulator@8 {
624                         regulator-always-on;
625                 };
626
627                 vaux1_reg: regulator@9 {
628                         regulator-always-on;
629                 };
630
631                 vaux2_reg: regulator@10 {
632                         regulator-always-on;
633                 };
634
635                 vaux33_reg: regulator@11 {
636                         regulator-always-on;
637                 };
638
639                 vmmc_reg: regulator@12 {
640                         regulator-min-microvolt = <1800000>;
641                         regulator-max-microvolt = <3300000>;
642                         regulator-always-on;
643                 };
644         };
645 };
646
647 &mac {
648         pinctrl-names = "default", "sleep";
649         pinctrl-0 = <&cpsw_default>;
650         pinctrl-1 = <&cpsw_sleep>;
651         dual_emac = <1>;
652         status = "okay";
653 };
654
655 &davinci_mdio {
656         pinctrl-names = "default", "sleep";
657         pinctrl-0 = <&davinci_mdio_default>;
658         pinctrl-1 = <&davinci_mdio_sleep>;
659         status = "okay";
660
661         ethphy0: ethernet-phy@0 {
662                 reg = <0>;
663         };
664
665         ethphy1: ethernet-phy@1 {
666                 reg = <1>;
667         };
668 };
669
670 &cpsw_emac0 {
671         phy-handle = <&ethphy0>;
672         phy-mode = "rgmii-id";
673         dual_emac_res_vlan = <1>;
674 };
675
676 &cpsw_emac1 {
677         phy-handle = <&ethphy1>;
678         phy-mode = "rgmii-id";
679         dual_emac_res_vlan = <2>;
680 };
681
682 &mmc1 {
683         status = "okay";
684         vmmc-supply = <&vmmc_reg>;
685         bus-width = <4>;
686         pinctrl-names = "default";
687         pinctrl-0 = <&mmc1_pins>;
688         cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
689 };
690
691 &sham {
692         status = "okay";
693 };
694
695 &aes {
696         status = "okay";
697 };
698
699 &gpio0 {
700         ti,no-reset-on-init;
701 };
702
703 &mmc2 {
704         status = "okay";
705         vmmc-supply = <&wl12xx_vmmc>;
706         ti,non-removable;
707         bus-width = <4>;
708         cap-power-off-card;
709         keep-power-in-suspend;
710         pinctrl-names = "default";
711         pinctrl-0 = <&mmc2_pins>;
712
713         #address-cells = <1>;
714         #size-cells = <0>;
715         wlcore: wlcore@2 {
716                 compatible = "ti,wl1271";
717                 reg = <2>;
718                 interrupt-parent = <&gpio0>;
719                 interrupts = <31 IRQ_TYPE_EDGE_RISING>; /* gpio 31 */
720                 ref-clock-frequency = <38400000>;
721         };
722 };
723
724 &mcasp1 {
725         #sound-dai-cells = <0>;
726         pinctrl-names = "default", "sleep";
727         pinctrl-0 = <&mcasp1_pins>;
728         pinctrl-1 = <&mcasp1_pins_sleep>;
729
730         status = "okay";
731
732         op-mode = <0>;          /* MCASP_IIS_MODE */
733         tdm-slots = <2>;
734         /* 4 serializers */
735         serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
736                 0 0 1 2
737         >;
738         tx-num-evt = <32>;
739         rx-num-evt = <32>;
740 };
741
742 &tscadc {
743         status = "okay";
744         tsc {
745                 ti,wires = <4>;
746                 ti,x-plate-resistance = <200>;
747                 ti,coordinate-readouts = <5>;
748                 ti,wire-config = <0x00 0x11 0x22 0x33>;
749         };
750 };
751
752 &lcdc {
753         status = "okay";
754
755         blue-and-red-wiring = "crossed";
756 };
757
758 &rtc {
759         clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
760         clock-names = "ext-clk", "int-clk";
761 };