arch/arm/boot/dts/am335x-baltos.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * VScom OnRISC
  11  * http://www.vscom.de
  12  */
  13
  14 #include "am33xx.dtsi"
  15 #include <dt-bindings/pwm/pwm.h>
  16 #include <dt-bindings/interrupt-controller/irq.h>
  17
  18 / {
  19         compatible = "vscom,onrisc", "ti,am33xx";
  20
  21         cpus {
  22                 cpu@0 {
  23                         cpu0-supply = <&vdd1_reg>;
  24                 };
  25         };
  26
  27         memory@80000000 {
  28                 device_type = "memory";
  29                 reg = <0x80000000 0x10000000>; /* 256 MB */
  30         };
  31
  32         vbat: fixedregulator0 {
  33                 compatible = "regulator-fixed";
  34                 regulator-name = "vbat";
  35                 regulator-min-microvolt = <5000000>;
  36                 regulator-max-microvolt = <5000000>;
  37                 regulator-boot-on;
  38         };
  39
  40         wl12xx_vmmc: fixedregulator2 {
  41                 pinctrl-names = "default";
  42                 pinctrl-0 = <&wl12xx_gpio>;
  43                 compatible = "regulator-fixed";
  44                 regulator-name = "vwl1271";
  45                 regulator-min-microvolt = <3300000>;
  46                 regulator-max-microvolt = <3300000>;
  47                 gpio = <&gpio3 8 0>;
  48                 startup-delay-us = <70000>;
  49                 enable-active-high;
  50         };
  51 };
  52
  53 &am33xx_pinmux {
  54         mmc2_pins: pinmux_mmc2_pins {
  55                 pinctrl-single,pins = <
  56                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_ad8.mmc1_dat0_mux0 */
  57                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_ad9.mmc1_dat1_mux0 */
  58                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_ad10.mmc1_dat2_mux0 */
  59                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_ad11.mmc1_dat3_mux0 */
  60                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_csn1.mmc1_clk_mux0 */
  61                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)      /* gpmc_csn2.mmc1_cmd_mux0 */
  62                         AM33XX_PADCONF(AM335X_PIN_EMU0, PIN_INPUT_PULLUP, MUX_MODE7)      /* emu0.gpio3[7] */
  63                 >;
  64         };
  65
  66         wl12xx_gpio: pinmux_wl12xx_gpio {
  67                 pinctrl-single,pins = <
  68                         AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT_PULLUP, MUX_MODE7)      /* emu1.gpio3[8] */
  69                 >;
  70         };
  71
  72         tps65910_pins: pinmux_tps65910_pins {
  73                 pinctrl-single,pins = <
  74                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE7)      /* gpmc_ben1.gpio1[28] */
  75                 >;
  76         };
  77
  78         i2c1_pins: pinmux_i2c1_pins {
  79                 pinctrl-single,pins = <
  80                         AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT, MUX_MODE2)      /* spi0_d1.i2c1_sda_mux3 */
  81                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT, MUX_MODE2)      /* spi0_cs0.i2c1_scl_mux3 */
  82                 >;
  83         };
  84
  85         uart0_pins: pinmux_uart0_pins {
  86                 pinctrl-single,pins = <
  87                         AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
  88                         AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  89                 >;
  90         };
  91
  92         cpsw_default: cpsw_default {
  93                 pinctrl-single,pins = <
  94                         /* Slave 1 */
  95                         AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)       /* mii1_crs.rmii1_crs_dv */
  96                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)      /* mii1_tx_en.rmii1_txen */
  97                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)      /* mii1_txd1.rmii1_txd1 */
  98                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)      /* mii1_txd0.rmii1_txd0 */
  99                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* mii1_rxd1.rmii1_rxd1 */
 100                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)      /* mii1_rxd0.rmii1_rxd0 */
 101                         AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)      /* rmii1_ref_clk.rmii1_refclk */
 102
 103
 104                         /* Slave 2 */
 105                         AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a0.rgmii2_tctl */
 106                         AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a1.rgmii2_rctl */
 107                         AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a2.rgmii2_td3 */
 108                         AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a3.rgmii2_td2 */
 109                         AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a4.rgmii2_td1 */
 110                         AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a5.rgmii2_td0 */
 111                         AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a6.rgmii2_tclk */
 112                         AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a7.rgmii2_rclk */
 113                         AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a8.rgmii2_rd3 */
 114                         AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)       /* gpmc_a9.rgmii2_rd2 */
 115                         AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a10.rgmii2_rd1 */
 116                         AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)      /* gpmc_a11.rgmii2_rd0 */
 117                 >;
 118         };
 119
 120         cpsw_sleep: cpsw_sleep {
 121                 pinctrl-single,pins = <
 122                         /* Slave 1 reset value */
 123                         AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)
 124                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
 125                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 126                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 127                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 128                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 129                         AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
 130
 131                         /* Slave 2 reset value*/
 132                         AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)
 133                         AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)
 134                         AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)
 135                         AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)
 136                         AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)
 137                         AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)
 138                         AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)
 139                         AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)
 140                         AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)
 141                         AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)
 142                         AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)
 143                         AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)
 144                 >;
 145         };
 146
 147         davinci_mdio_default: davinci_mdio_default {
 148                 pinctrl-single,pins = <
 149                         /* MDIO */
 150                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)    /* mdio_data.mdio_data */
 151                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)                    /* mdio_clk.mdio_clk */
 152                 >;
 153         };
 154
 155         davinci_mdio_sleep: davinci_mdio_sleep {
 156                 pinctrl-single,pins = <
 157                         /* MDIO reset value */
 158                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
 159                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
 160                 >;
 161         };
 162
 163         nandflash_pins_s0: nandflash_pins_s0 {
 164                 pinctrl-single,pins = <
 165                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad0.gpmc_ad0 */
 166                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad1.gpmc_ad1 */
 167                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad2.gpmc_ad2 */
 168                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad3.gpmc_ad3 */
 169                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad4.gpmc_ad4 */
 170                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad5.gpmc_ad5 */
 171                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad6.gpmc_ad6 */
 172                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)        /* gpmc_ad7.gpmc_ad7 */
 173                         AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)      /* gpmc_wait0.gpmc_wait0 */
 174                         AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)        /* gpmc_wpn.gpio0_30 */
 175                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)             /* gpmc_csn0.gpmc_csn0  */
 176                         AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)         /* gpmc_advn_ale.gpmc_advn_ale */
 177                         AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)          /* gpmc_oen_ren.gpmc_oen_ren */
 178                         AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)              /* gpmc_wen.gpmc_wen */
 179                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)         /* gpmc_be0n_cle.gpmc_be0n_cle */
 180                 >;
 181         };
 182 };
 183
 184 &elm {
 185         status = "okay";
 186 };
 187
 188 &gpmc {
 189         pinctrl-names = "default";
 190         pinctrl-0 = <&nandflash_pins_s0>;
 191         ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
 192         status = "okay";
 193
 194         nand@0,0 {
 195                 compatible = "ti,omap2-nand";
 196                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 197                 interrupt-parent = <&gpmc>;
 198                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 199                              <1 IRQ_TYPE_NONE>; /* termcount */
 200                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 201                 nand-bus-width = <8>;
 202                 ti,nand-ecc-opt = "bch8";
 203                 ti,nand-xfer-type = "polled";
 204
 205                 gpmc,device-nand = "true";
 206                 gpmc,device-width = <1>;
 207                 gpmc,sync-clk-ps = <0>;
 208                 gpmc,cs-on-ns = <0>;
 209                 gpmc,cs-rd-off-ns = <44>;
 210                 gpmc,cs-wr-off-ns = <44>;
 211                 gpmc,adv-on-ns = <6>;
 212                 gpmc,adv-rd-off-ns = <34>;
 213                 gpmc,adv-wr-off-ns = <44>;
 214                 gpmc,we-on-ns = <0>;
 215                 gpmc,we-off-ns = <40>;
 216                 gpmc,oe-on-ns = <0>;
 217                 gpmc,oe-off-ns = <54>;
 218                 gpmc,access-ns = <64>;
 219                 gpmc,rd-cycle-ns = <82>;
 220                 gpmc,wr-cycle-ns = <82>;
 221                 gpmc,bus-turnaround-ns = <0>;
 222                 gpmc,cycle2cycle-delay-ns = <0>;
 223                 gpmc,clk-activation-ns = <0>;
 224                 gpmc,wr-access-ns = <40>;
 225                 gpmc,wr-data-mux-bus-ns = <0>;
 226
 227                 #address-cells = <1>;
 228                 #size-cells = <1>;
 229                 ti,elm-id = <&elm>;
 230         };
 231 };
 232
 233 &uart0 {
 234         pinctrl-names = "default";
 235         pinctrl-0 = <&uart0_pins>;
 236
 237         status = "okay";
 238 };
 239
 240 &i2c1 {
 241         pinctrl-names = "default";
 242         pinctrl-0 = <&i2c1_pins>;
 243
 244         status = "okay";
 245         clock-frequency = <400000>;
 246
 247         tps: tps@2d {
 248                 reg = <0x2d>;
 249                 gpio-controller;
 250                 #gpio-cells = <2>;
 251                 interrupt-parent = <&gpio1>;
 252                 interrupts = <28 IRQ_TYPE_EDGE_RISING>;
 253                 pinctrl-names = "default";
 254                 pinctrl-0 = <&tps65910_pins>;
 255         };
 256
 257         at24@50 {
 258                 compatible = "atmel,24c02";
 259                 pagesize = <8>;
 260                 reg = <0x50>;
 261         };
 262 };
 263
 264 &usb {
 265         status = "okay";
 266 };
 267
 268 &usb_ctrl_mod {
 269         status = "okay";
 270 };
 271
 272 &cppi41dma  {
 273         status = "okay";
 274 };
 275
 276 #include "tps65910.dtsi"
 277
 278 &tps {
 279         vcc1-supply = <&vbat>;
 280         vcc2-supply = <&vbat>;
 281         vcc3-supply = <&vbat>;
 282         vcc4-supply = <&vbat>;
 283         vcc5-supply = <&vbat>;
 284         vcc6-supply = <&vbat>;
 285         vcc7-supply = <&vbat>;
 286         vccio-supply = <&vbat>;
 287
 288         ti,en-ck32k-xtal = <1>;
 289
 290         regulators {
 291                 vrtc_reg: regulator@0 {
 292                         regulator-always-on;
 293                 };
 294
 295                 vio_reg: regulator@1 {
 296                         regulator-always-on;
 297                 };
 298
 299                 vdd1_reg: regulator@2 {
 300                         /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
 301                         regulator-name = "vdd_mpu";
 302                         regulator-min-microvolt = <912500>;
 303                         regulator-max-microvolt = <1312500>;
 304                         regulator-boot-on;
 305                         regulator-always-on;
 306                 };
 307
 308                 vdd2_reg: regulator@3 {
 309                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 310                         regulator-name = "vdd_core";
 311                         regulator-min-microvolt = <912500>;
 312                         regulator-max-microvolt = <1150000>;
 313                         regulator-boot-on;
 314                         regulator-always-on;
 315                 };
 316
 317                 vdd3_reg: regulator@4 {
 318                         regulator-always-on;
 319                 };
 320
 321                 vdig1_reg: regulator@5 {
 322                         regulator-always-on;
 323                 };
 324
 325                 vdig2_reg: regulator@6 {
 326                         regulator-always-on;
 327                 };
 328
 329                 vpll_reg: regulator@7 {
 330                         regulator-always-on;
 331                 };
 332
 333                 vdac_reg: regulator@8 {
 334                         regulator-always-on;
 335                 };
 336
 337                 vaux1_reg: regulator@9 {
 338                         regulator-always-on;
 339                 };
 340
 341                 vaux2_reg: regulator@10 {
 342                         regulator-always-on;
 343                 };
 344
 345                 vaux33_reg: regulator@11 {
 346                         regulator-always-on;
 347                 };
 348
 349                 vmmc_reg: regulator@12 {
 350                         regulator-min-microvolt = <1800000>;
 351                         regulator-max-microvolt = <3300000>;
 352                         regulator-always-on;
 353                 };
 354         };
 355 };
 356
 357 &mac {
 358         pinctrl-names = "default", "sleep";
 359         pinctrl-0 = <&cpsw_default>;
 360         pinctrl-1 = <&cpsw_sleep>;
 361         dual_emac = <1>;
 362
 363         status = "okay";
 364 };
 365
 366 &davinci_mdio {
 367         status = "okay";
 368         pinctrl-names = "default", "sleep";
 369         pinctrl-0 = <&davinci_mdio_default>;
 370         pinctrl-1 = <&davinci_mdio_sleep>;
 371
 372         phy1: ethernet-phy@1 {
 373                 reg = <7>;
 374                 eee-broken-100tx;
 375                 eee-broken-1000t;
 376         };
 377 };
 378
 379 &mmc1 {
 380         vmmc-supply = <&vmmc_reg>;
 381         status = "okay";
 382 };
 383
 384 &mmc2 {
 385         status = "okay";
 386         vmmc-supply = <&wl12xx_vmmc>;
 387         ti,non-removable;
 388         bus-width = <4>;
 389         cap-power-off-card;
 390         pinctrl-names = "default";
 391         pinctrl-0 = <&mmc2_pins>;
 392
 393         #address-cells = <1>;
 394         #size-cells = <0>;
 395         wlcore: wlcore@2 {
 396                 compatible = "ti,wl1835";
 397                 reg = <2>;
 398                 interrupt-parent = <&gpio3>;
 399                 interrupts = <7 IRQ_TYPE_EDGE_RISING>;
 400         };
 401 };
 402
 403 &sham {
 404         status = "okay";
 405 };
 406
 407 &aes {
 408         status = "okay";
 409 };
 410
 411 &gpio0 {
 412         ti,no-reset-on-init;
 413 };
 414
 415 &gpio3 {
 416         ti,no-reset-on-init;
 417 };