arch/arm/boot/dts/am335x-baltos-ir2110.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   4  */
   5
   6 /*
   7  * VScom OnRISC
   8  * http://www.vscom.de
   9  */
  10
  11 /dts-v1/;
  12
  13 #include "am335x-baltos.dtsi"
  14 #include "am335x-baltos-leds.dtsi"
  15
  16 / {
  17         model = "OnRISC Baltos iR 2110";
  18 };
  19
  20 &am33xx_pinmux {
  21         uart1_pins: pinmux_uart1_pins {
  22                 pinctrl-single,pins = <
  23                         AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
  24                         AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)
  25                         AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
  26                         AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
  27                         AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)      /* lcd_vsync.gpio2[22] DTR */
  28                         AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_hsync.gpio2[23] DSR */
  29                         AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_pclk.gpio2[24] DCD */
  30                         AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)      /* lcd_ac_bias_en.gpio2[25] RI */
  31                 >;
  32         };
  33 };
  34
  35 &uart1 {
  36         pinctrl-names = "default";
  37         pinctrl-0 = <&uart1_pins>;
  38         dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
  39         dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
  40         dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
  41         rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
  42
  43         status = "okay";
  44 };
  45
  46 &usb0_phy {
  47         status = "okay";
  48 };
  49
  50 &usb0 {
  51         status = "okay";
  52         dr_mode = "host";
  53 };
  54
  55 &davinci_mdio {
  56         phy0: ethernet-phy@0 {
  57                 reg = <1>;
  58         };
  59 };
  60
  61 &cpsw_emac0 {
  62         phy-mode = "rmii";
  63         dual_emac_res_vlan = <1>;
  64         phy-handle = <&phy0>;
  65 };
  66
  67 &cpsw_emac1 {
  68         phy-mode = "rgmii-txid";
  69         dual_emac_res_vlan = <2>;
  70         phy-handle = <&phy1>;
  71 };